if_cemac.c revision 1.1.2.7
1 /* $NetBSD: if_cemac.c,v 1.1.2.7 2017/02/05 13:40:27 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.1.2.7 2017/02/05 13:40:27 skrll Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/kernel.h> 50 #include <sys/proc.h> 51 #include <sys/malloc.h> 52 #include <sys/time.h> 53 #include <sys/device.h> 54 #include <uvm/uvm_extern.h> 55 56 #include <sys/bus.h> 57 #include <machine/intr.h> 58 59 #include <arm/cpufunc.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_types.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #ifdef INET 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 #include <netinet/if_inarp.h> 76 #endif 77 78 #include <net/bpf.h> 79 #include <net/bpfdesc.h> 80 81 #ifdef IPKDB_AT91 // @@@ 82 #include <ipkdb/ipkdb.h> 83 #endif 84 85 #include <dev/cadence/cemacreg.h> 86 #include <dev/cadence/if_cemacvar.h> 87 88 #define DEFAULT_MDCDIV 32 89 90 #define CEMAC_READ(x) \ 91 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 92 #define CEMAC_WRITE(x, y) \ 93 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 94 #define CEMAC_GEM_WRITE(x, y) \ 95 do { \ 96 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 97 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 98 else \ 99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 100 } while(0) 101 102 #define RX_QLEN 64 103 #define TX_QLEN 2 /* I'm very sorry but that's where we can get */ 104 105 struct cemac_qmeta { 106 struct mbuf *m; 107 bus_dmamap_t m_dmamap; 108 }; 109 110 struct cemac_softc { 111 device_t sc_dev; 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_ioh; 114 bus_dma_tag_t sc_dmat; 115 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 116 struct ethercom sc_ethercom; 117 mii_data_t sc_mii; 118 119 void *rbqpage; 120 unsigned rbqlen; 121 bus_addr_t rbqpage_dsaddr; 122 bus_dmamap_t rbqpage_dmamap; 123 void *tbqpage; 124 unsigned tbqlen; 125 bus_addr_t tbqpage_dsaddr; 126 bus_dmamap_t tbqpage_dmamap; 127 128 volatile struct eth_dsc *RDSC; 129 int rxqi; 130 struct cemac_qmeta rxq[RX_QLEN]; 131 volatile struct eth_dsc *TDSC; 132 int txqi, txqc; 133 struct cemac_qmeta txq[TX_QLEN]; 134 callout_t cemac_tick_ch; 135 136 int cemac_flags; 137 }; 138 139 static void cemac_init(struct cemac_softc *); 140 static int cemac_gctx(struct cemac_softc *); 141 static int cemac_mediachange(struct ifnet *); 142 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 143 static int cemac_mii_readreg(device_t, int, int); 144 static void cemac_mii_writereg(device_t, int, int, int); 145 static void cemac_statchg(struct ifnet *); 146 static void cemac_tick(void *); 147 static int cemac_ifioctl(struct ifnet *, u_long, void *); 148 static void cemac_ifstart(struct ifnet *); 149 static void cemac_ifwatchdog(struct ifnet *); 150 static int cemac_ifinit(struct ifnet *); 151 static void cemac_ifstop(struct ifnet *, int); 152 static void cemac_setaddr(struct ifnet *); 153 154 #ifdef CEMAC_DEBUG 155 int cemac_debug = CEMAC_DEBUG; 156 #define DPRINTFN(n,fmt) if (cemac_debug >= (n)) printf fmt 157 #else 158 #define DPRINTFN(n,fmt) 159 #endif 160 161 CFATTACH_DECL_NEW(cemac, sizeof(struct cemac_softc), 162 cemac_match, cemac_attach, NULL, NULL); 163 164 int 165 cemac_match_common(device_t parent, cfdata_t match, void *aux) 166 { 167 if (strcmp(match->cf_name, "cemac") == 0) 168 return 1; 169 return 0; 170 } 171 172 void 173 cemac_attach_common(device_t self, bus_space_tag_t iot, 174 bus_space_handle_t ioh, bus_dma_tag_t dmat, int flags) 175 { 176 struct cemac_softc *sc = device_private(self); 177 prop_data_t enaddr; 178 uint32_t u; 179 180 181 sc->sc_dev = self; 182 sc->sc_ioh = ioh; 183 sc->sc_iot = iot; 184 sc->sc_dmat = dmat; 185 sc->cemac_flags = flags; 186 187 aprint_naive("\n"); 188 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 189 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 190 else 191 aprint_normal(": Cadence Ethernet Controller\n"); 192 193 /* configure emac: */ 194 CEMAC_WRITE(ETH_CTL, 0); // disable everything 195 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 196 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 197 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 198 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 199 CEMAC_WRITE(ETH_CFG, 200 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 201 else 202 CEMAC_WRITE(ETH_CFG, 203 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 204 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 205 //(void)CEMAC_READ(ETH_ISR); 206 u = CEMAC_READ(ETH_TSR); 207 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 208 | ETH_TSR_IDLE | ETH_TSR_RLE 209 | ETH_TSR_COL|ETH_TSR_OVR))); 210 u = CEMAC_READ(ETH_RSR); 211 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 212 213 /* Fetch the Ethernet address from property if set. */ 214 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 215 216 if (enaddr != NULL) { 217 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 218 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 219 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 220 ETHER_ADDR_LEN); 221 } else { 222 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 223 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 224 }; 225 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 226 } 227 228 cemac_init(sc); 229 } 230 231 static int 232 cemac_gctx(struct cemac_softc *sc) 233 { 234 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 235 uint32_t tsr; 236 237 tsr = CEMAC_READ(ETH_TSR); 238 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 239 // no space left 240 if (!(tsr & ETH_TSR_BNQ)) 241 return 0; 242 } else { 243 if (tsr & GEM_TSR_TXGO) 244 return 0; 245 } 246 CEMAC_WRITE(ETH_TSR, tsr); 247 248 // free sent frames 249 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 250 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 251 int bi = sc->txqi % TX_QLEN; 252 253 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 254 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 255 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 256 __FUNCTION__, bi, sc->TDSC[bi].Info)); 257 258 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 259 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 260 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 261 m_freem(sc->txq[bi].m); 262 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 263 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 264 sc->txq[bi].m = NULL; 265 sc->txqi = (bi + 1) % TX_QLEN; 266 sc->txqc--; 267 } 268 269 // mark we're free 270 if (ifp->if_flags & IFF_OACTIVE) { 271 ifp->if_flags &= ~IFF_OACTIVE; 272 /* Disable transmit-buffer-free interrupt */ 273 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 274 } 275 276 return 1; 277 } 278 279 int 280 cemac_intr(void *arg) 281 { 282 struct cemac_softc *sc = (struct cemac_softc *)arg; 283 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 284 uint32_t imr, isr, ctl; 285 #ifdef CEMAC_DEBUG 286 uint32_t rsr; 287 #endif 288 int bi; 289 290 imr = ~CEMAC_READ(ETH_IMR); 291 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR|ETH_ISR_TCOM))) { 292 // interrupt not enabled, can't be us 293 return 0; 294 } 295 296 isr = CEMAC_READ(ETH_ISR); 297 CEMAC_WRITE(ETH_ISR, isr); 298 isr &= imr; 299 #ifdef CEMAC_DEBUG 300 rsr = CEMAC_READ(ETH_RSR); // get receive status register 301 #endif 302 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 303 304 if (isr & ETH_ISR_RBNA) { // out of receive buffers 305 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 306 ctl = CEMAC_READ(ETH_CTL); // get current control register value 307 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 308 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 309 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 310 ifp->if_ierrors++; 311 ifp->if_ipackets++; 312 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 313 } 314 if (isr & ETH_ISR_ROVR) { 315 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 316 ifp->if_ierrors++; 317 ifp->if_ipackets++; 318 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 319 } 320 321 if (isr & ETH_ISR_RCOM) { // packet has been received! 322 uint32_t nfo; 323 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 324 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 325 int fl, csum; 326 struct mbuf *m; 327 328 nfo = sc->RDSC[bi].Info; 329 fl = (nfo & ETH_RDSC_I_LEN) - 4; 330 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 331 332 MGETHDR(m, M_DONTWAIT, MT_DATA); 333 if (m != NULL) MCLGET(m, M_DONTWAIT); 334 if (m != NULL && (m->m_flags & M_EXT)) { 335 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 336 MCLBYTES, BUS_DMASYNC_POSTREAD); 337 bus_dmamap_unload(sc->sc_dmat, 338 sc->rxq[bi].m_dmamap); 339 m_set_rcvif(sc->rxq[bi].m, ifp); 340 sc->rxq[bi].m->m_pkthdr.len = 341 sc->rxq[bi].m->m_len = fl; 342 switch (nfo & ETH_RDSC_I_CHKSUM) { 343 case ETH_RDSC_I_CHKSUM_IP: 344 csum = M_CSUM_IPv4; 345 break; 346 case ETH_RDSC_I_CHKSUM_UDP: 347 csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 348 M_CSUM_UDPv6; 349 break; 350 case ETH_RDSC_I_CHKSUM_TCP: 351 csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 352 M_CSUM_TCPv6; 353 break; 354 default: 355 csum = 0; 356 break; 357 } 358 sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 359 DPRINTFN(2,("received %u bytes packet\n", fl)); 360 if_percpuq_enqueue(ifp->if_percpuq, 361 sc->rxq[bi].m); 362 if (mtod(m, intptr_t) & 3) 363 m_adj(m, mtod(m, intptr_t) & 3); 364 sc->rxq[bi].m = m; 365 bus_dmamap_load(sc->sc_dmat, 366 sc->rxq[bi].m_dmamap, 367 m->m_ext.ext_buf, MCLBYTES, 368 NULL, BUS_DMA_NOWAIT); 369 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 370 MCLBYTES, BUS_DMASYNC_PREREAD); 371 sc->RDSC[bi].Info = 0; 372 sc->RDSC[bi].Addr = 373 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 374 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 375 } else { 376 /* Drop packets until we can get replacement 377 * empty mbufs for the RXDQ. 378 */ 379 if (m != NULL) 380 m_freem(m); 381 ifp->if_ierrors++; 382 } 383 sc->rxqi++; 384 } 385 } 386 387 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 388 cemac_ifstart(ifp); 389 #if 0 // reloop 390 irq = CEMAC_READ(IntStsC); 391 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 392 goto begin; 393 #endif 394 395 return (1); 396 } 397 398 399 static void 400 cemac_init(struct cemac_softc *sc) 401 { 402 bus_dma_segment_t segs; 403 int rsegs, err, i; 404 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 405 uint32_t u; 406 #if 0 407 int mdcdiv = DEFAULT_MDCDIV; 408 #endif 409 410 callout_init(&sc->cemac_tick_ch, 0); 411 412 // ok... 413 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 414 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 415 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 416 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 417 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 418 CEMAC_WRITE(ETH_CFG, 419 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 420 else 421 CEMAC_WRITE(ETH_CFG, 422 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 423 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 424 CEMAC_WRITE(GEM_DMA_CFG, 425 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 426 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 427 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 428 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 429 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 430 } 431 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 432 // (void)CEMAC_READ(ETH_ISR); 433 u = CEMAC_READ(ETH_TSR); 434 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 435 | ETH_TSR_IDLE | ETH_TSR_RLE 436 | ETH_TSR_COL|ETH_TSR_OVR))); 437 u = CEMAC_READ(ETH_RSR); 438 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 439 440 #if 0 441 if (device_cfdata(sc->sc_dev)->cf_flags) 442 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 443 #endif 444 /* set ethernet address */ 445 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 446 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 447 | (sc->sc_enaddr[0])); 448 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 449 | (sc->sc_enaddr[4])); 450 CEMAC_GEM_WRITE(SA2L, 0); 451 CEMAC_GEM_WRITE(SA2H, 0); 452 CEMAC_GEM_WRITE(SA3L, 0); 453 CEMAC_GEM_WRITE(SA3H, 0); 454 CEMAC_GEM_WRITE(SA4L, 0); 455 CEMAC_GEM_WRITE(SA4H, 0); 456 457 /* Allocate a page of memory for receive queue descriptors */ 458 sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 459 sc->rbqlen *= PAGE_SIZE; 460 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 461 462 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 463 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 464 &segs, 1, &rsegs, BUS_DMA_WAITOK); 465 if (err == 0) { 466 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 467 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 468 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 469 } 470 if (err == 0) { 471 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 472 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 473 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 474 &sc->rbqpage_dmamap); 475 } 476 if (err == 0) { 477 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 478 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 479 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 480 } 481 if (err != 0) 482 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 483 484 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 485 memset(sc->rbqpage, 0, sc->rbqlen); 486 487 /* Allocate a page of memory for transmit queue descriptors */ 488 sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 489 sc->tbqlen *= PAGE_SIZE; 490 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 491 492 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 493 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 494 &segs, 1, &rsegs, BUS_DMA_WAITOK); 495 if (err == 0) { 496 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 497 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 498 &sc->tbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 499 } 500 if (err == 0) { 501 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 502 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 503 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 504 &sc->tbqpage_dmamap); 505 } 506 if (err == 0) { 507 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 508 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 509 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 510 } 511 if (err != 0) 512 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 513 514 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 515 memset(sc->tbqpage, 0, sc->tbqlen); 516 517 /* Set up pointers to start of each queue in kernel addr space. 518 * Each descriptor queue or status queue entry uses 2 words 519 */ 520 sc->RDSC = (void *)sc->rbqpage; 521 sc->TDSC = (void *)sc->tbqpage; 522 523 /* init TX queue */ 524 for (i = 0; i < TX_QLEN; i++) { 525 sc->TDSC[i].Addr = 0; 526 sc->TDSC[i].Info = ETH_TDSC_I_USED | 527 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 528 } 529 530 /* Populate the RXQ with mbufs */ 531 sc->rxqi = 0; 532 for(i = 0; i < RX_QLEN; i++) { 533 struct mbuf *m; 534 535 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 536 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 537 if (err) { 538 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 539 } 540 MGETHDR(m, M_WAIT, MT_DATA); 541 MCLGET(m, M_WAIT); 542 sc->rxq[i].m = m; 543 if (mtod(m, intptr_t) & 3) { 544 m_adj(m, mtod(m, intptr_t) & 3); 545 } 546 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 547 m->m_ext.ext_buf, MCLBYTES, NULL, 548 BUS_DMA_WAITOK); 549 if (err) { 550 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 551 } 552 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 553 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 554 sc->RDSC[i].Info = 0; 555 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 556 MCLBYTES, BUS_DMASYNC_PREREAD); 557 } 558 559 /* prepare transmit queue */ 560 for (i = 0; i < TX_QLEN; i++) { 561 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 562 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 563 &sc->txq[i].m_dmamap); 564 if (err) 565 panic("ARGH #1"); 566 sc->txq[i].m = NULL; 567 } 568 569 /* Program each queue's start addr, cur addr, and len registers 570 * with the physical addresses. 571 */ 572 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 573 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 574 575 /* Divide HCLK by 32 for MDC clock */ 576 sc->sc_ethercom.ec_mii = &sc->sc_mii; 577 sc->sc_mii.mii_ifp = ifp; 578 sc->sc_mii.mii_readreg = cemac_mii_readreg; 579 sc->sc_mii.mii_writereg = cemac_mii_writereg; 580 sc->sc_mii.mii_statchg = cemac_statchg; 581 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, cemac_mediachange, 582 cemac_mediastatus); 583 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 584 MII_OFFSET_ANY, 0); 585 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 586 587 #if 0 588 // enable / disable interrupts 589 CEMAC_WRITE(ETH_IDR, -1); 590 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 591 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 592 // (void)CEMAC_READ(ETH_ISR); // why 593 594 // enable transmitter / receiver 595 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 596 | ETH_CTL_CSR | ETH_CTL_MPE); 597 #endif 598 /* 599 * We can support hardware checksumming. 600 */ 601 ifp->if_capabilities |= 602 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 603 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 604 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 605 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 606 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 607 608 /* 609 * We can support 802.1Q VLAN-sized frames. 610 */ 611 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 612 613 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 614 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 615 ifp->if_ioctl = cemac_ifioctl; 616 ifp->if_start = cemac_ifstart; 617 ifp->if_watchdog = cemac_ifwatchdog; 618 ifp->if_init = cemac_ifinit; 619 ifp->if_stop = cemac_ifstop; 620 ifp->if_timer = 0; 621 ifp->if_softc = sc; 622 IFQ_SET_READY(&ifp->if_snd); 623 if_attach(ifp); 624 ether_ifattach(ifp, (sc)->sc_enaddr); 625 } 626 627 static int 628 cemac_mediachange(struct ifnet *ifp) 629 { 630 if (ifp->if_flags & IFF_UP) 631 cemac_ifinit(ifp); 632 return (0); 633 } 634 635 static void 636 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 637 { 638 struct cemac_softc *sc = ifp->if_softc; 639 640 mii_pollstat(&sc->sc_mii); 641 ifmr->ifm_active = sc->sc_mii.mii_media_active; 642 ifmr->ifm_status = sc->sc_mii.mii_media_status; 643 } 644 645 646 static int 647 cemac_mii_readreg(device_t self, int phy, int reg) 648 { 649 struct cemac_softc *sc; 650 651 sc = device_private(self); 652 653 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 654 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 655 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 656 | ETH_MAN_CODE_IEEE802_3)); 657 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)); 658 659 return (CEMAC_READ(ETH_MAN) & ETH_MAN_DATA); 660 } 661 662 static void 663 cemac_mii_writereg(device_t self, int phy, int reg, int val) 664 { 665 struct cemac_softc *sc; 666 667 sc = device_private(self); 668 669 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 670 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 671 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 672 | ETH_MAN_CODE_IEEE802_3 673 | (val & ETH_MAN_DATA))); 674 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 675 } 676 677 678 static void 679 cemac_statchg(struct ifnet *ifp) 680 { 681 struct cemac_softc *sc = ifp->if_softc; 682 struct mii_data *mii = &sc->sc_mii; 683 uint32_t reg; 684 685 /* 686 * We must keep the MAC and the PHY in sync as 687 * to the status of full-duplex! 688 */ 689 reg = CEMAC_READ(ETH_CFG); 690 reg &= ~ETH_CFG_FD; 691 if (sc->sc_mii.mii_media_active & IFM_FDX) 692 reg |= ETH_CFG_FD; 693 694 reg &= ~ETH_CFG_SPD; 695 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 696 reg &= ~GEM_CFG_GEN; 697 switch (IFM_SUBTYPE(mii->mii_media_active)) { 698 case IFM_10_T: 699 break; 700 case IFM_100_TX: 701 reg |= ETH_CFG_SPD; 702 break; 703 case IFM_1000_T: 704 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 705 break; 706 default: 707 break; 708 } 709 CEMAC_WRITE(ETH_CFG, reg); 710 } 711 712 static void 713 cemac_tick(void *arg) 714 { 715 struct cemac_softc* sc = (struct cemac_softc *)arg; 716 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 717 int s; 718 719 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 720 ifp->if_collisions += CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL); 721 else 722 ifp->if_collisions += CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL); 723 724 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 725 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 726 uint32_t misses = CEMAC_READ(ETH_DRFC); 727 if (misses > 0) 728 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 729 } 730 731 s = splnet(); 732 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 733 cemac_ifstart(ifp); 734 splx(s); 735 736 mii_tick(&sc->sc_mii); 737 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 738 } 739 740 741 static int 742 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 743 { 744 struct cemac_softc *sc = ifp->if_softc; 745 struct ifreq *ifr = (struct ifreq *)data; 746 int s, error; 747 748 s = splnet(); 749 switch(cmd) { 750 case SIOCSIFMEDIA: 751 case SIOCGIFMEDIA: 752 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 753 break; 754 default: 755 error = ether_ioctl(ifp, cmd, data); 756 if (error != ENETRESET) 757 break; 758 error = 0; 759 760 if (cmd == SIOCSIFCAP) { 761 error = (*ifp->if_init)(ifp); 762 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 763 ; 764 else if (ifp->if_flags & IFF_RUNNING) { 765 cemac_setaddr(ifp); 766 } 767 } 768 splx(s); 769 return error; 770 } 771 772 static void 773 cemac_ifstart(struct ifnet *ifp) 774 { 775 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 776 struct mbuf *m; 777 bus_dma_segment_t *segs; 778 int s, bi, err, nsegs; 779 780 s = splnet(); 781 start: 782 if (cemac_gctx(sc) == 0) { 783 /* Enable transmit-buffer-free interrupt */ 784 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 785 ifp->if_flags |= IFF_OACTIVE; 786 ifp->if_timer = 10; 787 splx(s); 788 return; 789 } 790 791 ifp->if_timer = 0; 792 793 IFQ_POLL(&ifp->if_snd, m); 794 if (m == NULL) { 795 splx(s); 796 return; 797 } 798 799 bi = (sc->txqi + sc->txqc) % TX_QLEN; 800 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 801 BUS_DMA_NOWAIT)) || 802 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 803 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 804 /* Copy entire mbuf chain to new single */ 805 struct mbuf *mn; 806 807 if (err == 0) 808 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 809 810 MGETHDR(mn, M_DONTWAIT, MT_DATA); 811 if (mn == NULL) goto stop; 812 if (m->m_pkthdr.len > MHLEN) { 813 MCLGET(mn, M_DONTWAIT); 814 if ((mn->m_flags & M_EXT) == 0) { 815 m_freem(mn); 816 goto stop; 817 } 818 } 819 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 820 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 821 IFQ_DEQUEUE(&ifp->if_snd, m); 822 m_freem(m); 823 m = mn; 824 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 825 BUS_DMA_NOWAIT); 826 } else { 827 IFQ_DEQUEUE(&ifp->if_snd, m); 828 } 829 830 bpf_mtap(ifp, m); 831 832 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 833 segs = sc->txq[bi].m_dmamap->dm_segs; 834 if (nsegs > 1) 835 panic("#### ARGH #2"); 836 837 sc->txq[bi].m = m; 838 sc->txqc++; 839 840 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 841 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 842 (unsigned)m->m_pkthdr.len)); 843 #ifdef DIAGNOSTIC 844 if (sc->txqc > TX_QLEN) 845 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 846 #endif 847 848 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 849 sc->txq[bi].m_dmamap->dm_mapsize, 850 BUS_DMASYNC_PREWRITE); 851 852 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 853 sc->TDSC[bi].Addr = segs->ds_addr; 854 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 855 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 856 857 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 858 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 859 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 860 __FUNCTION__, bi, sc->TDSC[bi].Info)); 861 862 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 863 CEMAC_WRITE(ETH_CTL, ctl); 864 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 865 } else { 866 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 867 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 868 } 869 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 870 goto start; 871 stop: 872 873 splx(s); 874 return; 875 } 876 877 static void 878 cemac_ifwatchdog(struct ifnet *ifp) 879 { 880 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 881 882 if ((ifp->if_flags & IFF_RUNNING) == 0) 883 return; 884 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 885 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 886 } 887 888 static int 889 cemac_ifinit(struct ifnet *ifp) 890 { 891 struct cemac_softc *sc = ifp->if_softc; 892 uint32_t dma, cfg; 893 int s = splnet(); 894 895 callout_stop(&sc->cemac_tick_ch); 896 897 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 898 899 if (ifp->if_capenable & 900 (IFCAP_CSUM_IPv4_Tx | 901 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 902 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 903 dma = CEMAC_READ(GEM_DMA_CFG); 904 dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 905 CEMAC_WRITE(GEM_DMA_CFG, dma); 906 } 907 if (ifp->if_capenable & 908 (IFCAP_CSUM_IPv4_Rx | 909 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 910 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 911 cfg = CEMAC_READ(ETH_CFG); 912 cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN; 913 CEMAC_WRITE(ETH_CFG, cfg); 914 } 915 } 916 917 // enable interrupts 918 CEMAC_WRITE(ETH_IDR, -1); 919 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 920 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 921 922 // enable transmitter / receiver 923 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 924 | ETH_CTL_CSR | ETH_CTL_MPE); 925 926 mii_mediachg(&sc->sc_mii); 927 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 928 ifp->if_flags |= IFF_RUNNING; 929 splx(s); 930 return 0; 931 } 932 933 static void 934 cemac_ifstop(struct ifnet *ifp, int disable) 935 { 936 // uint32_t u; 937 struct cemac_softc *sc = ifp->if_softc; 938 939 #if 0 940 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 941 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 942 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 943 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 944 CEMAC_WRITE(ETH_CFG, 945 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 946 else 947 CEMAC_WRITE(ETH_CFG, 948 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 949 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 950 // (void)CEMAC_READ(ETH_ISR); 951 u = CEMAC_READ(ETH_TSR); 952 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 953 | ETH_TSR_IDLE | ETH_TSR_RLE 954 | ETH_TSR_COL|ETH_TSR_OVR))); 955 u = CEMAC_READ(ETH_RSR); 956 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 957 #endif 958 callout_stop(&sc->cemac_tick_ch); 959 960 /* Down the MII. */ 961 mii_down(&sc->sc_mii); 962 963 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 964 ifp->if_timer = 0; 965 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 966 } 967 968 static void 969 cemac_setaddr(struct ifnet *ifp) 970 { 971 struct cemac_softc *sc = ifp->if_softc; 972 struct ethercom *ac = &sc->sc_ethercom; 973 struct ether_multi *enm; 974 struct ether_multistep step; 975 uint8_t ias[3][ETHER_ADDR_LEN]; 976 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 977 uint32_t ctl = CEMAC_READ(ETH_CTL); 978 uint32_t cfg = CEMAC_READ(ETH_CFG); 979 980 /* disable receiver temporarily */ 981 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 982 983 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 984 985 if (ifp->if_flags & IFF_PROMISC) { 986 cfg |= ETH_CFG_CAF; 987 } else { 988 cfg &= ~ETH_CFG_CAF; 989 } 990 991 // ETH_CFG_BIG? 992 993 ifp->if_flags &= ~IFF_ALLMULTI; 994 995 ETHER_FIRST_MULTI(step, ac, enm); 996 while (enm != NULL) { 997 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 998 /* 999 * We must listen to a range of multicast addresses. 1000 * For now, just accept all multicasts, rather than 1001 * trying to set only those filter bits needed to match 1002 * the range. (At this time, the only use of address 1003 * ranges is for IP multicast routing, for which the 1004 * range is big enough to require all bits set.) 1005 */ 1006 cfg |= ETH_CFG_MTI; 1007 hashes[0] = 0xffffffffUL; 1008 hashes[1] = 0xffffffffUL; 1009 ifp->if_flags |= IFF_ALLMULTI; 1010 nma = 0; 1011 break; 1012 } 1013 1014 if (nma < 3) { 1015 /* We can program 3 perfect address filters for mcast */ 1016 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 1017 } else { 1018 /* 1019 * XXX: Datasheet is not very clear here, I'm not sure 1020 * if I'm doing this right. --joff 1021 */ 1022 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1023 1024 /* Just want the 6 most-significant bits. */ 1025 h = h >> 26; 1026 #if 0 1027 hashes[h / 32] |= (1 << (h % 32)); 1028 #else 1029 hashes[0] = 0xffffffffUL; 1030 hashes[1] = 0xffffffffUL; 1031 #endif 1032 cfg |= ETH_CFG_MTI; 1033 } 1034 ETHER_NEXT_MULTI(step, enm); 1035 nma++; 1036 } 1037 1038 // program... 1039 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1040 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 1041 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 1042 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 1043 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 1044 | (sc->sc_enaddr[0])); 1045 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 1046 | (sc->sc_enaddr[4])); 1047 if (nma > 0) { 1048 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1049 ias[0][0], ias[0][1], ias[0][2], 1050 ias[0][3], ias[0][4], ias[0][5])); 1051 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 1052 | (ias[0][2] << 16) | (ias[0][1] << 8) 1053 | (ias[0][0])); 1054 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 1055 | (ias[0][5])); 1056 } 1057 if (nma > 1) { 1058 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1059 ias[1][0], ias[1][1], ias[1][2], 1060 ias[1][3], ias[1][4], ias[1][5])); 1061 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1062 | (ias[1][2] << 16) | (ias[1][1] << 8) 1063 | (ias[1][0])); 1064 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1065 | (ias[1][5])); 1066 } 1067 if (nma > 2) { 1068 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1069 ias[2][0], ias[2][1], ias[2][2], 1070 ias[2][3], ias[2][4], ias[2][5])); 1071 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1072 | (ias[2][2] << 16) | (ias[2][1] << 8) 1073 | (ias[2][0])); 1074 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1075 | (ias[2][5])); 1076 } 1077 CEMAC_GEM_WRITE(HSH, hashes[0]); 1078 CEMAC_GEM_WRITE(HSL, hashes[1]); 1079 CEMAC_WRITE(ETH_CFG, cfg); 1080 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1081 } 1082
Indexes created Thu Oct 16 14:10:15 GMT 2025