if_cemac.c revision 1.13
1 /* $NetBSD: if_cemac.c,v 1.13 2018/06/26 06:48:00 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.13 2018/06/26 06:48:00 msaitoh Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/kernel.h> 50 #include <sys/proc.h> 51 #include <sys/malloc.h> 52 #include <sys/time.h> 53 #include <sys/device.h> 54 #include <uvm/uvm_extern.h> 55 56 #include <sys/bus.h> 57 #include <machine/intr.h> 58 59 #include <arm/cpufunc.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_types.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 #include <net/bpf.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #include <netinet/if_inarp.h> 77 #endif 78 79 #ifdef IPKDB_AT91 // @@@ 80 #include <ipkdb/ipkdb.h> 81 #endif 82 83 #include <dev/cadence/cemacreg.h> 84 #include <dev/cadence/if_cemacvar.h> 85 86 #define DEFAULT_MDCDIV 32 87 88 #define CEMAC_READ(x) \ 89 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 90 #define CEMAC_WRITE(x, y) \ 91 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 92 #define CEMAC_GEM_WRITE(x, y) \ 93 do { \ 94 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 95 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 96 else \ 97 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 98 } while(0) 99 100 #define RX_QLEN 64 101 #define TX_QLEN 2 /* I'm very sorry but that's where we can get */ 102 103 struct cemac_qmeta { 104 struct mbuf *m; 105 bus_dmamap_t m_dmamap; 106 }; 107 108 struct cemac_softc { 109 device_t sc_dev; 110 bus_space_tag_t sc_iot; 111 bus_space_handle_t sc_ioh; 112 bus_dma_tag_t sc_dmat; 113 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 114 struct ethercom sc_ethercom; 115 mii_data_t sc_mii; 116 117 void *rbqpage; 118 unsigned rbqlen; 119 bus_addr_t rbqpage_dsaddr; 120 bus_dmamap_t rbqpage_dmamap; 121 void *tbqpage; 122 unsigned tbqlen; 123 bus_addr_t tbqpage_dsaddr; 124 bus_dmamap_t tbqpage_dmamap; 125 126 volatile struct eth_dsc *RDSC; 127 int rxqi; 128 struct cemac_qmeta rxq[RX_QLEN]; 129 volatile struct eth_dsc *TDSC; 130 int txqi, txqc; 131 struct cemac_qmeta txq[TX_QLEN]; 132 callout_t cemac_tick_ch; 133 134 int cemac_flags; 135 }; 136 137 static void cemac_init(struct cemac_softc *); 138 static int cemac_gctx(struct cemac_softc *); 139 static int cemac_mediachange(struct ifnet *); 140 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 141 static int cemac_mii_readreg(device_t, int, int); 142 static void cemac_mii_writereg(device_t, int, int, int); 143 static void cemac_statchg(struct ifnet *); 144 static void cemac_tick(void *); 145 static int cemac_ifioctl(struct ifnet *, u_long, void *); 146 static void cemac_ifstart(struct ifnet *); 147 static void cemac_ifwatchdog(struct ifnet *); 148 static int cemac_ifinit(struct ifnet *); 149 static void cemac_ifstop(struct ifnet *, int); 150 static void cemac_setaddr(struct ifnet *); 151 152 #ifdef CEMAC_DEBUG 153 int cemac_debug = CEMAC_DEBUG; 154 #define DPRINTFN(n,fmt) if (cemac_debug >= (n)) printf fmt 155 #else 156 #define DPRINTFN(n,fmt) 157 #endif 158 159 CFATTACH_DECL_NEW(cemac, sizeof(struct cemac_softc), 160 cemac_match, cemac_attach, NULL, NULL); 161 162 int 163 cemac_match_common(device_t parent, cfdata_t match, void *aux) 164 { 165 if (strcmp(match->cf_name, "cemac") == 0) 166 return 1; 167 return 0; 168 } 169 170 void 171 cemac_attach_common(device_t self, bus_space_tag_t iot, 172 bus_space_handle_t ioh, bus_dma_tag_t dmat, int flags) 173 { 174 struct cemac_softc *sc = device_private(self); 175 prop_data_t enaddr; 176 uint32_t u; 177 178 179 sc->sc_dev = self; 180 sc->sc_ioh = ioh; 181 sc->sc_iot = iot; 182 sc->sc_dmat = dmat; 183 sc->cemac_flags = flags; 184 185 aprint_naive("\n"); 186 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 187 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 188 else 189 aprint_normal(": Cadence Ethernet Controller\n"); 190 191 /* configure emac: */ 192 CEMAC_WRITE(ETH_CTL, 0); // disable everything 193 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 194 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 195 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 196 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 197 CEMAC_WRITE(ETH_CFG, 198 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 199 else 200 CEMAC_WRITE(ETH_CFG, 201 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 202 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 203 //(void)CEMAC_READ(ETH_ISR); 204 u = CEMAC_READ(ETH_TSR); 205 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 206 | ETH_TSR_IDLE | ETH_TSR_RLE 207 | ETH_TSR_COL|ETH_TSR_OVR))); 208 u = CEMAC_READ(ETH_RSR); 209 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 210 211 /* Fetch the Ethernet address from property if set. */ 212 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 213 214 if (enaddr != NULL) { 215 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 216 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 217 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 218 ETHER_ADDR_LEN); 219 } else { 220 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 221 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 222 }; 223 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 224 } 225 226 cemac_init(sc); 227 } 228 229 static int 230 cemac_gctx(struct cemac_softc *sc) 231 { 232 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 233 uint32_t tsr; 234 235 tsr = CEMAC_READ(ETH_TSR); 236 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 237 // no space left 238 if (!(tsr & ETH_TSR_BNQ)) 239 return 0; 240 } else { 241 if (tsr & GEM_TSR_TXGO) 242 return 0; 243 } 244 CEMAC_WRITE(ETH_TSR, tsr); 245 246 // free sent frames 247 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 248 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 249 int bi = sc->txqi % TX_QLEN; 250 251 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 252 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 253 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 254 __FUNCTION__, bi, sc->TDSC[bi].Info)); 255 256 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 257 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 258 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 259 m_freem(sc->txq[bi].m); 260 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 261 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 262 sc->txq[bi].m = NULL; 263 sc->txqi = (bi + 1) % TX_QLEN; 264 sc->txqc--; 265 } 266 267 // mark we're free 268 if (ifp->if_flags & IFF_OACTIVE) { 269 ifp->if_flags &= ~IFF_OACTIVE; 270 /* Disable transmit-buffer-free interrupt */ 271 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 272 } 273 274 return 1; 275 } 276 277 int 278 cemac_intr(void *arg) 279 { 280 struct cemac_softc *sc = (struct cemac_softc *)arg; 281 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 282 uint32_t imr, isr, ctl; 283 #ifdef CEMAC_DEBUG 284 uint32_t rsr; 285 #endif 286 int bi; 287 288 imr = ~CEMAC_READ(ETH_IMR); 289 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR|ETH_ISR_TCOM))) { 290 // interrupt not enabled, can't be us 291 return 0; 292 } 293 294 isr = CEMAC_READ(ETH_ISR); 295 CEMAC_WRITE(ETH_ISR, isr); 296 isr &= imr; 297 #ifdef CEMAC_DEBUG 298 rsr = CEMAC_READ(ETH_RSR); // get receive status register 299 #endif 300 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 301 302 if (isr & ETH_ISR_RBNA) { // out of receive buffers 303 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 304 ctl = CEMAC_READ(ETH_CTL); // get current control register value 305 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 306 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 307 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 308 ifp->if_ierrors++; 309 ifp->if_ipackets++; 310 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 311 } 312 if (isr & ETH_ISR_ROVR) { 313 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 314 ifp->if_ierrors++; 315 ifp->if_ipackets++; 316 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 317 } 318 319 if (isr & ETH_ISR_RCOM) { // packet has been received! 320 uint32_t nfo; 321 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 322 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 323 int fl, csum; 324 struct mbuf *m; 325 326 nfo = sc->RDSC[bi].Info; 327 fl = (nfo & ETH_RDSC_I_LEN) - 4; 328 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 329 330 MGETHDR(m, M_DONTWAIT, MT_DATA); 331 if (m != NULL) MCLGET(m, M_DONTWAIT); 332 if (m != NULL && (m->m_flags & M_EXT)) { 333 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 334 MCLBYTES, BUS_DMASYNC_POSTREAD); 335 bus_dmamap_unload(sc->sc_dmat, 336 sc->rxq[bi].m_dmamap); 337 m_set_rcvif(sc->rxq[bi].m, ifp); 338 sc->rxq[bi].m->m_pkthdr.len = 339 sc->rxq[bi].m->m_len = fl; 340 switch (nfo & ETH_RDSC_I_CHKSUM) { 341 case ETH_RDSC_I_CHKSUM_IP: 342 csum = M_CSUM_IPv4; 343 break; 344 case ETH_RDSC_I_CHKSUM_UDP: 345 csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 346 M_CSUM_UDPv6; 347 break; 348 case ETH_RDSC_I_CHKSUM_TCP: 349 csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 350 M_CSUM_TCPv6; 351 break; 352 default: 353 csum = 0; 354 break; 355 } 356 sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 357 DPRINTFN(2,("received %u bytes packet\n", fl)); 358 if_percpuq_enqueue(ifp->if_percpuq, 359 sc->rxq[bi].m); 360 if (mtod(m, intptr_t) & 3) 361 m_adj(m, mtod(m, intptr_t) & 3); 362 sc->rxq[bi].m = m; 363 bus_dmamap_load(sc->sc_dmat, 364 sc->rxq[bi].m_dmamap, 365 m->m_ext.ext_buf, MCLBYTES, 366 NULL, BUS_DMA_NOWAIT); 367 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 368 MCLBYTES, BUS_DMASYNC_PREREAD); 369 sc->RDSC[bi].Info = 0; 370 sc->RDSC[bi].Addr = 371 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 372 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 373 } else { 374 /* Drop packets until we can get replacement 375 * empty mbufs for the RXDQ. 376 */ 377 if (m != NULL) 378 m_freem(m); 379 ifp->if_ierrors++; 380 } 381 sc->rxqi++; 382 } 383 } 384 385 if (cemac_gctx(sc) > 0) 386 if_schedule_deferred_start(ifp); 387 #if 0 // reloop 388 irq = CEMAC_READ(IntStsC); 389 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 390 goto begin; 391 #endif 392 393 return (1); 394 } 395 396 397 static void 398 cemac_init(struct cemac_softc *sc) 399 { 400 bus_dma_segment_t segs; 401 int rsegs, err, i; 402 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 403 uint32_t u; 404 #if 0 405 int mdcdiv = DEFAULT_MDCDIV; 406 #endif 407 408 callout_init(&sc->cemac_tick_ch, 0); 409 410 // ok... 411 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 412 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 413 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 414 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 415 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 416 CEMAC_WRITE(ETH_CFG, 417 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 418 else 419 CEMAC_WRITE(ETH_CFG, 420 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 421 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 422 CEMAC_WRITE(GEM_DMA_CFG, 423 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 424 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 425 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 426 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 427 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 428 } 429 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 430 // (void)CEMAC_READ(ETH_ISR); 431 u = CEMAC_READ(ETH_TSR); 432 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 433 | ETH_TSR_IDLE | ETH_TSR_RLE 434 | ETH_TSR_COL|ETH_TSR_OVR))); 435 u = CEMAC_READ(ETH_RSR); 436 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 437 438 #if 0 439 if (device_cfdata(sc->sc_dev)->cf_flags) 440 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 441 #endif 442 /* set ethernet address */ 443 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 444 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 445 | (sc->sc_enaddr[0])); 446 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 447 | (sc->sc_enaddr[4])); 448 CEMAC_GEM_WRITE(SA2L, 0); 449 CEMAC_GEM_WRITE(SA2H, 0); 450 CEMAC_GEM_WRITE(SA3L, 0); 451 CEMAC_GEM_WRITE(SA3H, 0); 452 CEMAC_GEM_WRITE(SA4L, 0); 453 CEMAC_GEM_WRITE(SA4H, 0); 454 455 /* Allocate a page of memory for receive queue descriptors */ 456 sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 457 sc->rbqlen *= PAGE_SIZE; 458 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 459 460 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 461 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 462 &segs, 1, &rsegs, BUS_DMA_WAITOK); 463 if (err == 0) { 464 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 465 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 466 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 467 } 468 if (err == 0) { 469 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 470 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 471 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 472 &sc->rbqpage_dmamap); 473 } 474 if (err == 0) { 475 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 476 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 477 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 478 } 479 if (err != 0) 480 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 481 482 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 483 memset(sc->rbqpage, 0, sc->rbqlen); 484 485 /* Allocate a page of memory for transmit queue descriptors */ 486 sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 487 sc->tbqlen *= PAGE_SIZE; 488 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 489 490 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 491 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 492 &segs, 1, &rsegs, BUS_DMA_WAITOK); 493 if (err == 0) { 494 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 495 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 496 &sc->tbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 497 } 498 if (err == 0) { 499 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 500 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 501 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 502 &sc->tbqpage_dmamap); 503 } 504 if (err == 0) { 505 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 506 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 507 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 508 } 509 if (err != 0) 510 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 511 512 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 513 memset(sc->tbqpage, 0, sc->tbqlen); 514 515 /* Set up pointers to start of each queue in kernel addr space. 516 * Each descriptor queue or status queue entry uses 2 words 517 */ 518 sc->RDSC = (void *)sc->rbqpage; 519 sc->TDSC = (void *)sc->tbqpage; 520 521 /* init TX queue */ 522 for (i = 0; i < TX_QLEN; i++) { 523 sc->TDSC[i].Addr = 0; 524 sc->TDSC[i].Info = ETH_TDSC_I_USED | 525 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 526 } 527 528 /* Populate the RXQ with mbufs */ 529 sc->rxqi = 0; 530 for(i = 0; i < RX_QLEN; i++) { 531 struct mbuf *m; 532 533 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 534 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 535 if (err) { 536 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 537 } 538 MGETHDR(m, M_WAIT, MT_DATA); 539 MCLGET(m, M_WAIT); 540 sc->rxq[i].m = m; 541 if (mtod(m, intptr_t) & 3) { 542 m_adj(m, mtod(m, intptr_t) & 3); 543 } 544 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 545 m->m_ext.ext_buf, MCLBYTES, NULL, 546 BUS_DMA_WAITOK); 547 if (err) { 548 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 549 } 550 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 551 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 552 sc->RDSC[i].Info = 0; 553 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 554 MCLBYTES, BUS_DMASYNC_PREREAD); 555 } 556 557 /* prepare transmit queue */ 558 for (i = 0; i < TX_QLEN; i++) { 559 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 560 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 561 &sc->txq[i].m_dmamap); 562 if (err) 563 panic("ARGH #1"); 564 sc->txq[i].m = NULL; 565 } 566 567 /* Program each queue's start addr, cur addr, and len registers 568 * with the physical addresses. 569 */ 570 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 571 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 572 573 /* Divide HCLK by 32 for MDC clock */ 574 sc->sc_ethercom.ec_mii = &sc->sc_mii; 575 sc->sc_mii.mii_ifp = ifp; 576 sc->sc_mii.mii_readreg = cemac_mii_readreg; 577 sc->sc_mii.mii_writereg = cemac_mii_writereg; 578 sc->sc_mii.mii_statchg = cemac_statchg; 579 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, cemac_mediachange, 580 cemac_mediastatus); 581 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 582 MII_OFFSET_ANY, 0); 583 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 584 585 #if 0 586 // enable / disable interrupts 587 CEMAC_WRITE(ETH_IDR, -1); 588 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 589 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 590 // (void)CEMAC_READ(ETH_ISR); // why 591 592 // enable transmitter / receiver 593 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 594 | ETH_CTL_CSR | ETH_CTL_MPE); 595 #endif 596 /* 597 * We can support hardware checksumming. 598 */ 599 ifp->if_capabilities |= 600 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 601 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 602 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 603 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 604 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 605 606 /* 607 * We can support 802.1Q VLAN-sized frames. 608 */ 609 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 610 611 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 612 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 613 ifp->if_ioctl = cemac_ifioctl; 614 ifp->if_start = cemac_ifstart; 615 ifp->if_watchdog = cemac_ifwatchdog; 616 ifp->if_init = cemac_ifinit; 617 ifp->if_stop = cemac_ifstop; 618 ifp->if_timer = 0; 619 ifp->if_softc = sc; 620 IFQ_SET_READY(&ifp->if_snd); 621 if_attach(ifp); 622 if_deferred_start_init(ifp, NULL); 623 ether_ifattach(ifp, (sc)->sc_enaddr); 624 } 625 626 static int 627 cemac_mediachange(struct ifnet *ifp) 628 { 629 if (ifp->if_flags & IFF_UP) 630 cemac_ifinit(ifp); 631 return (0); 632 } 633 634 static void 635 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 636 { 637 struct cemac_softc *sc = ifp->if_softc; 638 639 mii_pollstat(&sc->sc_mii); 640 ifmr->ifm_active = sc->sc_mii.mii_media_active; 641 ifmr->ifm_status = sc->sc_mii.mii_media_status; 642 } 643 644 645 static int 646 cemac_mii_readreg(device_t self, int phy, int reg) 647 { 648 struct cemac_softc *sc; 649 650 sc = device_private(self); 651 652 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 653 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 654 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 655 | ETH_MAN_CODE_IEEE802_3)); 656 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)); 657 658 return (CEMAC_READ(ETH_MAN) & ETH_MAN_DATA); 659 } 660 661 static void 662 cemac_mii_writereg(device_t self, int phy, int reg, int val) 663 { 664 struct cemac_softc *sc; 665 666 sc = device_private(self); 667 668 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 669 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 670 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 671 | ETH_MAN_CODE_IEEE802_3 672 | (val & ETH_MAN_DATA))); 673 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 674 } 675 676 677 static void 678 cemac_statchg(struct ifnet *ifp) 679 { 680 struct cemac_softc *sc = ifp->if_softc; 681 struct mii_data *mii = &sc->sc_mii; 682 uint32_t reg; 683 684 /* 685 * We must keep the MAC and the PHY in sync as 686 * to the status of full-duplex! 687 */ 688 reg = CEMAC_READ(ETH_CFG); 689 reg &= ~ETH_CFG_FD; 690 if (sc->sc_mii.mii_media_active & IFM_FDX) 691 reg |= ETH_CFG_FD; 692 693 reg &= ~ETH_CFG_SPD; 694 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 695 reg &= ~GEM_CFG_GEN; 696 switch (IFM_SUBTYPE(mii->mii_media_active)) { 697 case IFM_10_T: 698 break; 699 case IFM_100_TX: 700 reg |= ETH_CFG_SPD; 701 break; 702 case IFM_1000_T: 703 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 704 break; 705 default: 706 break; 707 } 708 CEMAC_WRITE(ETH_CFG, reg); 709 } 710 711 static void 712 cemac_tick(void *arg) 713 { 714 struct cemac_softc* sc = (struct cemac_softc *)arg; 715 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 716 int s; 717 718 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 719 ifp->if_collisions += CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL); 720 else 721 ifp->if_collisions += CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL); 722 723 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 724 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 725 uint32_t misses = CEMAC_READ(ETH_DRFC); 726 if (misses > 0) 727 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 728 } 729 730 s = splnet(); 731 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 732 cemac_ifstart(ifp); 733 splx(s); 734 735 mii_tick(&sc->sc_mii); 736 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 737 } 738 739 740 static int 741 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 742 { 743 struct cemac_softc *sc = ifp->if_softc; 744 struct ifreq *ifr = (struct ifreq *)data; 745 int s, error; 746 747 s = splnet(); 748 switch(cmd) { 749 case SIOCSIFMEDIA: 750 case SIOCGIFMEDIA: 751 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 752 break; 753 default: 754 error = ether_ioctl(ifp, cmd, data); 755 if (error != ENETRESET) 756 break; 757 error = 0; 758 759 if (cmd == SIOCSIFCAP) { 760 error = (*ifp->if_init)(ifp); 761 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 762 ; 763 else if (ifp->if_flags & IFF_RUNNING) { 764 cemac_setaddr(ifp); 765 } 766 } 767 splx(s); 768 return error; 769 } 770 771 static void 772 cemac_ifstart(struct ifnet *ifp) 773 { 774 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 775 struct mbuf *m; 776 bus_dma_segment_t *segs; 777 int s, bi, err, nsegs; 778 779 s = splnet(); 780 start: 781 if (cemac_gctx(sc) == 0) { 782 /* Enable transmit-buffer-free interrupt */ 783 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 784 ifp->if_flags |= IFF_OACTIVE; 785 ifp->if_timer = 10; 786 splx(s); 787 return; 788 } 789 790 ifp->if_timer = 0; 791 792 IFQ_POLL(&ifp->if_snd, m); 793 if (m == NULL) { 794 splx(s); 795 return; 796 } 797 798 bi = (sc->txqi + sc->txqc) % TX_QLEN; 799 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 800 BUS_DMA_NOWAIT)) || 801 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 802 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 803 /* Copy entire mbuf chain to new single */ 804 struct mbuf *mn; 805 806 if (err == 0) 807 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 808 809 MGETHDR(mn, M_DONTWAIT, MT_DATA); 810 if (mn == NULL) goto stop; 811 if (m->m_pkthdr.len > MHLEN) { 812 MCLGET(mn, M_DONTWAIT); 813 if ((mn->m_flags & M_EXT) == 0) { 814 m_freem(mn); 815 goto stop; 816 } 817 } 818 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 819 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 820 IFQ_DEQUEUE(&ifp->if_snd, m); 821 m_freem(m); 822 m = mn; 823 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 824 BUS_DMA_NOWAIT); 825 } else { 826 IFQ_DEQUEUE(&ifp->if_snd, m); 827 } 828 829 bpf_mtap(ifp, m, BPF_D_OUT); 830 831 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 832 segs = sc->txq[bi].m_dmamap->dm_segs; 833 if (nsegs > 1) 834 panic("#### ARGH #2"); 835 836 sc->txq[bi].m = m; 837 sc->txqc++; 838 839 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 840 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 841 (unsigned)m->m_pkthdr.len)); 842 #ifdef DIAGNOSTIC 843 if (sc->txqc > TX_QLEN) 844 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 845 #endif 846 847 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 848 sc->txq[bi].m_dmamap->dm_mapsize, 849 BUS_DMASYNC_PREWRITE); 850 851 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 852 sc->TDSC[bi].Addr = segs->ds_addr; 853 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 854 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 855 856 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 857 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 858 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 859 __FUNCTION__, bi, sc->TDSC[bi].Info)); 860 861 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 862 CEMAC_WRITE(ETH_CTL, ctl); 863 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 864 } else { 865 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 866 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 867 } 868 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 869 goto start; 870 stop: 871 872 splx(s); 873 return; 874 } 875 876 static void 877 cemac_ifwatchdog(struct ifnet *ifp) 878 { 879 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 880 881 if ((ifp->if_flags & IFF_RUNNING) == 0) 882 return; 883 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 884 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 885 } 886 887 static int 888 cemac_ifinit(struct ifnet *ifp) 889 { 890 struct cemac_softc *sc = ifp->if_softc; 891 uint32_t dma, cfg; 892 int s = splnet(); 893 894 callout_stop(&sc->cemac_tick_ch); 895 896 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 897 898 if (ifp->if_capenable & 899 (IFCAP_CSUM_IPv4_Tx | 900 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 901 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 902 dma = CEMAC_READ(GEM_DMA_CFG); 903 dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 904 CEMAC_WRITE(GEM_DMA_CFG, dma); 905 } 906 if (ifp->if_capenable & 907 (IFCAP_CSUM_IPv4_Rx | 908 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 909 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 910 cfg = CEMAC_READ(ETH_CFG); 911 cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN; 912 CEMAC_WRITE(ETH_CFG, cfg); 913 } 914 } 915 916 // enable interrupts 917 CEMAC_WRITE(ETH_IDR, -1); 918 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 919 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 920 921 // enable transmitter / receiver 922 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 923 | ETH_CTL_CSR | ETH_CTL_MPE); 924 925 mii_mediachg(&sc->sc_mii); 926 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 927 ifp->if_flags |= IFF_RUNNING; 928 splx(s); 929 return 0; 930 } 931 932 static void 933 cemac_ifstop(struct ifnet *ifp, int disable) 934 { 935 // uint32_t u; 936 struct cemac_softc *sc = ifp->if_softc; 937 938 #if 0 939 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 940 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 941 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 942 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 943 CEMAC_WRITE(ETH_CFG, 944 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 945 else 946 CEMAC_WRITE(ETH_CFG, 947 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 948 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 949 // (void)CEMAC_READ(ETH_ISR); 950 u = CEMAC_READ(ETH_TSR); 951 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 952 | ETH_TSR_IDLE | ETH_TSR_RLE 953 | ETH_TSR_COL|ETH_TSR_OVR))); 954 u = CEMAC_READ(ETH_RSR); 955 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 956 #endif 957 callout_stop(&sc->cemac_tick_ch); 958 959 /* Down the MII. */ 960 mii_down(&sc->sc_mii); 961 962 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 963 ifp->if_timer = 0; 964 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 965 } 966 967 static void 968 cemac_setaddr(struct ifnet *ifp) 969 { 970 struct cemac_softc *sc = ifp->if_softc; 971 struct ethercom *ac = &sc->sc_ethercom; 972 struct ether_multi *enm; 973 struct ether_multistep step; 974 uint8_t ias[3][ETHER_ADDR_LEN]; 975 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 976 uint32_t ctl = CEMAC_READ(ETH_CTL); 977 uint32_t cfg = CEMAC_READ(ETH_CFG); 978 979 /* disable receiver temporarily */ 980 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 981 982 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 983 984 if (ifp->if_flags & IFF_PROMISC) { 985 cfg |= ETH_CFG_CAF; 986 } else { 987 cfg &= ~ETH_CFG_CAF; 988 } 989 990 // ETH_CFG_BIG? 991 992 ifp->if_flags &= ~IFF_ALLMULTI; 993 994 ETHER_FIRST_MULTI(step, ac, enm); 995 while (enm != NULL) { 996 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 997 /* 998 * We must listen to a range of multicast addresses. 999 * For now, just accept all multicasts, rather than 1000 * trying to set only those filter bits needed to match 1001 * the range. (At this time, the only use of address 1002 * ranges is for IP multicast routing, for which the 1003 * range is big enough to require all bits set.) 1004 */ 1005 cfg |= ETH_CFG_MTI; 1006 hashes[0] = 0xffffffffUL; 1007 hashes[1] = 0xffffffffUL; 1008 ifp->if_flags |= IFF_ALLMULTI; 1009 nma = 0; 1010 break; 1011 } 1012 1013 if (nma < 3) { 1014 /* We can program 3 perfect address filters for mcast */ 1015 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 1016 } else { 1017 /* 1018 * XXX: Datasheet is not very clear here, I'm not sure 1019 * if I'm doing this right. --joff 1020 */ 1021 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1022 1023 /* Just want the 6 most-significant bits. */ 1024 h = h >> 26; 1025 #if 0 1026 hashes[h / 32] |= (1 << (h % 32)); 1027 #else 1028 hashes[0] = 0xffffffffUL; 1029 hashes[1] = 0xffffffffUL; 1030 #endif 1031 cfg |= ETH_CFG_MTI; 1032 } 1033 ETHER_NEXT_MULTI(step, enm); 1034 nma++; 1035 } 1036 1037 // program... 1038 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1039 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 1040 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 1041 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 1042 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 1043 | (sc->sc_enaddr[0])); 1044 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 1045 | (sc->sc_enaddr[4])); 1046 if (nma > 0) { 1047 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1048 ias[0][0], ias[0][1], ias[0][2], 1049 ias[0][3], ias[0][4], ias[0][5])); 1050 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 1051 | (ias[0][2] << 16) | (ias[0][1] << 8) 1052 | (ias[0][0])); 1053 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 1054 | (ias[0][5])); 1055 } 1056 if (nma > 1) { 1057 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1058 ias[1][0], ias[1][1], ias[1][2], 1059 ias[1][3], ias[1][4], ias[1][5])); 1060 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1061 | (ias[1][2] << 16) | (ias[1][1] << 8) 1062 | (ias[1][0])); 1063 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1064 | (ias[1][5])); 1065 } 1066 if (nma > 2) { 1067 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1068 ias[2][0], ias[2][1], ias[2][2], 1069 ias[2][3], ias[2][4], ias[2][5])); 1070 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1071 | (ias[2][2] << 16) | (ias[2][1] << 8) 1072 | (ias[2][0])); 1073 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1074 | (ias[2][5])); 1075 } 1076 CEMAC_GEM_WRITE(HSH, hashes[0]); 1077 CEMAC_GEM_WRITE(HSL, hashes[1]); 1078 CEMAC_WRITE(ETH_CFG, cfg); 1079 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1080 } 1081
Indexes created Tue Sep 23 02:09:52 GMT 2025