if_cemac.c revision 1.31
1 /* $NetBSD: if_cemac.c,v 1.31 2024/08/24 10:11:40 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.31 2024/08/24 10:11:40 skrll Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/kernel.h> 50 #include <sys/proc.h> 51 #include <sys/malloc.h> 52 #include <sys/time.h> 53 #include <sys/device.h> 54 #include <uvm/uvm_extern.h> 55 56 #include <sys/bus.h> 57 #include <machine/intr.h> 58 59 #include <arm/cpufunc.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_types.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 #include <net/bpf.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #include <netinet/if_inarp.h> 77 #endif 78 79 #include <dev/cadence/cemacreg.h> 80 #include <dev/cadence/if_cemacvar.h> 81 82 #define DEFAULT_MDCDIV 32 83 84 #define CEMAC_READ(x) \ 85 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 86 #define CEMAC_WRITE(x, y) \ 87 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 88 #define CEMAC_GEM_WRITE(x, y) \ 89 do { \ 90 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 91 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 92 else \ 93 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 94 } while(0) 95 96 #define RX_QLEN 64 97 #define TX_QLEN 2 /* I'm very sorry but that's where we can get */ 98 99 struct cemac_qmeta { 100 struct mbuf *m; 101 bus_dmamap_t m_dmamap; 102 }; 103 104 struct cemac_softc { 105 device_t sc_dev; 106 bus_space_tag_t sc_iot; 107 bus_space_handle_t sc_ioh; 108 bus_dma_tag_t sc_dmat; 109 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 110 struct ethercom sc_ethercom; 111 mii_data_t sc_mii; 112 113 void *rbqpage; 114 unsigned rbqlen; 115 bus_addr_t rbqpage_dsaddr; 116 bus_dmamap_t rbqpage_dmamap; 117 void *tbqpage; 118 unsigned tbqlen; 119 bus_addr_t tbqpage_dsaddr; 120 bus_dmamap_t tbqpage_dmamap; 121 122 volatile struct eth_dsc *RDSC; 123 int rxqi; 124 struct cemac_qmeta rxq[RX_QLEN]; 125 volatile struct eth_dsc *TDSC; 126 int txqi, txqc; 127 struct cemac_qmeta txq[TX_QLEN]; 128 callout_t cemac_tick_ch; 129 bool tx_busy; 130 131 int cemac_flags; 132 }; 133 134 static void cemac_init(struct cemac_softc *); 135 static int cemac_gctx(struct cemac_softc *); 136 static int cemac_mediachange(struct ifnet *); 137 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 138 static int cemac_mii_readreg(device_t, int, int, uint16_t *); 139 static int cemac_mii_writereg(device_t, int, int, uint16_t); 140 static void cemac_statchg(struct ifnet *); 141 static void cemac_tick(void *); 142 static int cemac_ifioctl(struct ifnet *, u_long, void *); 143 static void cemac_ifstart(struct ifnet *); 144 static void cemac_ifwatchdog(struct ifnet *); 145 static int cemac_ifinit(struct ifnet *); 146 static void cemac_ifstop(struct ifnet *, int); 147 static void cemac_setaddr(struct ifnet *); 148 149 #ifdef CEMAC_DEBUG 150 int cemac_debug = CEMAC_DEBUG; 151 #define DPRINTFN(n, fmt) if (cemac_debug >= (n)) printf fmt 152 #else 153 #define DPRINTFN(n, fmt) 154 #endif 155 156 CFATTACH_DECL_NEW(cemac, sizeof(struct cemac_softc), 157 cemac_match, cemac_attach, NULL, NULL); 158 159 160 void 161 cemac_attach_common(device_t self, bus_space_tag_t iot, 162 bus_space_handle_t ioh, bus_dma_tag_t dmat, int flags) 163 { 164 struct cemac_softc *sc = device_private(self); 165 prop_data_t enaddr; 166 uint32_t u; 167 168 169 sc->sc_dev = self; 170 sc->sc_ioh = ioh; 171 sc->sc_iot = iot; 172 sc->sc_dmat = dmat; 173 sc->cemac_flags = flags; 174 175 aprint_naive("\n"); 176 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 177 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 178 else 179 aprint_normal(": Cadence Ethernet Controller\n"); 180 181 /* configure emac: */ 182 CEMAC_WRITE(ETH_CTL, 0); // disable everything 183 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 184 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 185 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 186 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 187 CEMAC_WRITE(ETH_CFG, 188 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 189 else 190 CEMAC_WRITE(ETH_CFG, 191 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 192 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 193 //(void)CEMAC_READ(ETH_ISR); 194 u = CEMAC_READ(ETH_TSR); 195 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 196 | ETH_TSR_IDLE | ETH_TSR_RLE 197 | ETH_TSR_COL | ETH_TSR_OVR))); 198 u = CEMAC_READ(ETH_RSR); 199 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 200 201 /* Fetch the Ethernet address from property if set. */ 202 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 203 204 if (enaddr != NULL) { 205 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 206 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 207 memcpy(sc->sc_enaddr, prop_data_value(enaddr), 208 ETHER_ADDR_LEN); 209 } else { 210 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 211 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 212 }; 213 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 214 } 215 216 cemac_init(sc); 217 } 218 219 static int 220 cemac_gctx(struct cemac_softc *sc) 221 { 222 uint32_t tsr; 223 224 tsr = CEMAC_READ(ETH_TSR); 225 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 226 // no space left 227 if (!(tsr & ETH_TSR_BNQ)) 228 return 0; 229 } else { 230 if (tsr & GEM_TSR_TXGO) 231 return 0; 232 } 233 CEMAC_WRITE(ETH_TSR, tsr); 234 235 // free sent frames 236 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 237 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 238 int bi = sc->txqi % TX_QLEN; 239 240 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 241 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 242 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 243 __FUNCTION__, bi, sc->TDSC[bi].Info)); 244 245 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 246 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 247 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 248 m_freem(sc->txq[bi].m); 249 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 250 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 251 sc->txq[bi].m = NULL; 252 sc->txqi = (bi + 1) % TX_QLEN; 253 sc->txqc--; 254 } 255 256 // mark we're free 257 if (sc->tx_busy) { 258 sc->tx_busy = false; 259 /* Disable transmit-buffer-free interrupt */ 260 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 261 } 262 263 return 1; 264 } 265 266 int 267 cemac_intr(void *arg) 268 { 269 struct cemac_softc *sc = (struct cemac_softc *)arg; 270 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 271 uint32_t imr, isr, ctl; 272 #ifdef CEMAC_DEBUG 273 uint32_t rsr; 274 #endif 275 int bi; 276 277 imr = ~CEMAC_READ(ETH_IMR); 278 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE | 279 ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM))) { 280 // interrupt not enabled, can't be us 281 return 0; 282 } 283 284 isr = CEMAC_READ(ETH_ISR); 285 CEMAC_WRITE(ETH_ISR, isr); 286 isr &= imr; 287 #ifdef CEMAC_DEBUG 288 rsr = CEMAC_READ(ETH_RSR); // get receive status register 289 #endif 290 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 291 292 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 293 if (isr & ETH_ISR_RBNA) { // out of receive buffers 294 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 295 ctl = CEMAC_READ(ETH_CTL); // get current control register value 296 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 297 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 298 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 299 if_statinc_ref(ifp, nsr, if_ierrors); 300 if_statinc_ref(ifp, nsr, if_ipackets); 301 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 302 } 303 if (isr & ETH_ISR_ROVR) { 304 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 305 if_statinc_ref(ifp, nsr, if_ierrors); 306 if_statinc_ref(ifp, nsr, if_ipackets); 307 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 308 } 309 310 if (isr & ETH_ISR_RCOM) { // packet has been received! 311 uint32_t nfo; 312 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 313 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 314 int fl, csum; 315 struct mbuf *m; 316 317 nfo = sc->RDSC[bi].Info; 318 fl = (nfo & ETH_RDSC_I_LEN) - 4; 319 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 320 321 MGETHDR(m, M_DONTWAIT, MT_DATA); 322 if (m != NULL) MCLGET(m, M_DONTWAIT); 323 if (m != NULL && (m->m_flags & M_EXT)) { 324 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 325 MCLBYTES, BUS_DMASYNC_POSTREAD); 326 bus_dmamap_unload(sc->sc_dmat, 327 sc->rxq[bi].m_dmamap); 328 m_set_rcvif(sc->rxq[bi].m, ifp); 329 sc->rxq[bi].m->m_pkthdr.len = 330 sc->rxq[bi].m->m_len = fl; 331 switch (nfo & ETH_RDSC_I_CHKSUM) { 332 case ETH_RDSC_I_CHKSUM_IP: 333 csum = M_CSUM_IPv4; 334 break; 335 case ETH_RDSC_I_CHKSUM_UDP: 336 csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 337 M_CSUM_UDPv6; 338 break; 339 case ETH_RDSC_I_CHKSUM_TCP: 340 csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 341 M_CSUM_TCPv6; 342 break; 343 default: 344 csum = 0; 345 break; 346 } 347 sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 348 DPRINTFN(2,("received %u bytes packet\n", fl)); 349 if_percpuq_enqueue(ifp->if_percpuq, 350 sc->rxq[bi].m); 351 if (mtod(m, intptr_t) & 3) 352 m_adj(m, mtod(m, intptr_t) & 3); 353 sc->rxq[bi].m = m; 354 bus_dmamap_load(sc->sc_dmat, 355 sc->rxq[bi].m_dmamap, 356 m->m_ext.ext_buf, MCLBYTES, 357 NULL, BUS_DMA_NOWAIT); 358 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 359 MCLBYTES, BUS_DMASYNC_PREREAD); 360 sc->RDSC[bi].Info = 0; 361 sc->RDSC[bi].Addr = 362 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 363 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 364 } else { 365 /* Drop packets until we can get replacement 366 * empty mbufs for the RXDQ. 367 */ 368 m_freem(m); 369 if_statinc_ref(ifp, nsr, if_ierrors); 370 } 371 sc->rxqi++; 372 } 373 } 374 375 IF_STAT_PUTREF(ifp); 376 377 if (cemac_gctx(sc) > 0) 378 if_schedule_deferred_start(ifp); 379 #if 0 // reloop 380 irq = CEMAC_READ(IntStsC); 381 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 382 goto begin; 383 #endif 384 385 return 1; 386 } 387 388 389 static void 390 cemac_init(struct cemac_softc *sc) 391 { 392 bus_dma_segment_t segs; 393 int rsegs, err, i; 394 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 395 struct mii_data * const mii = &sc->sc_mii; 396 uint32_t u; 397 #if 0 398 int mdcdiv = DEFAULT_MDCDIV; 399 #endif 400 401 callout_init(&sc->cemac_tick_ch, 0); 402 403 // ok... 404 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 405 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 406 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 407 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 408 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 409 CEMAC_WRITE(ETH_CFG, 410 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 411 else 412 CEMAC_WRITE(ETH_CFG, 413 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 414 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 415 CEMAC_WRITE(GEM_DMA_CFG, 416 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 417 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 418 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 419 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 420 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 421 } 422 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 423 // (void)CEMAC_READ(ETH_ISR); 424 u = CEMAC_READ(ETH_TSR); 425 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 426 | ETH_TSR_IDLE | ETH_TSR_RLE 427 | ETH_TSR_COL | ETH_TSR_OVR))); 428 u = CEMAC_READ(ETH_RSR); 429 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 430 431 #if 0 432 if (device_cfdata(sc->sc_dev)->cf_flags) 433 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 434 #endif 435 /* set ethernet address */ 436 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 437 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 438 | (sc->sc_enaddr[0])); 439 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 440 | (sc->sc_enaddr[4])); 441 CEMAC_GEM_WRITE(SA2L, 0); 442 CEMAC_GEM_WRITE(SA2H, 0); 443 CEMAC_GEM_WRITE(SA3L, 0); 444 CEMAC_GEM_WRITE(SA3H, 0); 445 CEMAC_GEM_WRITE(SA4L, 0); 446 CEMAC_GEM_WRITE(SA4H, 0); 447 448 /* Allocate a page of memory for receive queue descriptors */ 449 sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 450 sc->rbqlen *= PAGE_SIZE; 451 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 452 453 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 454 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 455 &segs, 1, &rsegs, BUS_DMA_WAITOK); 456 if (err == 0) { 457 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 458 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 459 &sc->rbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 460 } 461 if (err == 0) { 462 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 463 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 464 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 465 &sc->rbqpage_dmamap); 466 } 467 if (err == 0) { 468 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 469 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 470 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 471 } 472 if (err != 0) 473 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 474 475 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 476 memset(sc->rbqpage, 0, sc->rbqlen); 477 478 /* Allocate a page of memory for transmit queue descriptors */ 479 sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 480 sc->tbqlen *= PAGE_SIZE; 481 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 482 483 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 484 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 485 &segs, 1, &rsegs, BUS_DMA_WAITOK); 486 if (err == 0) { 487 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 488 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 489 &sc->tbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 490 } 491 if (err == 0) { 492 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 493 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 494 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 495 &sc->tbqpage_dmamap); 496 } 497 if (err == 0) { 498 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 499 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 500 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 501 } 502 if (err != 0) 503 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 504 505 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 506 memset(sc->tbqpage, 0, sc->tbqlen); 507 508 /* Set up pointers to start of each queue in kernel addr space. 509 * Each descriptor queue or status queue entry uses 2 words 510 */ 511 sc->RDSC = (void *)sc->rbqpage; 512 sc->TDSC = (void *)sc->tbqpage; 513 514 /* init TX queue */ 515 for (i = 0; i < TX_QLEN; i++) { 516 sc->TDSC[i].Addr = 0; 517 sc->TDSC[i].Info = ETH_TDSC_I_USED | 518 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 519 } 520 521 /* Populate the RXQ with mbufs */ 522 sc->rxqi = 0; 523 for (i = 0; i < RX_QLEN; i++) { 524 struct mbuf *m; 525 526 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 527 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 528 if (err) { 529 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 530 } 531 MGETHDR(m, M_WAIT, MT_DATA); 532 MCLGET(m, M_WAIT); 533 sc->rxq[i].m = m; 534 if (mtod(m, intptr_t) & 3) { 535 m_adj(m, mtod(m, intptr_t) & 3); 536 } 537 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 538 m->m_ext.ext_buf, MCLBYTES, NULL, 539 BUS_DMA_WAITOK); 540 if (err) { 541 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 542 } 543 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 544 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 545 sc->RDSC[i].Info = 0; 546 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 547 MCLBYTES, BUS_DMASYNC_PREREAD); 548 } 549 550 /* prepare transmit queue */ 551 for (i = 0; i < TX_QLEN; i++) { 552 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 553 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 554 &sc->txq[i].m_dmamap); 555 if (err) 556 panic("ARGH #1"); 557 sc->txq[i].m = NULL; 558 } 559 560 /* Program each queue's start addr, cur addr, and len registers 561 * with the physical addresses. 562 */ 563 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 564 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 565 566 /* Divide HCLK by 32 for MDC clock */ 567 sc->sc_ethercom.ec_mii = mii; 568 mii->mii_ifp = ifp; 569 mii->mii_readreg = cemac_mii_readreg; 570 mii->mii_writereg = cemac_mii_writereg; 571 mii->mii_statchg = cemac_statchg; 572 ifmedia_init(&mii->mii_media, IFM_IMASK, cemac_mediachange, 573 cemac_mediastatus); 574 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1, 0); 575 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 576 577 #if 0 578 // enable / disable interrupts 579 CEMAC_WRITE(ETH_IDR, -1); 580 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 581 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 582 // (void)CEMAC_READ(ETH_ISR); // why 583 584 // enable transmitter / receiver 585 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 586 | ETH_CTL_CSR | ETH_CTL_MPE); 587 #endif 588 /* 589 * We can support hardware checksumming. 590 */ 591 ifp->if_capabilities |= 592 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 593 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 594 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 595 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 596 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 597 598 /* 599 * We can support 802.1Q VLAN-sized frames. 600 */ 601 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 602 603 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 605 ifp->if_ioctl = cemac_ifioctl; 606 ifp->if_start = cemac_ifstart; 607 ifp->if_watchdog = cemac_ifwatchdog; 608 ifp->if_init = cemac_ifinit; 609 ifp->if_stop = cemac_ifstop; 610 ifp->if_timer = 0; 611 ifp->if_softc = sc; 612 IFQ_SET_READY(&ifp->if_snd); 613 if_attach(ifp); 614 if_deferred_start_init(ifp, NULL); 615 ether_ifattach(ifp, (sc)->sc_enaddr); 616 } 617 618 static int 619 cemac_mediachange(struct ifnet *ifp) 620 { 621 if (ifp->if_flags & IFF_UP) 622 cemac_ifinit(ifp); 623 return 0; 624 } 625 626 static void 627 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 628 { 629 struct cemac_softc *sc = ifp->if_softc; 630 631 mii_pollstat(&sc->sc_mii); 632 ifmr->ifm_active = sc->sc_mii.mii_media_active; 633 ifmr->ifm_status = sc->sc_mii.mii_media_status; 634 } 635 636 637 static int 638 cemac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 639 { 640 struct cemac_softc *sc; 641 642 sc = device_private(self); 643 644 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 645 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 646 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 647 | ETH_MAN_CODE_IEEE802_3)); 648 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 649 ; 650 651 *val = CEMAC_READ(ETH_MAN) & ETH_MAN_DATA; 652 return 0; 653 } 654 655 static int 656 cemac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 657 { 658 struct cemac_softc *sc; 659 660 sc = device_private(self); 661 662 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 663 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 664 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 665 | ETH_MAN_CODE_IEEE802_3 666 | (val & ETH_MAN_DATA))); 667 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 668 ; 669 670 return 0; 671 } 672 673 674 static void 675 cemac_statchg(struct ifnet *ifp) 676 { 677 struct cemac_softc *sc = ifp->if_softc; 678 struct mii_data *mii = &sc->sc_mii; 679 uint32_t reg; 680 681 /* 682 * We must keep the MAC and the PHY in sync as 683 * to the status of full-duplex! 684 */ 685 reg = CEMAC_READ(ETH_CFG); 686 reg &= ~ETH_CFG_FD; 687 if (sc->sc_mii.mii_media_active & IFM_FDX) 688 reg |= ETH_CFG_FD; 689 690 reg &= ~ETH_CFG_SPD; 691 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 692 reg &= ~GEM_CFG_GEN; 693 switch (IFM_SUBTYPE(mii->mii_media_active)) { 694 case IFM_10_T: 695 break; 696 case IFM_100_TX: 697 reg |= ETH_CFG_SPD; 698 break; 699 case IFM_1000_T: 700 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 701 break; 702 default: 703 break; 704 } 705 CEMAC_WRITE(ETH_CFG, reg); 706 } 707 708 static void 709 cemac_tick(void *arg) 710 { 711 struct cemac_softc *sc = (struct cemac_softc *)arg; 712 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 713 int s; 714 715 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 716 if_statadd(ifp, if_collisions, 717 CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL)); 718 else 719 if_statadd(ifp, if_collisions, 720 CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL)); 721 722 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 723 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 724 uint32_t misses = CEMAC_READ(ETH_DRFC); 725 if (misses > 0) 726 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 727 } 728 729 s = splnet(); 730 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 731 cemac_ifstart(ifp); 732 splx(s); 733 734 mii_tick(&sc->sc_mii); 735 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 736 } 737 738 739 static int 740 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 741 { 742 int s, error; 743 744 s = splnet(); 745 switch (cmd) { 746 default: 747 error = ether_ioctl(ifp, cmd, data); 748 if (error != ENETRESET) 749 break; 750 error = 0; 751 752 if (cmd == SIOCSIFCAP) { 753 error = if_init(ifp); 754 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 755 ; 756 else if (ifp->if_flags & IFF_RUNNING) { 757 cemac_setaddr(ifp); 758 } 759 } 760 splx(s); 761 return error; 762 } 763 764 static void 765 cemac_ifstart(struct ifnet *ifp) 766 { 767 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 768 struct mbuf *m; 769 bus_dma_segment_t *segs; 770 int s, bi, err, nsegs; 771 772 s = splnet(); 773 start: 774 if (cemac_gctx(sc) == 0) { 775 /* Enable transmit-buffer-free interrupt */ 776 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 777 sc->tx_busy = true; 778 ifp->if_timer = 10; 779 splx(s); 780 return; 781 } 782 783 ifp->if_timer = 0; 784 785 IFQ_POLL(&ifp->if_snd, m); 786 if (m == NULL) { 787 splx(s); 788 return; 789 } 790 791 bi = (sc->txqi + sc->txqc) % TX_QLEN; 792 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 793 BUS_DMA_NOWAIT)) || 794 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 795 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 796 /* Copy entire mbuf chain to new single */ 797 struct mbuf *mn; 798 799 if (err == 0) 800 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 801 802 MGETHDR(mn, M_DONTWAIT, MT_DATA); 803 if (mn == NULL) goto stop; 804 if (m->m_pkthdr.len > MHLEN) { 805 MCLGET(mn, M_DONTWAIT); 806 if ((mn->m_flags & M_EXT) == 0) { 807 m_freem(mn); 808 goto stop; 809 } 810 } 811 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 812 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 813 IFQ_DEQUEUE(&ifp->if_snd, m); 814 m_freem(m); 815 m = mn; 816 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 817 BUS_DMA_NOWAIT); 818 } else { 819 IFQ_DEQUEUE(&ifp->if_snd, m); 820 } 821 822 bpf_mtap(ifp, m, BPF_D_OUT); 823 824 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 825 segs = sc->txq[bi].m_dmamap->dm_segs; 826 if (nsegs > 1) 827 panic("#### ARGH #2"); 828 829 sc->txq[bi].m = m; 830 sc->txqc++; 831 832 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 833 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void *)segs->ds_addr, 834 (unsigned)m->m_pkthdr.len)); 835 #ifdef DIAGNOSTIC 836 if (sc->txqc > TX_QLEN) 837 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 838 #endif 839 840 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 841 sc->txq[bi].m_dmamap->dm_mapsize, 842 BUS_DMASYNC_PREWRITE); 843 844 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 845 sc->TDSC[bi].Addr = segs->ds_addr; 846 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 847 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 848 849 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 850 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 851 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 852 __FUNCTION__, bi, sc->TDSC[bi].Info)); 853 854 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 855 CEMAC_WRITE(ETH_CTL, ctl); 856 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 857 } else { 858 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 859 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 860 } 861 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 862 goto start; 863 stop: 864 865 splx(s); 866 return; 867 } 868 869 static void 870 cemac_ifwatchdog(struct ifnet *ifp) 871 { 872 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 873 874 if ((ifp->if_flags & IFF_RUNNING) == 0) 875 return; 876 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 877 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 878 } 879 880 static int 881 cemac_ifinit(struct ifnet *ifp) 882 { 883 struct cemac_softc *sc = ifp->if_softc; 884 uint32_t dma, cfg; 885 int s = splnet(); 886 887 callout_stop(&sc->cemac_tick_ch); 888 889 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 890 891 if (ifp->if_capenable & 892 (IFCAP_CSUM_IPv4_Tx | 893 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 894 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 895 dma = CEMAC_READ(GEM_DMA_CFG); 896 dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 897 CEMAC_WRITE(GEM_DMA_CFG, dma); 898 } 899 if (ifp->if_capenable & 900 (IFCAP_CSUM_IPv4_Rx | 901 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 902 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 903 cfg = CEMAC_READ(ETH_CFG); 904 cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN; 905 CEMAC_WRITE(ETH_CFG, cfg); 906 } 907 } 908 909 // enable interrupts 910 CEMAC_WRITE(ETH_IDR, -1); 911 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 912 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 913 914 // enable transmitter / receiver 915 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 916 | ETH_CTL_CSR | ETH_CTL_MPE); 917 918 mii_mediachg(&sc->sc_mii); 919 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 920 ifp->if_flags |= IFF_RUNNING; 921 splx(s); 922 return 0; 923 } 924 925 static void 926 cemac_ifstop(struct ifnet *ifp, int disable) 927 { 928 // uint32_t u; 929 struct cemac_softc *sc = ifp->if_softc; 930 931 #if 0 932 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 933 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 934 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 935 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 936 CEMAC_WRITE(ETH_CFG, 937 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 938 else 939 CEMAC_WRITE(ETH_CFG, 940 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 941 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 942 // (void)CEMAC_READ(ETH_ISR); 943 u = CEMAC_READ(ETH_TSR); 944 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 945 | ETH_TSR_IDLE | ETH_TSR_RLE 946 | ETH_TSR_COL | ETH_TSR_OVR))); 947 u = CEMAC_READ(ETH_RSR); 948 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 949 #endif 950 callout_stop(&sc->cemac_tick_ch); 951 952 /* Down the MII. */ 953 mii_down(&sc->sc_mii); 954 955 ifp->if_flags &= ~IFF_RUNNING; 956 ifp->if_timer = 0; 957 sc->tx_busy = false; 958 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 959 } 960 961 static void 962 cemac_setaddr(struct ifnet *ifp) 963 { 964 struct cemac_softc *sc = ifp->if_softc; 965 struct ethercom *ec = &sc->sc_ethercom; 966 struct ether_multi *enm; 967 struct ether_multistep step; 968 uint8_t ias[3][ETHER_ADDR_LEN]; 969 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 970 uint32_t ctl = CEMAC_READ(ETH_CTL); 971 uint32_t cfg = CEMAC_READ(ETH_CFG); 972 973 /* disable receiver temporarily */ 974 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 975 976 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 977 978 if (ifp->if_flags & IFF_PROMISC) { 979 cfg |= ETH_CFG_CAF; 980 } else { 981 cfg &= ~ETH_CFG_CAF; 982 } 983 984 // ETH_CFG_BIG? 985 986 ifp->if_flags &= ~IFF_ALLMULTI; 987 988 ETHER_LOCK(ec); 989 ETHER_FIRST_MULTI(step, ec, enm); 990 while (enm != NULL) { 991 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 992 /* 993 * We must listen to a range of multicast addresses. 994 * For now, just accept all multicasts, rather than 995 * trying to set only those filter bits needed to match 996 * the range. (At this time, the only use of address 997 * ranges is for IP multicast routing, for which the 998 * range is big enough to require all bits set.) 999 */ 1000 cfg |= ETH_CFG_MTI; 1001 hashes[0] = 0xffffffffUL; 1002 hashes[1] = 0xffffffffUL; 1003 ifp->if_flags |= IFF_ALLMULTI; 1004 nma = 0; 1005 break; 1006 } 1007 1008 if (nma < 3) { 1009 /* We can program 3 perfect address filters for mcast */ 1010 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 1011 } else { 1012 /* 1013 * XXX: Datasheet is not very clear here, I'm not sure 1014 * if I'm doing this right. --joff 1015 */ 1016 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1017 1018 /* Just want the 6 most-significant bits. */ 1019 h = h >> 26; 1020 #if 0 1021 hashes[h / 32] |= (1 << (h % 32)); 1022 #else 1023 hashes[0] = 0xffffffffUL; 1024 hashes[1] = 0xffffffffUL; 1025 #endif 1026 cfg |= ETH_CFG_MTI; 1027 } 1028 ETHER_NEXT_MULTI(step, enm); 1029 nma++; 1030 } 1031 ETHER_UNLOCK(ec); 1032 1033 // program... 1034 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1035 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 1036 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 1037 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 1038 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 1039 | (sc->sc_enaddr[0])); 1040 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 1041 | (sc->sc_enaddr[4])); 1042 if (nma > 0) { 1043 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1044 ias[0][0], ias[0][1], ias[0][2], 1045 ias[0][3], ias[0][4], ias[0][5])); 1046 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 1047 | (ias[0][2] << 16) | (ias[0][1] << 8) 1048 | (ias[0][0])); 1049 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 1050 | (ias[0][5])); 1051 } 1052 if (nma > 1) { 1053 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1054 ias[1][0], ias[1][1], ias[1][2], 1055 ias[1][3], ias[1][4], ias[1][5])); 1056 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1057 | (ias[1][2] << 16) | (ias[1][1] << 8) 1058 | (ias[1][0])); 1059 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1060 | (ias[1][5])); 1061 } 1062 if (nma > 2) { 1063 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1064 ias[2][0], ias[2][1], ias[2][2], 1065 ias[2][3], ias[2][4], ias[2][5])); 1066 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1067 | (ias[2][2] << 16) | (ias[2][1] << 8) 1068 | (ias[2][0])); 1069 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1070 | (ias[2][5])); 1071 } 1072 CEMAC_GEM_WRITE(HSH, hashes[0]); 1073 CEMAC_GEM_WRITE(HSL, hashes[1]); 1074 CEMAC_WRITE(ETH_CFG, cfg); 1075 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1076 } 1077
Indexes created Fri Sep 26 20:09:58 GMT 2025