if_cemac.c revision 1.33
1 /* $NetBSD: if_cemac.c,v 1.33 2024/08/25 07:25:00 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.33 2024/08/25 07:25:00 skrll Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/types.h> 47 48 #include <sys/bus.h> 49 #include <sys/device.h> 50 #include <sys/kernel.h> 51 #include <sys/proc.h> 52 #include <sys/systm.h> 53 #include <sys/time.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 #include <net/bpf.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #include <dev/cadence/cemacreg.h> 74 #include <dev/cadence/if_cemacvar.h> 75 76 #define DEFAULT_MDCDIV 32 77 78 #define CEMAC_READ(x) \ 79 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 80 #define CEMAC_WRITE(x, y) \ 81 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 82 #define CEMAC_GEM_WRITE(x, y) \ 83 do { \ 84 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 85 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 86 else \ 87 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 88 } while(0) 89 90 static void cemac_init(struct cemac_softc *); 91 static int cemac_gctx(struct cemac_softc *); 92 static int cemac_mediachange(struct ifnet *); 93 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 94 static int cemac_mii_readreg(device_t, int, int, uint16_t *); 95 static int cemac_mii_writereg(device_t, int, int, uint16_t); 96 static void cemac_statchg(struct ifnet *); 97 static void cemac_tick(void *); 98 static int cemac_ifioctl(struct ifnet *, u_long, void *); 99 static void cemac_ifstart(struct ifnet *); 100 static void cemac_ifwatchdog(struct ifnet *); 101 static int cemac_ifinit(struct ifnet *); 102 static void cemac_ifstop(struct ifnet *, int); 103 static void cemac_setaddr(struct ifnet *); 104 105 #ifdef CEMAC_DEBUG 106 int cemac_debug = CEMAC_DEBUG; 107 #define DPRINTFN(n, fmt) if (cemac_debug >= (n)) printf fmt 108 #else 109 #define DPRINTFN(n, fmt) 110 #endif 111 112 void 113 cemac_attach_common(struct cemac_softc *sc) 114 { 115 uint32_t u; 116 117 aprint_naive("\n"); 118 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 119 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 120 else 121 aprint_normal(": Cadence Ethernet Controller\n"); 122 123 /* configure emac: */ 124 CEMAC_WRITE(ETH_CTL, 0); // disable everything 125 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 126 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 127 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 128 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 129 CEMAC_WRITE(ETH_CFG, 130 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 131 else 132 CEMAC_WRITE(ETH_CFG, 133 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 134 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 135 //(void)CEMAC_READ(ETH_ISR); 136 u = CEMAC_READ(ETH_TSR); 137 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 138 | ETH_TSR_IDLE | ETH_TSR_RLE 139 | ETH_TSR_COL | ETH_TSR_OVR))); 140 u = CEMAC_READ(ETH_RSR); 141 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 142 143 /* Fetch the Ethernet address from property if set. */ 144 prop_dictionary_t prop = device_properties(sc->sc_dev); 145 prop_data_t enaddr = prop_dictionary_get(prop, "mac-address"); 146 147 if (enaddr != NULL) { 148 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 149 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 150 memcpy(sc->sc_enaddr, prop_data_value(enaddr), 151 ETHER_ADDR_LEN); 152 } else { 153 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 154 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 155 }; 156 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 157 } 158 159 cemac_init(sc); 160 } 161 162 static int 163 cemac_gctx(struct cemac_softc *sc) 164 { 165 uint32_t tsr; 166 167 tsr = CEMAC_READ(ETH_TSR); 168 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 169 // no space left 170 if (!(tsr & ETH_TSR_BNQ)) 171 return 0; 172 } else { 173 if (tsr & GEM_TSR_TXGO) 174 return 0; 175 } 176 CEMAC_WRITE(ETH_TSR, tsr); 177 178 // free sent frames 179 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 180 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 181 int bi = sc->txqi % TX_QLEN; 182 183 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 184 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 185 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 186 __FUNCTION__, bi, sc->TDSC[bi].Info)); 187 188 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 189 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 190 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 191 m_freem(sc->txq[bi].m); 192 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 193 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 194 sc->txq[bi].m = NULL; 195 sc->txqi = (bi + 1) % TX_QLEN; 196 sc->txqc--; 197 } 198 199 // mark we're free 200 if (sc->tx_busy) { 201 sc->tx_busy = false; 202 /* Disable transmit-buffer-free interrupt */ 203 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 204 } 205 206 return 1; 207 } 208 209 int 210 cemac_intr(void *arg) 211 { 212 struct cemac_softc *sc = (struct cemac_softc *)arg; 213 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 214 uint32_t imr, isr, ctl; 215 #ifdef CEMAC_DEBUG 216 uint32_t rsr; 217 #endif 218 int bi; 219 220 imr = ~CEMAC_READ(ETH_IMR); 221 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE | 222 ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM))) { 223 // interrupt not enabled, can't be us 224 return 0; 225 } 226 227 isr = CEMAC_READ(ETH_ISR); 228 CEMAC_WRITE(ETH_ISR, isr); 229 isr &= imr; 230 #ifdef CEMAC_DEBUG 231 rsr = CEMAC_READ(ETH_RSR); // get receive status register 232 #endif 233 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 234 235 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 236 if (isr & ETH_ISR_RBNA) { // out of receive buffers 237 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 238 ctl = CEMAC_READ(ETH_CTL); // get current control register value 239 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 240 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 241 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 242 if_statinc_ref(ifp, nsr, if_ierrors); 243 if_statinc_ref(ifp, nsr, if_ipackets); 244 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 245 } 246 if (isr & ETH_ISR_ROVR) { 247 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 248 if_statinc_ref(ifp, nsr, if_ierrors); 249 if_statinc_ref(ifp, nsr, if_ipackets); 250 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 251 } 252 253 if (isr & ETH_ISR_RCOM) { // packet has been received! 254 uint32_t nfo; 255 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 256 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 257 int fl, csum; 258 struct mbuf *m; 259 260 nfo = sc->RDSC[bi].Info; 261 fl = (nfo & ETH_RDSC_I_LEN) - 4; 262 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 263 264 MGETHDR(m, M_DONTWAIT, MT_DATA); 265 if (m != NULL) MCLGET(m, M_DONTWAIT); 266 if (m != NULL && (m->m_flags & M_EXT)) { 267 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 268 MCLBYTES, BUS_DMASYNC_POSTREAD); 269 bus_dmamap_unload(sc->sc_dmat, 270 sc->rxq[bi].m_dmamap); 271 m_set_rcvif(sc->rxq[bi].m, ifp); 272 sc->rxq[bi].m->m_pkthdr.len = 273 sc->rxq[bi].m->m_len = fl; 274 switch (nfo & ETH_RDSC_I_CHKSUM) { 275 case ETH_RDSC_I_CHKSUM_IP: 276 csum = M_CSUM_IPv4; 277 break; 278 case ETH_RDSC_I_CHKSUM_UDP: 279 csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 280 M_CSUM_UDPv6; 281 break; 282 case ETH_RDSC_I_CHKSUM_TCP: 283 csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 284 M_CSUM_TCPv6; 285 break; 286 default: 287 csum = 0; 288 break; 289 } 290 sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 291 DPRINTFN(2,("received %u bytes packet\n", fl)); 292 if_percpuq_enqueue(ifp->if_percpuq, 293 sc->rxq[bi].m); 294 if (mtod(m, intptr_t) & 3) 295 m_adj(m, mtod(m, intptr_t) & 3); 296 sc->rxq[bi].m = m; 297 bus_dmamap_load(sc->sc_dmat, 298 sc->rxq[bi].m_dmamap, 299 m->m_ext.ext_buf, MCLBYTES, 300 NULL, BUS_DMA_NOWAIT); 301 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 302 MCLBYTES, BUS_DMASYNC_PREREAD); 303 sc->RDSC[bi].Info = 0; 304 sc->RDSC[bi].Addr = 305 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 306 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 307 } else { 308 /* Drop packets until we can get replacement 309 * empty mbufs for the RXDQ. 310 */ 311 m_freem(m); 312 if_statinc_ref(ifp, nsr, if_ierrors); 313 } 314 sc->rxqi++; 315 } 316 } 317 318 IF_STAT_PUTREF(ifp); 319 320 if (cemac_gctx(sc) > 0) 321 if_schedule_deferred_start(ifp); 322 #if 0 // reloop 323 irq = CEMAC_READ(IntStsC); 324 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 325 goto begin; 326 #endif 327 328 return 1; 329 } 330 331 332 static void 333 cemac_init(struct cemac_softc *sc) 334 { 335 bus_dma_segment_t segs; 336 int rsegs, err, i; 337 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 338 struct mii_data * const mii = &sc->sc_mii; 339 uint32_t u; 340 #if 0 341 int mdcdiv = DEFAULT_MDCDIV; 342 #endif 343 344 callout_init(&sc->cemac_tick_ch, 0); 345 346 // ok... 347 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 348 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 349 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 350 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 351 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 352 CEMAC_WRITE(ETH_CFG, 353 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 354 else 355 CEMAC_WRITE(ETH_CFG, 356 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 357 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 358 CEMAC_WRITE(GEM_DMA_CFG, 359 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 360 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 361 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 362 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 363 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 364 } 365 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 366 // (void)CEMAC_READ(ETH_ISR); 367 u = CEMAC_READ(ETH_TSR); 368 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 369 | ETH_TSR_IDLE | ETH_TSR_RLE 370 | ETH_TSR_COL | ETH_TSR_OVR))); 371 u = CEMAC_READ(ETH_RSR); 372 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 373 374 #if 0 375 if (device_cfdata(sc->sc_dev)->cf_flags) 376 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 377 #endif 378 /* set ethernet address */ 379 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 380 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 381 | (sc->sc_enaddr[0])); 382 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 383 | (sc->sc_enaddr[4])); 384 CEMAC_GEM_WRITE(SA2L, 0); 385 CEMAC_GEM_WRITE(SA2H, 0); 386 CEMAC_GEM_WRITE(SA3L, 0); 387 CEMAC_GEM_WRITE(SA3H, 0); 388 CEMAC_GEM_WRITE(SA4L, 0); 389 CEMAC_GEM_WRITE(SA4H, 0); 390 391 /* Allocate a page of memory for receive queue descriptors */ 392 sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 393 sc->rbqlen *= PAGE_SIZE; 394 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 395 396 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 397 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 398 &segs, 1, &rsegs, BUS_DMA_WAITOK); 399 if (err == 0) { 400 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 401 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 402 &sc->rbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 403 } 404 if (err == 0) { 405 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 406 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 407 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 408 &sc->rbqpage_dmamap); 409 } 410 if (err == 0) { 411 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 412 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 413 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 414 } 415 if (err != 0) 416 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 417 418 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 419 memset(sc->rbqpage, 0, sc->rbqlen); 420 421 /* Allocate a page of memory for transmit queue descriptors */ 422 sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 423 sc->tbqlen *= PAGE_SIZE; 424 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 425 426 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 427 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 428 &segs, 1, &rsegs, BUS_DMA_WAITOK); 429 if (err == 0) { 430 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 431 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 432 &sc->tbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 433 } 434 if (err == 0) { 435 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 436 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 437 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 438 &sc->tbqpage_dmamap); 439 } 440 if (err == 0) { 441 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 442 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 443 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 444 } 445 if (err != 0) 446 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 447 448 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 449 memset(sc->tbqpage, 0, sc->tbqlen); 450 451 /* Set up pointers to start of each queue in kernel addr space. 452 * Each descriptor queue or status queue entry uses 2 words 453 */ 454 sc->RDSC = (void *)sc->rbqpage; 455 sc->TDSC = (void *)sc->tbqpage; 456 457 /* init TX queue */ 458 for (i = 0; i < TX_QLEN; i++) { 459 sc->TDSC[i].Addr = 0; 460 sc->TDSC[i].Info = ETH_TDSC_I_USED | 461 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 462 } 463 464 /* Populate the RXQ with mbufs */ 465 sc->rxqi = 0; 466 for (i = 0; i < RX_QLEN; i++) { 467 struct mbuf *m; 468 469 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 470 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 471 if (err) { 472 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 473 } 474 MGETHDR(m, M_WAIT, MT_DATA); 475 MCLGET(m, M_WAIT); 476 sc->rxq[i].m = m; 477 if (mtod(m, intptr_t) & 3) { 478 m_adj(m, mtod(m, intptr_t) & 3); 479 } 480 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 481 m->m_ext.ext_buf, MCLBYTES, NULL, 482 BUS_DMA_WAITOK); 483 if (err) { 484 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 485 } 486 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 487 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 488 sc->RDSC[i].Info = 0; 489 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 490 MCLBYTES, BUS_DMASYNC_PREREAD); 491 } 492 493 /* prepare transmit queue */ 494 for (i = 0; i < TX_QLEN; i++) { 495 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 496 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 497 &sc->txq[i].m_dmamap); 498 if (err) 499 panic("ARGH #1"); 500 sc->txq[i].m = NULL; 501 } 502 503 /* Program each queue's start addr, cur addr, and len registers 504 * with the physical addresses. 505 */ 506 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 507 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 508 509 /* Divide HCLK by 32 for MDC clock */ 510 sc->sc_ethercom.ec_mii = mii; 511 mii->mii_ifp = ifp; 512 mii->mii_readreg = cemac_mii_readreg; 513 mii->mii_writereg = cemac_mii_writereg; 514 mii->mii_statchg = cemac_statchg; 515 ifmedia_init(&mii->mii_media, IFM_IMASK, cemac_mediachange, 516 cemac_mediastatus); 517 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1, 0); 518 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 519 520 #if 0 521 // enable / disable interrupts 522 CEMAC_WRITE(ETH_IDR, -1); 523 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 524 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 525 // (void)CEMAC_READ(ETH_ISR); // why 526 527 // enable transmitter / receiver 528 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 529 | ETH_CTL_CSR | ETH_CTL_MPE); 530 #endif 531 /* 532 * We can support hardware checksumming. 533 */ 534 ifp->if_capabilities |= 535 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 536 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 537 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 538 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 539 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 540 541 /* 542 * We can support 802.1Q VLAN-sized frames. 543 */ 544 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 545 546 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 547 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 548 ifp->if_ioctl = cemac_ifioctl; 549 ifp->if_start = cemac_ifstart; 550 ifp->if_watchdog = cemac_ifwatchdog; 551 ifp->if_init = cemac_ifinit; 552 ifp->if_stop = cemac_ifstop; 553 ifp->if_timer = 0; 554 ifp->if_softc = sc; 555 IFQ_SET_READY(&ifp->if_snd); 556 if_attach(ifp); 557 if_deferred_start_init(ifp, NULL); 558 ether_ifattach(ifp, (sc)->sc_enaddr); 559 } 560 561 static int 562 cemac_mediachange(struct ifnet *ifp) 563 { 564 if (ifp->if_flags & IFF_UP) 565 cemac_ifinit(ifp); 566 return 0; 567 } 568 569 static void 570 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 571 { 572 struct cemac_softc *sc = ifp->if_softc; 573 574 mii_pollstat(&sc->sc_mii); 575 ifmr->ifm_active = sc->sc_mii.mii_media_active; 576 ifmr->ifm_status = sc->sc_mii.mii_media_status; 577 } 578 579 580 static int 581 cemac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 582 { 583 struct cemac_softc *sc; 584 585 sc = device_private(self); 586 587 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 588 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 589 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 590 | ETH_MAN_CODE_IEEE802_3)); 591 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 592 ; 593 594 *val = CEMAC_READ(ETH_MAN) & ETH_MAN_DATA; 595 return 0; 596 } 597 598 static int 599 cemac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 600 { 601 struct cemac_softc *sc; 602 603 sc = device_private(self); 604 605 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 606 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 607 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 608 | ETH_MAN_CODE_IEEE802_3 609 | (val & ETH_MAN_DATA))); 610 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 611 ; 612 613 return 0; 614 } 615 616 617 static void 618 cemac_statchg(struct ifnet *ifp) 619 { 620 struct cemac_softc *sc = ifp->if_softc; 621 struct mii_data *mii = &sc->sc_mii; 622 uint32_t reg; 623 624 /* 625 * We must keep the MAC and the PHY in sync as 626 * to the status of full-duplex! 627 */ 628 reg = CEMAC_READ(ETH_CFG); 629 reg &= ~ETH_CFG_FD; 630 if (sc->sc_mii.mii_media_active & IFM_FDX) 631 reg |= ETH_CFG_FD; 632 633 reg &= ~ETH_CFG_SPD; 634 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 635 reg &= ~GEM_CFG_GEN; 636 switch (IFM_SUBTYPE(mii->mii_media_active)) { 637 case IFM_10_T: 638 break; 639 case IFM_100_TX: 640 reg |= ETH_CFG_SPD; 641 break; 642 case IFM_1000_T: 643 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 644 break; 645 default: 646 break; 647 } 648 CEMAC_WRITE(ETH_CFG, reg); 649 } 650 651 static void 652 cemac_tick(void *arg) 653 { 654 struct cemac_softc *sc = (struct cemac_softc *)arg; 655 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 656 int s; 657 658 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 659 if_statadd(ifp, if_collisions, 660 CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL)); 661 else 662 if_statadd(ifp, if_collisions, 663 CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL)); 664 665 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 666 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 667 uint32_t misses = CEMAC_READ(ETH_DRFC); 668 if (misses > 0) 669 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 670 } 671 672 s = splnet(); 673 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 674 cemac_ifstart(ifp); 675 splx(s); 676 677 mii_tick(&sc->sc_mii); 678 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 679 } 680 681 682 static int 683 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 684 { 685 int s, error; 686 687 s = splnet(); 688 switch (cmd) { 689 default: 690 error = ether_ioctl(ifp, cmd, data); 691 if (error != ENETRESET) 692 break; 693 error = 0; 694 695 if (cmd == SIOCSIFCAP) { 696 error = if_init(ifp); 697 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 698 ; 699 else if (ifp->if_flags & IFF_RUNNING) { 700 cemac_setaddr(ifp); 701 } 702 } 703 splx(s); 704 return error; 705 } 706 707 static void 708 cemac_ifstart(struct ifnet *ifp) 709 { 710 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 711 struct mbuf *m; 712 bus_dma_segment_t *segs; 713 int s, bi, err, nsegs; 714 715 s = splnet(); 716 start: 717 if (cemac_gctx(sc) == 0) { 718 /* Enable transmit-buffer-free interrupt */ 719 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 720 sc->tx_busy = true; 721 ifp->if_timer = 10; 722 splx(s); 723 return; 724 } 725 726 ifp->if_timer = 0; 727 728 IFQ_POLL(&ifp->if_snd, m); 729 if (m == NULL) { 730 splx(s); 731 return; 732 } 733 734 bi = (sc->txqi + sc->txqc) % TX_QLEN; 735 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 736 BUS_DMA_NOWAIT)) || 737 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 738 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 739 /* Copy entire mbuf chain to new single */ 740 struct mbuf *mn; 741 742 if (err == 0) 743 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 744 745 MGETHDR(mn, M_DONTWAIT, MT_DATA); 746 if (mn == NULL) goto stop; 747 if (m->m_pkthdr.len > MHLEN) { 748 MCLGET(mn, M_DONTWAIT); 749 if ((mn->m_flags & M_EXT) == 0) { 750 m_freem(mn); 751 goto stop; 752 } 753 } 754 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 755 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 756 IFQ_DEQUEUE(&ifp->if_snd, m); 757 m_freem(m); 758 m = mn; 759 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 760 BUS_DMA_NOWAIT); 761 } else { 762 IFQ_DEQUEUE(&ifp->if_snd, m); 763 } 764 765 bpf_mtap(ifp, m, BPF_D_OUT); 766 767 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 768 segs = sc->txq[bi].m_dmamap->dm_segs; 769 if (nsegs > 1) 770 panic("#### ARGH #2"); 771 772 sc->txq[bi].m = m; 773 sc->txqc++; 774 775 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 776 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void *)segs->ds_addr, 777 (unsigned)m->m_pkthdr.len)); 778 #ifdef DIAGNOSTIC 779 if (sc->txqc > TX_QLEN) 780 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 781 #endif 782 783 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 784 sc->txq[bi].m_dmamap->dm_mapsize, 785 BUS_DMASYNC_PREWRITE); 786 787 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 788 sc->TDSC[bi].Addr = segs->ds_addr; 789 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 790 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 791 792 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 793 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 794 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 795 __FUNCTION__, bi, sc->TDSC[bi].Info)); 796 797 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 798 CEMAC_WRITE(ETH_CTL, ctl); 799 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 800 } else { 801 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 802 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 803 } 804 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 805 goto start; 806 stop: 807 808 splx(s); 809 return; 810 } 811 812 static void 813 cemac_ifwatchdog(struct ifnet *ifp) 814 { 815 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 816 817 if ((ifp->if_flags & IFF_RUNNING) == 0) 818 return; 819 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 820 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 821 } 822 823 static int 824 cemac_ifinit(struct ifnet *ifp) 825 { 826 struct cemac_softc *sc = ifp->if_softc; 827 uint32_t dma, cfg; 828 int s = splnet(); 829 830 callout_stop(&sc->cemac_tick_ch); 831 832 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 833 834 if (ifp->if_capenable & 835 (IFCAP_CSUM_IPv4_Tx | 836 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 837 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 838 dma = CEMAC_READ(GEM_DMA_CFG); 839 dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 840 CEMAC_WRITE(GEM_DMA_CFG, dma); 841 } 842 if (ifp->if_capenable & 843 (IFCAP_CSUM_IPv4_Rx | 844 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 845 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 846 cfg = CEMAC_READ(ETH_CFG); 847 cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN; 848 CEMAC_WRITE(ETH_CFG, cfg); 849 } 850 } 851 852 // enable interrupts 853 CEMAC_WRITE(ETH_IDR, -1); 854 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 855 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 856 857 // enable transmitter / receiver 858 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 859 | ETH_CTL_CSR | ETH_CTL_MPE); 860 861 mii_mediachg(&sc->sc_mii); 862 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 863 ifp->if_flags |= IFF_RUNNING; 864 splx(s); 865 return 0; 866 } 867 868 static void 869 cemac_ifstop(struct ifnet *ifp, int disable) 870 { 871 // uint32_t u; 872 struct cemac_softc *sc = ifp->if_softc; 873 874 #if 0 875 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 876 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 877 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 878 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 879 CEMAC_WRITE(ETH_CFG, 880 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 881 else 882 CEMAC_WRITE(ETH_CFG, 883 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 884 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 885 // (void)CEMAC_READ(ETH_ISR); 886 u = CEMAC_READ(ETH_TSR); 887 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 888 | ETH_TSR_IDLE | ETH_TSR_RLE 889 | ETH_TSR_COL | ETH_TSR_OVR))); 890 u = CEMAC_READ(ETH_RSR); 891 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 892 #endif 893 callout_stop(&sc->cemac_tick_ch); 894 895 /* Down the MII. */ 896 mii_down(&sc->sc_mii); 897 898 ifp->if_flags &= ~IFF_RUNNING; 899 ifp->if_timer = 0; 900 sc->tx_busy = false; 901 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 902 } 903 904 static void 905 cemac_setaddr(struct ifnet *ifp) 906 { 907 struct cemac_softc *sc = ifp->if_softc; 908 struct ethercom *ec = &sc->sc_ethercom; 909 struct ether_multi *enm; 910 struct ether_multistep step; 911 uint8_t ias[3][ETHER_ADDR_LEN]; 912 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 913 uint32_t ctl = CEMAC_READ(ETH_CTL); 914 uint32_t cfg = CEMAC_READ(ETH_CFG); 915 916 /* disable receiver temporarily */ 917 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 918 919 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 920 921 if (ifp->if_flags & IFF_PROMISC) { 922 cfg |= ETH_CFG_CAF; 923 } else { 924 cfg &= ~ETH_CFG_CAF; 925 } 926 927 // ETH_CFG_BIG? 928 929 ifp->if_flags &= ~IFF_ALLMULTI; 930 931 ETHER_LOCK(ec); 932 ETHER_FIRST_MULTI(step, ec, enm); 933 while (enm != NULL) { 934 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 935 /* 936 * We must listen to a range of multicast addresses. 937 * For now, just accept all multicasts, rather than 938 * trying to set only those filter bits needed to match 939 * the range. (At this time, the only use of address 940 * ranges is for IP multicast routing, for which the 941 * range is big enough to require all bits set.) 942 */ 943 cfg |= ETH_CFG_MTI; 944 hashes[0] = 0xffffffffUL; 945 hashes[1] = 0xffffffffUL; 946 ifp->if_flags |= IFF_ALLMULTI; 947 nma = 0; 948 break; 949 } 950 951 if (nma < 3) { 952 /* We can program 3 perfect address filters for mcast */ 953 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 954 } else { 955 /* 956 * XXX: Datasheet is not very clear here, I'm not sure 957 * if I'm doing this right. --joff 958 */ 959 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 960 961 /* Just want the 6 most-significant bits. */ 962 h = h >> 26; 963 #if 0 964 hashes[h / 32] |= (1 << (h % 32)); 965 #else 966 hashes[0] = 0xffffffffUL; 967 hashes[1] = 0xffffffffUL; 968 #endif 969 cfg |= ETH_CFG_MTI; 970 } 971 ETHER_NEXT_MULTI(step, enm); 972 nma++; 973 } 974 ETHER_UNLOCK(ec); 975 976 // program... 977 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 978 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 979 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 980 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 981 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 982 | (sc->sc_enaddr[0])); 983 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 984 | (sc->sc_enaddr[4])); 985 if (nma > 0) { 986 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 987 ias[0][0], ias[0][1], ias[0][2], 988 ias[0][3], ias[0][4], ias[0][5])); 989 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 990 | (ias[0][2] << 16) | (ias[0][1] << 8) 991 | (ias[0][0])); 992 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 993 | (ias[0][5])); 994 } 995 if (nma > 1) { 996 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 997 ias[1][0], ias[1][1], ias[1][2], 998 ias[1][3], ias[1][4], ias[1][5])); 999 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1000 | (ias[1][2] << 16) | (ias[1][1] << 8) 1001 | (ias[1][0])); 1002 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1003 | (ias[1][5])); 1004 } 1005 if (nma > 2) { 1006 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1007 ias[2][0], ias[2][1], ias[2][2], 1008 ias[2][3], ias[2][4], ias[2][5])); 1009 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1010 | (ias[2][2] << 16) | (ias[2][1] << 8) 1011 | (ias[2][0])); 1012 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1013 | (ias[2][5])); 1014 } 1015 CEMAC_GEM_WRITE(HSH, hashes[0]); 1016 CEMAC_GEM_WRITE(HSL, hashes[1]); 1017 CEMAC_WRITE(ETH_CFG, cfg); 1018 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1019 } 1020
Indexes created Fri Sep 26 20:09:58 GMT 2025