if_cemac.c revision 1.35
1 /* $NetBSD: if_cemac.c,v 1.35 2024/08/25 16:06:46 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.35 2024/08/25 16:06:46 skrll Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/types.h> 47 48 #include <sys/bus.h> 49 #include <sys/device.h> 50 #include <sys/kernel.h> 51 #include <sys/proc.h> 52 #include <sys/systm.h> 53 #include <sys/time.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 #include <net/bpf.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #include <dev/cadence/cemacreg.h> 74 #include <dev/cadence/if_cemacvar.h> 75 76 #define DEFAULT_MDCDIV 32 77 78 #define CEMAC_READ(x) \ 79 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 80 #define CEMAC_WRITE(x, y) \ 81 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 82 #define CEMAC_GEM_WRITE(x, y) \ 83 do { \ 84 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 85 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 86 else \ 87 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 88 } while(0) 89 90 static void cemac_init(struct cemac_softc *); 91 static int cemac_gctx(struct cemac_softc *); 92 static int cemac_mediachange(struct ifnet *); 93 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 94 static int cemac_mii_readreg(device_t, int, int, uint16_t *); 95 static int cemac_mii_writereg(device_t, int, int, uint16_t); 96 static void cemac_statchg(struct ifnet *); 97 static void cemac_tick(void *); 98 static int cemac_ifioctl(struct ifnet *, u_long, void *); 99 static void cemac_ifstart(struct ifnet *); 100 static void cemac_ifwatchdog(struct ifnet *); 101 static int cemac_ifinit(struct ifnet *); 102 static void cemac_ifstop(struct ifnet *, int); 103 static void cemac_setaddr(struct ifnet *); 104 105 #ifdef CEMAC_DEBUG 106 int cemac_debug = CEMAC_DEBUG; 107 #define DPRINTFN(n, fmt) if (cemac_debug >= (n)) printf fmt 108 #else 109 #define DPRINTFN(n, fmt) 110 #endif 111 112 void 113 cemac_attach_common(struct cemac_softc *sc) 114 { 115 uint32_t u; 116 117 aprint_naive("\n"); 118 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 119 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 120 else 121 aprint_normal(": Cadence Ethernet Controller\n"); 122 123 /* configure emac: */ 124 CEMAC_WRITE(ETH_CTL, 0); // disable everything 125 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 126 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 127 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 128 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 129 CEMAC_WRITE(ETH_CFG, 130 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 131 else 132 CEMAC_WRITE(ETH_CFG, 133 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 134 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 135 //(void)CEMAC_READ(ETH_ISR); 136 u = CEMAC_READ(ETH_TSR); 137 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 138 | ETH_TSR_IDLE | ETH_TSR_RLE 139 | ETH_TSR_COL | ETH_TSR_OVR))); 140 u = CEMAC_READ(ETH_RSR); 141 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 142 143 /* Fetch the Ethernet address from property if set. */ 144 prop_dictionary_t prop = device_properties(sc->sc_dev); 145 prop_data_t enaddr = prop_dictionary_get(prop, "mac-address"); 146 147 if (enaddr != NULL) { 148 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 149 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 150 memcpy(sc->sc_enaddr, prop_data_value(enaddr), 151 ETHER_ADDR_LEN); 152 } else { 153 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 154 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 155 }; 156 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 157 } 158 159 cemac_init(sc); 160 } 161 162 static int 163 cemac_gctx(struct cemac_softc *sc) 164 { 165 uint32_t tsr; 166 167 tsr = CEMAC_READ(ETH_TSR); 168 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 169 // no space left 170 if (!(tsr & ETH_TSR_BNQ)) 171 return 0; 172 } else { 173 if (tsr & GEM_TSR_TXGO) 174 return 0; 175 } 176 CEMAC_WRITE(ETH_TSR, tsr); 177 178 // free sent frames 179 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 180 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 181 int bi = sc->txqi % TX_QLEN; 182 183 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 184 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 185 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 186 __FUNCTION__, bi, sc->TDSC[bi].Info)); 187 188 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 189 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 190 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 191 m_freem(sc->txq[bi].m); 192 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 193 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 194 sc->txq[bi].m = NULL; 195 sc->txqi = (bi + 1) % TX_QLEN; 196 sc->txqc--; 197 } 198 199 // mark we're free 200 if (sc->tx_busy) { 201 sc->tx_busy = false; 202 /* Disable transmit-buffer-free interrupt */ 203 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 204 } 205 206 return 1; 207 } 208 209 int 210 cemac_intr(void *arg) 211 { 212 struct cemac_softc * const sc = arg; 213 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 214 uint32_t imr, isr, ctl; 215 #ifdef CEMAC_DEBUG 216 uint32_t rsr; 217 #endif 218 int bi; 219 220 imr = ~CEMAC_READ(ETH_IMR); 221 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE | 222 ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM))) { 223 // interrupt not enabled, can't be us 224 return 0; 225 } 226 227 isr = CEMAC_READ(ETH_ISR); 228 CEMAC_WRITE(ETH_ISR, isr); 229 isr &= imr; 230 #ifdef CEMAC_DEBUG 231 rsr = CEMAC_READ(ETH_RSR); // get receive status register 232 #endif 233 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 234 235 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 236 if (isr & ETH_ISR_RBNA) { // out of receive buffers 237 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 238 ctl = CEMAC_READ(ETH_CTL); // get current control register value 239 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 240 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 241 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 242 if_statinc_ref(ifp, nsr, if_ierrors); 243 if_statinc_ref(ifp, nsr, if_ipackets); 244 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 245 } 246 if (isr & ETH_ISR_ROVR) { 247 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 248 if_statinc_ref(ifp, nsr, if_ierrors); 249 if_statinc_ref(ifp, nsr, if_ipackets); 250 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 251 } 252 253 if (isr & ETH_ISR_RCOM) { // packet has been received! 254 uint32_t nfo; 255 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 256 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 257 int fl, csum; 258 struct mbuf *m; 259 260 nfo = sc->RDSC[bi].Info; 261 fl = (nfo & ETH_RDSC_I_LEN) - 4; 262 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 263 264 MGETHDR(m, M_DONTWAIT, MT_DATA); 265 if (m != NULL) 266 MCLGET(m, M_DONTWAIT); 267 if (m != NULL && (m->m_flags & M_EXT)) { 268 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 269 MCLBYTES, BUS_DMASYNC_POSTREAD); 270 bus_dmamap_unload(sc->sc_dmat, 271 sc->rxq[bi].m_dmamap); 272 m_set_rcvif(sc->rxq[bi].m, ifp); 273 sc->rxq[bi].m->m_pkthdr.len = 274 sc->rxq[bi].m->m_len = fl; 275 switch (nfo & ETH_RDSC_I_CHKSUM) { 276 case ETH_RDSC_I_CHKSUM_IP: 277 csum = M_CSUM_IPv4; 278 break; 279 case ETH_RDSC_I_CHKSUM_UDP: 280 csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 281 M_CSUM_UDPv6; 282 break; 283 case ETH_RDSC_I_CHKSUM_TCP: 284 csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 285 M_CSUM_TCPv6; 286 break; 287 default: 288 csum = 0; 289 break; 290 } 291 sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 292 DPRINTFN(2,("received %u bytes packet\n", fl)); 293 if_percpuq_enqueue(ifp->if_percpuq, 294 sc->rxq[bi].m); 295 if (mtod(m, intptr_t) & 3) 296 m_adj(m, mtod(m, intptr_t) & 3); 297 sc->rxq[bi].m = m; 298 bus_dmamap_load(sc->sc_dmat, 299 sc->rxq[bi].m_dmamap, 300 m->m_ext.ext_buf, MCLBYTES, 301 NULL, BUS_DMA_NOWAIT); 302 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 303 MCLBYTES, BUS_DMASYNC_PREREAD); 304 sc->RDSC[bi].Info = 0; 305 sc->RDSC[bi].Addr = 306 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 307 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 308 } else { 309 /* Drop packets until we can get replacement 310 * empty mbufs for the RXDQ. 311 */ 312 m_freem(m); 313 if_statinc_ref(ifp, nsr, if_ierrors); 314 } 315 sc->rxqi++; 316 } 317 } 318 319 IF_STAT_PUTREF(ifp); 320 321 if (cemac_gctx(sc) > 0) 322 if_schedule_deferred_start(ifp); 323 #if 0 // reloop 324 irq = CEMAC_READ(IntStsC); 325 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 326 goto begin; 327 #endif 328 329 return 1; 330 } 331 332 333 static void 334 cemac_init(struct cemac_softc *sc) 335 { 336 bus_dma_segment_t segs; 337 int rsegs, err, i; 338 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 339 struct mii_data * const mii = &sc->sc_mii; 340 uint32_t u; 341 #if 0 342 int mdcdiv = DEFAULT_MDCDIV; 343 #endif 344 345 callout_init(&sc->cemac_tick_ch, 0); 346 347 // ok... 348 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 349 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 350 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 351 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 352 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 353 CEMAC_WRITE(ETH_CFG, 354 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 355 else 356 CEMAC_WRITE(ETH_CFG, 357 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 358 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 359 CEMAC_WRITE(GEM_DMA_CFG, 360 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 361 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 362 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 363 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 364 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 365 } 366 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 367 // (void)CEMAC_READ(ETH_ISR); 368 u = CEMAC_READ(ETH_TSR); 369 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 370 | ETH_TSR_IDLE | ETH_TSR_RLE 371 | ETH_TSR_COL | ETH_TSR_OVR))); 372 u = CEMAC_READ(ETH_RSR); 373 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 374 375 #if 0 376 if (device_cfdata(sc->sc_dev)->cf_flags) 377 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 378 #endif 379 /* set ethernet address */ 380 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 381 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 382 | (sc->sc_enaddr[0])); 383 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 384 | (sc->sc_enaddr[4])); 385 CEMAC_GEM_WRITE(SA2L, 0); 386 CEMAC_GEM_WRITE(SA2H, 0); 387 CEMAC_GEM_WRITE(SA3L, 0); 388 CEMAC_GEM_WRITE(SA3H, 0); 389 CEMAC_GEM_WRITE(SA4L, 0); 390 CEMAC_GEM_WRITE(SA4H, 0); 391 392 /* Allocate a page of memory for receive queue descriptors */ 393 sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 394 sc->rbqlen *= PAGE_SIZE; 395 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 396 397 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 398 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 399 &segs, 1, &rsegs, BUS_DMA_WAITOK); 400 if (err == 0) { 401 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 402 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 403 &sc->rbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 404 } 405 if (err == 0) { 406 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 407 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 408 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 409 &sc->rbqpage_dmamap); 410 } 411 if (err == 0) { 412 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 413 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 414 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 415 } 416 if (err != 0) 417 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 418 419 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 420 memset(sc->rbqpage, 0, sc->rbqlen); 421 422 /* Allocate a page of memory for transmit queue descriptors */ 423 sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 424 sc->tbqlen *= PAGE_SIZE; 425 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 426 427 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 428 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 429 &segs, 1, &rsegs, BUS_DMA_WAITOK); 430 if (err == 0) { 431 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 432 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 433 &sc->tbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 434 } 435 if (err == 0) { 436 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 437 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 438 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 439 &sc->tbqpage_dmamap); 440 } 441 if (err == 0) { 442 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 443 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 444 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 445 } 446 if (err != 0) 447 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 448 449 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 450 memset(sc->tbqpage, 0, sc->tbqlen); 451 452 /* Set up pointers to start of each queue in kernel addr space. 453 * Each descriptor queue or status queue entry uses 2 words 454 */ 455 sc->RDSC = (void *)sc->rbqpage; 456 sc->TDSC = (void *)sc->tbqpage; 457 458 /* init TX queue */ 459 for (i = 0; i < TX_QLEN; i++) { 460 sc->TDSC[i].Addr = 0; 461 sc->TDSC[i].Info = ETH_TDSC_I_USED | 462 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 463 } 464 465 /* Populate the RXQ with mbufs */ 466 sc->rxqi = 0; 467 for (i = 0; i < RX_QLEN; i++) { 468 struct mbuf *m; 469 470 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 471 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 472 if (err) { 473 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 474 } 475 MGETHDR(m, M_WAIT, MT_DATA); 476 MCLGET(m, M_WAIT); 477 sc->rxq[i].m = m; 478 if (mtod(m, intptr_t) & 3) { 479 m_adj(m, mtod(m, intptr_t) & 3); 480 } 481 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 482 m->m_ext.ext_buf, MCLBYTES, NULL, 483 BUS_DMA_WAITOK); 484 if (err) { 485 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 486 } 487 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 488 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 489 sc->RDSC[i].Info = 0; 490 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 491 MCLBYTES, BUS_DMASYNC_PREREAD); 492 } 493 494 /* prepare transmit queue */ 495 for (i = 0; i < TX_QLEN; i++) { 496 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 497 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 498 &sc->txq[i].m_dmamap); 499 if (err) 500 panic("ARGH #1"); 501 sc->txq[i].m = NULL; 502 } 503 504 /* Program each queue's start addr, cur addr, and len registers 505 * with the physical addresses. 506 */ 507 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 508 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 509 510 /* Divide HCLK by 32 for MDC clock */ 511 sc->sc_ethercom.ec_mii = mii; 512 mii->mii_ifp = ifp; 513 mii->mii_readreg = cemac_mii_readreg; 514 mii->mii_writereg = cemac_mii_writereg; 515 mii->mii_statchg = cemac_statchg; 516 ifmedia_init(&mii->mii_media, IFM_IMASK, cemac_mediachange, 517 cemac_mediastatus); 518 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1, 0); 519 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 520 521 #if 0 522 // enable / disable interrupts 523 CEMAC_WRITE(ETH_IDR, -1); 524 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 525 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 526 // (void)CEMAC_READ(ETH_ISR); // why 527 528 // enable transmitter / receiver 529 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 530 | ETH_CTL_CSR | ETH_CTL_MPE); 531 #endif 532 /* 533 * We can support hardware checksumming. 534 */ 535 ifp->if_capabilities |= 536 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 537 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 538 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 539 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 540 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 541 542 /* 543 * We can support 802.1Q VLAN-sized frames. 544 */ 545 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 546 547 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 548 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 549 ifp->if_ioctl = cemac_ifioctl; 550 ifp->if_start = cemac_ifstart; 551 ifp->if_watchdog = cemac_ifwatchdog; 552 ifp->if_init = cemac_ifinit; 553 ifp->if_stop = cemac_ifstop; 554 ifp->if_timer = 0; 555 ifp->if_softc = sc; 556 IFQ_SET_READY(&ifp->if_snd); 557 if_attach(ifp); 558 if_deferred_start_init(ifp, NULL); 559 ether_ifattach(ifp, (sc)->sc_enaddr); 560 } 561 562 static int 563 cemac_mediachange(struct ifnet *ifp) 564 { 565 if (ifp->if_flags & IFF_UP) 566 cemac_ifinit(ifp); 567 return 0; 568 } 569 570 static void 571 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 572 { 573 struct cemac_softc * const sc = ifp->if_softc; 574 575 mii_pollstat(&sc->sc_mii); 576 ifmr->ifm_active = sc->sc_mii.mii_media_active; 577 ifmr->ifm_status = sc->sc_mii.mii_media_status; 578 } 579 580 581 static int 582 cemac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 583 { 584 struct cemac_softc * const sc = device_private(self); 585 586 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 587 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 588 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 589 | ETH_MAN_CODE_IEEE802_3)); 590 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 591 ; 592 593 *val = CEMAC_READ(ETH_MAN) & ETH_MAN_DATA; 594 return 0; 595 } 596 597 static int 598 cemac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 599 { 600 struct cemac_softc * const sc = device_private(self); 601 602 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 603 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 604 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 605 | ETH_MAN_CODE_IEEE802_3 606 | (val & ETH_MAN_DATA))); 607 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 608 ; 609 610 return 0; 611 } 612 613 614 static void 615 cemac_statchg(struct ifnet *ifp) 616 { 617 struct cemac_softc * const sc = ifp->if_softc; 618 struct mii_data *mii = &sc->sc_mii; 619 uint32_t reg; 620 621 /* 622 * We must keep the MAC and the PHY in sync as 623 * to the status of full-duplex! 624 */ 625 reg = CEMAC_READ(ETH_CFG); 626 reg &= ~ETH_CFG_FD; 627 if (sc->sc_mii.mii_media_active & IFM_FDX) 628 reg |= ETH_CFG_FD; 629 630 reg &= ~ETH_CFG_SPD; 631 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 632 reg &= ~GEM_CFG_GEN; 633 switch (IFM_SUBTYPE(mii->mii_media_active)) { 634 case IFM_10_T: 635 break; 636 case IFM_100_TX: 637 reg |= ETH_CFG_SPD; 638 break; 639 case IFM_1000_T: 640 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 641 break; 642 default: 643 break; 644 } 645 CEMAC_WRITE(ETH_CFG, reg); 646 } 647 648 static void 649 cemac_tick(void *arg) 650 { 651 struct cemac_softc * const sc = arg; 652 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 653 int s; 654 655 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 656 if_statadd(ifp, if_collisions, 657 CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL)); 658 else 659 if_statadd(ifp, if_collisions, 660 CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL)); 661 662 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 663 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 664 uint32_t misses = CEMAC_READ(ETH_DRFC); 665 if (misses > 0) 666 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 667 } 668 669 s = splnet(); 670 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 671 cemac_ifstart(ifp); 672 splx(s); 673 674 mii_tick(&sc->sc_mii); 675 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 676 } 677 678 679 static int 680 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 681 { 682 int s, error; 683 684 s = splnet(); 685 switch (cmd) { 686 default: 687 error = ether_ioctl(ifp, cmd, data); 688 if (error != ENETRESET) 689 break; 690 error = 0; 691 692 if (cmd == SIOCSIFCAP) { 693 error = if_init(ifp); 694 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 695 ; 696 else if (ifp->if_flags & IFF_RUNNING) { 697 cemac_setaddr(ifp); 698 } 699 } 700 splx(s); 701 return error; 702 } 703 704 static void 705 cemac_ifstart(struct ifnet *ifp) 706 { 707 struct cemac_softc * const sc = ifp->if_softc; 708 struct mbuf *m; 709 bus_dma_segment_t *segs; 710 int s, bi, err, nsegs; 711 712 s = splnet(); 713 start: 714 if (cemac_gctx(sc) == 0) { 715 /* Enable transmit-buffer-free interrupt */ 716 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 717 sc->tx_busy = true; 718 ifp->if_timer = 10; 719 splx(s); 720 return; 721 } 722 723 ifp->if_timer = 0; 724 725 IFQ_POLL(&ifp->if_snd, m); 726 if (m == NULL) { 727 splx(s); 728 return; 729 } 730 731 bi = (sc->txqi + sc->txqc) % TX_QLEN; 732 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 733 BUS_DMA_NOWAIT)) || 734 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 735 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 736 /* Copy entire mbuf chain to new single */ 737 struct mbuf *mn; 738 739 if (err == 0) 740 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 741 742 MGETHDR(mn, M_DONTWAIT, MT_DATA); 743 if (mn == NULL) 744 goto stop; 745 if (m->m_pkthdr.len > MHLEN) { 746 MCLGET(mn, M_DONTWAIT); 747 if ((mn->m_flags & M_EXT) == 0) { 748 m_freem(mn); 749 goto stop; 750 } 751 } 752 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 753 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 754 IFQ_DEQUEUE(&ifp->if_snd, m); 755 m_freem(m); 756 m = mn; 757 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 758 BUS_DMA_NOWAIT); 759 } else { 760 IFQ_DEQUEUE(&ifp->if_snd, m); 761 } 762 763 bpf_mtap(ifp, m, BPF_D_OUT); 764 765 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 766 segs = sc->txq[bi].m_dmamap->dm_segs; 767 if (nsegs > 1) 768 panic("#### ARGH #2"); 769 770 sc->txq[bi].m = m; 771 sc->txqc++; 772 773 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 774 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void *)segs->ds_addr, 775 (unsigned)m->m_pkthdr.len)); 776 #ifdef DIAGNOSTIC 777 if (sc->txqc > TX_QLEN) 778 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 779 #endif 780 781 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 782 sc->txq[bi].m_dmamap->dm_mapsize, 783 BUS_DMASYNC_PREWRITE); 784 785 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 786 sc->TDSC[bi].Addr = segs->ds_addr; 787 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 788 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 789 790 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 791 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 792 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 793 __FUNCTION__, bi, sc->TDSC[bi].Info)); 794 795 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 796 CEMAC_WRITE(ETH_CTL, ctl); 797 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 798 } else { 799 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 800 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 801 } 802 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 803 goto start; 804 stop: 805 806 splx(s); 807 return; 808 } 809 810 static void 811 cemac_ifwatchdog(struct ifnet *ifp) 812 { 813 struct cemac_softc * const sc = ifp->if_softc; 814 815 if ((ifp->if_flags & IFF_RUNNING) == 0) 816 return; 817 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 818 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 819 } 820 821 static int 822 cemac_ifinit(struct ifnet *ifp) 823 { 824 struct cemac_softc * const sc = ifp->if_softc; 825 uint32_t dma, cfg; 826 int s = splnet(); 827 828 callout_stop(&sc->cemac_tick_ch); 829 830 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 831 832 if (ifp->if_capenable & 833 (IFCAP_CSUM_IPv4_Tx | 834 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 835 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 836 dma = CEMAC_READ(GEM_DMA_CFG); 837 dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 838 CEMAC_WRITE(GEM_DMA_CFG, dma); 839 } 840 if (ifp->if_capenable & 841 (IFCAP_CSUM_IPv4_Rx | 842 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 843 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 844 cfg = CEMAC_READ(ETH_CFG); 845 cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN; 846 CEMAC_WRITE(ETH_CFG, cfg); 847 } 848 } 849 850 // enable interrupts 851 CEMAC_WRITE(ETH_IDR, -1); 852 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 853 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 854 855 // enable transmitter / receiver 856 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 857 | ETH_CTL_CSR | ETH_CTL_MPE); 858 859 mii_mediachg(&sc->sc_mii); 860 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 861 ifp->if_flags |= IFF_RUNNING; 862 splx(s); 863 return 0; 864 } 865 866 static void 867 cemac_ifstop(struct ifnet *ifp, int disable) 868 { 869 // uint32_t u; 870 struct cemac_softc * const sc = ifp->if_softc; 871 872 #if 0 873 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 874 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 875 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 876 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 877 CEMAC_WRITE(ETH_CFG, 878 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 879 else 880 CEMAC_WRITE(ETH_CFG, 881 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 882 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 883 // (void)CEMAC_READ(ETH_ISR); 884 u = CEMAC_READ(ETH_TSR); 885 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 886 | ETH_TSR_IDLE | ETH_TSR_RLE 887 | ETH_TSR_COL | ETH_TSR_OVR))); 888 u = CEMAC_READ(ETH_RSR); 889 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 890 #endif 891 callout_stop(&sc->cemac_tick_ch); 892 893 /* Down the MII. */ 894 mii_down(&sc->sc_mii); 895 896 ifp->if_flags &= ~IFF_RUNNING; 897 ifp->if_timer = 0; 898 sc->tx_busy = false; 899 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 900 } 901 902 static void 903 cemac_setaddr(struct ifnet *ifp) 904 { 905 struct cemac_softc * const sc = ifp->if_softc; 906 struct ethercom *ec = &sc->sc_ethercom; 907 struct ether_multi *enm; 908 struct ether_multistep step; 909 uint8_t ias[3][ETHER_ADDR_LEN]; 910 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 911 uint32_t ctl = CEMAC_READ(ETH_CTL); 912 uint32_t cfg = CEMAC_READ(ETH_CFG); 913 914 /* disable receiver temporarily */ 915 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 916 917 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 918 919 if (ifp->if_flags & IFF_PROMISC) { 920 cfg |= ETH_CFG_CAF; 921 } else { 922 cfg &= ~ETH_CFG_CAF; 923 } 924 925 // ETH_CFG_BIG? 926 927 ifp->if_flags &= ~IFF_ALLMULTI; 928 929 ETHER_LOCK(ec); 930 ETHER_FIRST_MULTI(step, ec, enm); 931 while (enm != NULL) { 932 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 933 /* 934 * We must listen to a range of multicast addresses. 935 * For now, just accept all multicasts, rather than 936 * trying to set only those filter bits needed to match 937 * the range. (At this time, the only use of address 938 * ranges is for IP multicast routing, for which the 939 * range is big enough to require all bits set.) 940 */ 941 cfg |= ETH_CFG_MTI; 942 hashes[0] = 0xffffffffUL; 943 hashes[1] = 0xffffffffUL; 944 ifp->if_flags |= IFF_ALLMULTI; 945 nma = 0; 946 break; 947 } 948 949 if (nma < 3) { 950 /* We can program 3 perfect address filters for mcast */ 951 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 952 } else { 953 /* 954 * XXX: Datasheet is not very clear here, I'm not sure 955 * if I'm doing this right. --joff 956 */ 957 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 958 959 /* Just want the 6 most-significant bits. */ 960 h = h >> 26; 961 #if 0 962 hashes[h / 32] |= (1 << (h % 32)); 963 #else 964 hashes[0] = 0xffffffffUL; 965 hashes[1] = 0xffffffffUL; 966 #endif 967 cfg |= ETH_CFG_MTI; 968 } 969 ETHER_NEXT_MULTI(step, enm); 970 nma++; 971 } 972 ETHER_UNLOCK(ec); 973 974 // program... 975 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 976 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 977 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 978 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 979 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 980 | (sc->sc_enaddr[0])); 981 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 982 | (sc->sc_enaddr[4])); 983 if (nma > 0) { 984 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 985 ias[0][0], ias[0][1], ias[0][2], 986 ias[0][3], ias[0][4], ias[0][5])); 987 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 988 | (ias[0][2] << 16) | (ias[0][1] << 8) 989 | (ias[0][0])); 990 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 991 | (ias[0][5])); 992 } 993 if (nma > 1) { 994 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 995 ias[1][0], ias[1][1], ias[1][2], 996 ias[1][3], ias[1][4], ias[1][5])); 997 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 998 | (ias[1][2] << 16) | (ias[1][1] << 8) 999 | (ias[1][0])); 1000 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1001 | (ias[1][5])); 1002 } 1003 if (nma > 2) { 1004 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1005 ias[2][0], ias[2][1], ias[2][2], 1006 ias[2][3], ias[2][4], ias[2][5])); 1007 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1008 | (ias[2][2] << 16) | (ias[2][1] << 8) 1009 | (ias[2][0])); 1010 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1011 | (ias[2][5])); 1012 } 1013 CEMAC_GEM_WRITE(HSH, hashes[0]); 1014 CEMAC_GEM_WRITE(HSL, hashes[1]); 1015 CEMAC_WRITE(ETH_CFG, cfg); 1016 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1017 } 1018
Indexes created Fri Sep 26 20:09:58 GMT 2025