if_cemac.c revision 1.36
1 /* $NetBSD: if_cemac.c,v 1.36 2024/08/25 16:25:29 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.36 2024/08/25 16:25:29 skrll Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/types.h> 47 48 #include <sys/bus.h> 49 #include <sys/device.h> 50 #include <sys/kernel.h> 51 #include <sys/proc.h> 52 #include <sys/systm.h> 53 #include <sys/time.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 #include <net/bpf.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #include <dev/cadence/cemacreg.h> 74 #include <dev/cadence/if_cemacvar.h> 75 76 #define DEFAULT_MDCDIV 32 77 78 #define CEMAC_READ(x) \ 79 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 80 #define CEMAC_WRITE(x, y) \ 81 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 82 #define CEMAC_GEM_WRITE(x, y) \ 83 do { \ 84 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 85 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 86 else \ 87 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 88 } while(0) 89 90 static void cemac_init(struct cemac_softc *); 91 static int cemac_gctx(struct cemac_softc *); 92 static int cemac_mediachange(struct ifnet *); 93 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 94 static int cemac_mii_readreg(device_t, int, int, uint16_t *); 95 static int cemac_mii_writereg(device_t, int, int, uint16_t); 96 static void cemac_statchg(struct ifnet *); 97 static void cemac_tick(void *); 98 static int cemac_ifioctl(struct ifnet *, u_long, void *); 99 static void cemac_ifstart(struct ifnet *); 100 static void cemac_ifwatchdog(struct ifnet *); 101 static int cemac_ifinit(struct ifnet *); 102 static void cemac_ifstop(struct ifnet *, int); 103 static void cemac_setaddr(struct ifnet *); 104 105 #ifdef CEMAC_DEBUG 106 int cemac_debug = CEMAC_DEBUG; 107 #define DPRINTFN(n, fmt) if (cemac_debug >= (n)) printf fmt 108 #else 109 #define DPRINTFN(n, fmt) 110 #endif 111 112 void 113 cemac_attach_common(struct cemac_softc *sc) 114 { 115 uint32_t u; 116 117 aprint_naive("\n"); 118 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 119 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 120 else 121 aprint_normal(": Cadence Ethernet Controller\n"); 122 123 /* configure emac: */ 124 CEMAC_WRITE(ETH_CTL, 0); // disable everything 125 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 126 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 127 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 128 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 129 CEMAC_WRITE(ETH_CFG, 130 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 131 else 132 CEMAC_WRITE(ETH_CFG, 133 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 134 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 135 //(void)CEMAC_READ(ETH_ISR); 136 u = CEMAC_READ(ETH_TSR); 137 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 138 | ETH_TSR_IDLE | ETH_TSR_RLE 139 | ETH_TSR_COL | ETH_TSR_OVR))); 140 u = CEMAC_READ(ETH_RSR); 141 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 142 143 /* Fetch the Ethernet address from property if set. */ 144 prop_dictionary_t prop = device_properties(sc->sc_dev); 145 prop_data_t enaddr = prop_dictionary_get(prop, "mac-address"); 146 147 if (enaddr != NULL) { 148 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 149 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 150 memcpy(sc->sc_enaddr, prop_data_value(enaddr), 151 ETHER_ADDR_LEN); 152 } else { 153 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 154 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 155 }; 156 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 157 } 158 159 cemac_init(sc); 160 } 161 162 static int 163 cemac_gctx(struct cemac_softc *sc) 164 { 165 uint32_t tsr; 166 167 tsr = CEMAC_READ(ETH_TSR); 168 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 169 // no space left 170 if (!(tsr & ETH_TSR_BNQ)) 171 return 0; 172 } else { 173 if (tsr & GEM_TSR_TXGO) 174 return 0; 175 } 176 CEMAC_WRITE(ETH_TSR, tsr); 177 178 // free sent frames 179 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 180 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 181 int bi = sc->txqi % TX_QLEN; 182 183 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 184 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 185 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 186 __FUNCTION__, bi, sc->TDSC[bi].Info)); 187 188 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 189 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 190 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 191 m_freem(sc->txq[bi].m); 192 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 193 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 194 sc->txq[bi].m = NULL; 195 sc->txqi = (bi + 1) % TX_QLEN; 196 sc->txqc--; 197 } 198 199 // mark we're free 200 if (sc->tx_busy) { 201 sc->tx_busy = false; 202 /* Disable transmit-buffer-free interrupt */ 203 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 204 } 205 206 return 1; 207 } 208 209 int 210 cemac_intr(void *arg) 211 { 212 struct cemac_softc * const sc = arg; 213 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 214 uint32_t imr, isr, ctl; 215 #ifdef CEMAC_DEBUG 216 uint32_t rsr; 217 #endif 218 int bi; 219 220 imr = ~CEMAC_READ(ETH_IMR); 221 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE | 222 ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM))) { 223 // interrupt not enabled, can't be us 224 return 0; 225 } 226 227 isr = CEMAC_READ(ETH_ISR); 228 CEMAC_WRITE(ETH_ISR, isr); 229 isr &= imr; 230 #ifdef CEMAC_DEBUG 231 rsr = CEMAC_READ(ETH_RSR); // get receive status register 232 #endif 233 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 234 235 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 236 if (isr & ETH_ISR_RBNA) { // out of receive buffers 237 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 238 ctl = CEMAC_READ(ETH_CTL); // get current control register value 239 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 240 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 241 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 242 if_statinc_ref(ifp, nsr, if_ierrors); 243 if_statinc_ref(ifp, nsr, if_ipackets); 244 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 245 } 246 if (isr & ETH_ISR_ROVR) { 247 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 248 if_statinc_ref(ifp, nsr, if_ierrors); 249 if_statinc_ref(ifp, nsr, if_ipackets); 250 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 251 } 252 253 if (isr & ETH_ISR_RCOM) { // packet has been received! 254 uint32_t nfo; 255 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 256 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 257 int fl, csum; 258 struct mbuf *m; 259 260 nfo = sc->RDSC[bi].Info; 261 fl = (nfo & ETH_RDSC_I_LEN) - 4; 262 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 263 264 MGETHDR(m, M_DONTWAIT, MT_DATA); 265 if (m != NULL) 266 MCLGET(m, M_DONTWAIT); 267 if (m != NULL && (m->m_flags & M_EXT)) { 268 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 269 MCLBYTES, BUS_DMASYNC_POSTREAD); 270 bus_dmamap_unload(sc->sc_dmat, 271 sc->rxq[bi].m_dmamap); 272 m_set_rcvif(sc->rxq[bi].m, ifp); 273 sc->rxq[bi].m->m_pkthdr.len = 274 sc->rxq[bi].m->m_len = fl; 275 switch (nfo & ETH_RDSC_I_CHKSUM) { 276 case ETH_RDSC_I_CHKSUM_IP: 277 csum = M_CSUM_IPv4; 278 break; 279 case ETH_RDSC_I_CHKSUM_UDP: 280 csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 281 M_CSUM_UDPv6; 282 break; 283 case ETH_RDSC_I_CHKSUM_TCP: 284 csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 285 M_CSUM_TCPv6; 286 break; 287 default: 288 csum = 0; 289 break; 290 } 291 sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 292 DPRINTFN(2,("received %u bytes packet\n", fl)); 293 if_percpuq_enqueue(ifp->if_percpuq, 294 sc->rxq[bi].m); 295 if (mtod(m, intptr_t) & 3) 296 m_adj(m, mtod(m, intptr_t) & 3); 297 sc->rxq[bi].m = m; 298 bus_dmamap_load(sc->sc_dmat, 299 sc->rxq[bi].m_dmamap, 300 m->m_ext.ext_buf, MCLBYTES, 301 NULL, BUS_DMA_NOWAIT); 302 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 303 MCLBYTES, BUS_DMASYNC_PREREAD); 304 sc->RDSC[bi].Info = 0; 305 sc->RDSC[bi].Addr = 306 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 307 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 308 } else { 309 /* Drop packets until we can get replacement 310 * empty mbufs for the RXDQ. 311 */ 312 m_freem(m); 313 if_statinc_ref(ifp, nsr, if_ierrors); 314 } 315 sc->rxqi++; 316 } 317 } 318 319 IF_STAT_PUTREF(ifp); 320 321 if (cemac_gctx(sc) > 0) 322 if_schedule_deferred_start(ifp); 323 #if 0 // reloop 324 irq = CEMAC_READ(IntStsC); 325 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 326 goto begin; 327 #endif 328 329 return 1; 330 } 331 332 333 static void 334 cemac_init(struct cemac_softc *sc) 335 { 336 bus_dma_segment_t segs; 337 int rsegs, err, i; 338 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 339 struct mii_data * const mii = &sc->sc_mii; 340 uint32_t u; 341 #if 0 342 int mdcdiv = DEFAULT_MDCDIV; 343 #endif 344 345 callout_init(&sc->cemac_tick_ch, 0); 346 347 // ok... 348 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 349 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 350 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 351 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 352 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 353 CEMAC_WRITE(ETH_CFG, 354 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 355 else 356 CEMAC_WRITE(ETH_CFG, 357 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 358 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 359 CEMAC_WRITE(GEM_DMA_CFG, 360 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 361 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 362 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 363 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 364 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 365 } 366 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 367 // (void)CEMAC_READ(ETH_ISR); 368 u = CEMAC_READ(ETH_TSR); 369 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 370 | ETH_TSR_IDLE | ETH_TSR_RLE 371 | ETH_TSR_COL | ETH_TSR_OVR))); 372 u = CEMAC_READ(ETH_RSR); 373 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 374 375 #if 0 376 if (device_cfdata(sc->sc_dev)->cf_flags) 377 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 378 #endif 379 /* set ethernet address */ 380 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 381 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 382 | (sc->sc_enaddr[0])); 383 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 384 | (sc->sc_enaddr[4])); 385 CEMAC_GEM_WRITE(SA2L, 0); 386 CEMAC_GEM_WRITE(SA2H, 0); 387 CEMAC_GEM_WRITE(SA3L, 0); 388 CEMAC_GEM_WRITE(SA3H, 0); 389 CEMAC_GEM_WRITE(SA4L, 0); 390 CEMAC_GEM_WRITE(SA4H, 0); 391 392 /* Allocate a page of memory for receive queue descriptors */ 393 sc->rbqlen = roundup(ETH_DSC_SIZE * (RX_QLEN + 1) * 2, PAGE_SIZE); 394 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 395 396 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 397 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 398 &segs, 1, &rsegs, BUS_DMA_WAITOK); 399 if (err == 0) { 400 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 401 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 402 &sc->rbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 403 } 404 if (err == 0) { 405 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 406 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 407 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 408 &sc->rbqpage_dmamap); 409 } 410 if (err == 0) { 411 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 412 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 413 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 414 } 415 if (err != 0) 416 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 417 418 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 419 memset(sc->rbqpage, 0, sc->rbqlen); 420 421 /* Allocate a page of memory for transmit queue descriptors */ 422 sc->tbqlen = roundup(ETH_DSC_SIZE * (TX_QLEN + 1) * 2, PAGE_SIZE); 423 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 424 425 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 426 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 427 &segs, 1, &rsegs, BUS_DMA_WAITOK); 428 if (err == 0) { 429 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 430 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 431 &sc->tbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 432 } 433 if (err == 0) { 434 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 435 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 436 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 437 &sc->tbqpage_dmamap); 438 } 439 if (err == 0) { 440 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 441 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 442 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 443 } 444 if (err != 0) 445 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 446 447 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 448 memset(sc->tbqpage, 0, sc->tbqlen); 449 450 /* Set up pointers to start of each queue in kernel addr space. 451 * Each descriptor queue or status queue entry uses 2 words 452 */ 453 sc->RDSC = (void *)sc->rbqpage; 454 sc->TDSC = (void *)sc->tbqpage; 455 456 /* init TX queue */ 457 for (i = 0; i < TX_QLEN; i++) { 458 sc->TDSC[i].Addr = 0; 459 sc->TDSC[i].Info = ETH_TDSC_I_USED | 460 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 461 } 462 463 /* Populate the RXQ with mbufs */ 464 sc->rxqi = 0; 465 for (i = 0; i < RX_QLEN; i++) { 466 struct mbuf *m; 467 468 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 469 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 470 if (err) { 471 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 472 } 473 MGETHDR(m, M_WAIT, MT_DATA); 474 MCLGET(m, M_WAIT); 475 sc->rxq[i].m = m; 476 if (mtod(m, intptr_t) & 3) { 477 m_adj(m, mtod(m, intptr_t) & 3); 478 } 479 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 480 m->m_ext.ext_buf, MCLBYTES, NULL, 481 BUS_DMA_WAITOK); 482 if (err) { 483 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 484 } 485 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 486 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 487 sc->RDSC[i].Info = 0; 488 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 489 MCLBYTES, BUS_DMASYNC_PREREAD); 490 } 491 492 /* prepare transmit queue */ 493 for (i = 0; i < TX_QLEN; i++) { 494 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 495 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 496 &sc->txq[i].m_dmamap); 497 if (err) 498 panic("ARGH #1"); 499 sc->txq[i].m = NULL; 500 } 501 502 /* Program each queue's start addr, cur addr, and len registers 503 * with the physical addresses. 504 */ 505 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 506 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 507 508 /* Divide HCLK by 32 for MDC clock */ 509 sc->sc_ethercom.ec_mii = mii; 510 mii->mii_ifp = ifp; 511 mii->mii_readreg = cemac_mii_readreg; 512 mii->mii_writereg = cemac_mii_writereg; 513 mii->mii_statchg = cemac_statchg; 514 ifmedia_init(&mii->mii_media, IFM_IMASK, cemac_mediachange, 515 cemac_mediastatus); 516 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1, 0); 517 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 518 519 #if 0 520 // enable / disable interrupts 521 CEMAC_WRITE(ETH_IDR, -1); 522 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 523 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 524 // (void)CEMAC_READ(ETH_ISR); // why 525 526 // enable transmitter / receiver 527 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 528 | ETH_CTL_CSR | ETH_CTL_MPE); 529 #endif 530 /* 531 * We can support hardware checksumming. 532 */ 533 ifp->if_capabilities |= 534 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 535 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 536 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 537 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 538 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 539 540 /* 541 * We can support 802.1Q VLAN-sized frames. 542 */ 543 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 544 545 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 546 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 547 ifp->if_ioctl = cemac_ifioctl; 548 ifp->if_start = cemac_ifstart; 549 ifp->if_watchdog = cemac_ifwatchdog; 550 ifp->if_init = cemac_ifinit; 551 ifp->if_stop = cemac_ifstop; 552 ifp->if_timer = 0; 553 ifp->if_softc = sc; 554 IFQ_SET_READY(&ifp->if_snd); 555 if_attach(ifp); 556 if_deferred_start_init(ifp, NULL); 557 ether_ifattach(ifp, (sc)->sc_enaddr); 558 } 559 560 static int 561 cemac_mediachange(struct ifnet *ifp) 562 { 563 if (ifp->if_flags & IFF_UP) 564 cemac_ifinit(ifp); 565 return 0; 566 } 567 568 static void 569 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 570 { 571 struct cemac_softc * const sc = ifp->if_softc; 572 573 mii_pollstat(&sc->sc_mii); 574 ifmr->ifm_active = sc->sc_mii.mii_media_active; 575 ifmr->ifm_status = sc->sc_mii.mii_media_status; 576 } 577 578 579 static int 580 cemac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 581 { 582 struct cemac_softc * const sc = device_private(self); 583 584 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 585 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 586 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 587 | ETH_MAN_CODE_IEEE802_3)); 588 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 589 ; 590 591 *val = CEMAC_READ(ETH_MAN) & ETH_MAN_DATA; 592 return 0; 593 } 594 595 static int 596 cemac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 597 { 598 struct cemac_softc * const sc = device_private(self); 599 600 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 601 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 602 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 603 | ETH_MAN_CODE_IEEE802_3 604 | (val & ETH_MAN_DATA))); 605 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 606 ; 607 608 return 0; 609 } 610 611 612 static void 613 cemac_statchg(struct ifnet *ifp) 614 { 615 struct cemac_softc * const sc = ifp->if_softc; 616 struct mii_data *mii = &sc->sc_mii; 617 uint32_t reg; 618 619 /* 620 * We must keep the MAC and the PHY in sync as 621 * to the status of full-duplex! 622 */ 623 reg = CEMAC_READ(ETH_CFG); 624 reg &= ~ETH_CFG_FD; 625 if (sc->sc_mii.mii_media_active & IFM_FDX) 626 reg |= ETH_CFG_FD; 627 628 reg &= ~ETH_CFG_SPD; 629 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 630 reg &= ~GEM_CFG_GEN; 631 switch (IFM_SUBTYPE(mii->mii_media_active)) { 632 case IFM_10_T: 633 break; 634 case IFM_100_TX: 635 reg |= ETH_CFG_SPD; 636 break; 637 case IFM_1000_T: 638 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 639 break; 640 default: 641 break; 642 } 643 CEMAC_WRITE(ETH_CFG, reg); 644 } 645 646 static void 647 cemac_tick(void *arg) 648 { 649 struct cemac_softc * const sc = arg; 650 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 651 int s; 652 653 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 654 if_statadd(ifp, if_collisions, 655 CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL)); 656 else 657 if_statadd(ifp, if_collisions, 658 CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL)); 659 660 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 661 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 662 uint32_t misses = CEMAC_READ(ETH_DRFC); 663 if (misses > 0) 664 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 665 } 666 667 s = splnet(); 668 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 669 cemac_ifstart(ifp); 670 splx(s); 671 672 mii_tick(&sc->sc_mii); 673 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 674 } 675 676 677 static int 678 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 679 { 680 int s, error; 681 682 s = splnet(); 683 switch (cmd) { 684 default: 685 error = ether_ioctl(ifp, cmd, data); 686 if (error != ENETRESET) 687 break; 688 error = 0; 689 690 if (cmd == SIOCSIFCAP) { 691 error = if_init(ifp); 692 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 693 ; 694 else if (ifp->if_flags & IFF_RUNNING) { 695 cemac_setaddr(ifp); 696 } 697 } 698 splx(s); 699 return error; 700 } 701 702 static void 703 cemac_ifstart(struct ifnet *ifp) 704 { 705 struct cemac_softc * const sc = ifp->if_softc; 706 struct mbuf *m; 707 bus_dma_segment_t *segs; 708 int s, bi, err, nsegs; 709 710 s = splnet(); 711 start: 712 if (cemac_gctx(sc) == 0) { 713 /* Enable transmit-buffer-free interrupt */ 714 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 715 sc->tx_busy = true; 716 ifp->if_timer = 10; 717 splx(s); 718 return; 719 } 720 721 ifp->if_timer = 0; 722 723 IFQ_POLL(&ifp->if_snd, m); 724 if (m == NULL) { 725 splx(s); 726 return; 727 } 728 729 bi = (sc->txqi + sc->txqc) % TX_QLEN; 730 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 731 BUS_DMA_NOWAIT)) || 732 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 733 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 734 /* Copy entire mbuf chain to new single */ 735 struct mbuf *mn; 736 737 if (err == 0) 738 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 739 740 MGETHDR(mn, M_DONTWAIT, MT_DATA); 741 if (mn == NULL) 742 goto stop; 743 if (m->m_pkthdr.len > MHLEN) { 744 MCLGET(mn, M_DONTWAIT); 745 if ((mn->m_flags & M_EXT) == 0) { 746 m_freem(mn); 747 goto stop; 748 } 749 } 750 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 751 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 752 IFQ_DEQUEUE(&ifp->if_snd, m); 753 m_freem(m); 754 m = mn; 755 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 756 BUS_DMA_NOWAIT); 757 } else { 758 IFQ_DEQUEUE(&ifp->if_snd, m); 759 } 760 761 bpf_mtap(ifp, m, BPF_D_OUT); 762 763 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 764 segs = sc->txq[bi].m_dmamap->dm_segs; 765 if (nsegs > 1) 766 panic("#### ARGH #2"); 767 768 sc->txq[bi].m = m; 769 sc->txqc++; 770 771 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 772 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void *)segs->ds_addr, 773 (unsigned)m->m_pkthdr.len)); 774 #ifdef DIAGNOSTIC 775 if (sc->txqc > TX_QLEN) 776 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 777 #endif 778 779 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 780 sc->txq[bi].m_dmamap->dm_mapsize, 781 BUS_DMASYNC_PREWRITE); 782 783 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 784 sc->TDSC[bi].Addr = segs->ds_addr; 785 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 786 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 787 788 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 789 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 790 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 791 __FUNCTION__, bi, sc->TDSC[bi].Info)); 792 793 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 794 CEMAC_WRITE(ETH_CTL, ctl); 795 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 796 } else { 797 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 798 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 799 } 800 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 801 goto start; 802 stop: 803 804 splx(s); 805 return; 806 } 807 808 static void 809 cemac_ifwatchdog(struct ifnet *ifp) 810 { 811 struct cemac_softc * const sc = ifp->if_softc; 812 813 if ((ifp->if_flags & IFF_RUNNING) == 0) 814 return; 815 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 816 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 817 } 818 819 static int 820 cemac_ifinit(struct ifnet *ifp) 821 { 822 struct cemac_softc * const sc = ifp->if_softc; 823 uint32_t dma, cfg; 824 int s = splnet(); 825 826 callout_stop(&sc->cemac_tick_ch); 827 828 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 829 830 if (ifp->if_capenable & 831 (IFCAP_CSUM_IPv4_Tx | 832 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 833 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 834 dma = CEMAC_READ(GEM_DMA_CFG); 835 dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 836 CEMAC_WRITE(GEM_DMA_CFG, dma); 837 } 838 if (ifp->if_capenable & 839 (IFCAP_CSUM_IPv4_Rx | 840 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 841 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 842 cfg = CEMAC_READ(ETH_CFG); 843 cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN; 844 CEMAC_WRITE(ETH_CFG, cfg); 845 } 846 } 847 848 // enable interrupts 849 CEMAC_WRITE(ETH_IDR, -1); 850 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 851 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 852 853 // enable transmitter / receiver 854 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 855 | ETH_CTL_CSR | ETH_CTL_MPE); 856 857 mii_mediachg(&sc->sc_mii); 858 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 859 ifp->if_flags |= IFF_RUNNING; 860 splx(s); 861 return 0; 862 } 863 864 static void 865 cemac_ifstop(struct ifnet *ifp, int disable) 866 { 867 // uint32_t u; 868 struct cemac_softc * const sc = ifp->if_softc; 869 870 #if 0 871 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 872 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 873 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 874 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 875 CEMAC_WRITE(ETH_CFG, 876 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 877 else 878 CEMAC_WRITE(ETH_CFG, 879 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 880 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 881 // (void)CEMAC_READ(ETH_ISR); 882 u = CEMAC_READ(ETH_TSR); 883 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 884 | ETH_TSR_IDLE | ETH_TSR_RLE 885 | ETH_TSR_COL | ETH_TSR_OVR))); 886 u = CEMAC_READ(ETH_RSR); 887 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 888 #endif 889 callout_stop(&sc->cemac_tick_ch); 890 891 /* Down the MII. */ 892 mii_down(&sc->sc_mii); 893 894 ifp->if_flags &= ~IFF_RUNNING; 895 ifp->if_timer = 0; 896 sc->tx_busy = false; 897 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 898 } 899 900 static void 901 cemac_setaddr(struct ifnet *ifp) 902 { 903 struct cemac_softc * const sc = ifp->if_softc; 904 struct ethercom *ec = &sc->sc_ethercom; 905 struct ether_multi *enm; 906 struct ether_multistep step; 907 uint8_t ias[3][ETHER_ADDR_LEN]; 908 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 909 uint32_t ctl = CEMAC_READ(ETH_CTL); 910 uint32_t cfg = CEMAC_READ(ETH_CFG); 911 912 /* disable receiver temporarily */ 913 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 914 915 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 916 917 if (ifp->if_flags & IFF_PROMISC) { 918 cfg |= ETH_CFG_CAF; 919 } else { 920 cfg &= ~ETH_CFG_CAF; 921 } 922 923 // ETH_CFG_BIG? 924 925 ifp->if_flags &= ~IFF_ALLMULTI; 926 927 ETHER_LOCK(ec); 928 ETHER_FIRST_MULTI(step, ec, enm); 929 while (enm != NULL) { 930 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 931 /* 932 * We must listen to a range of multicast addresses. 933 * For now, just accept all multicasts, rather than 934 * trying to set only those filter bits needed to match 935 * the range. (At this time, the only use of address 936 * ranges is for IP multicast routing, for which the 937 * range is big enough to require all bits set.) 938 */ 939 cfg |= ETH_CFG_MTI; 940 hashes[0] = 0xffffffffUL; 941 hashes[1] = 0xffffffffUL; 942 ifp->if_flags |= IFF_ALLMULTI; 943 nma = 0; 944 break; 945 } 946 947 if (nma < 3) { 948 /* We can program 3 perfect address filters for mcast */ 949 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 950 } else { 951 /* 952 * XXX: Datasheet is not very clear here, I'm not sure 953 * if I'm doing this right. --joff 954 */ 955 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 956 957 /* Just want the 6 most-significant bits. */ 958 h = h >> 26; 959 #if 0 960 hashes[h / 32] |= (1 << (h % 32)); 961 #else 962 hashes[0] = 0xffffffffUL; 963 hashes[1] = 0xffffffffUL; 964 #endif 965 cfg |= ETH_CFG_MTI; 966 } 967 ETHER_NEXT_MULTI(step, enm); 968 nma++; 969 } 970 ETHER_UNLOCK(ec); 971 972 // program... 973 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 974 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 975 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 976 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 977 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 978 | (sc->sc_enaddr[0])); 979 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 980 | (sc->sc_enaddr[4])); 981 if (nma > 0) { 982 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 983 ias[0][0], ias[0][1], ias[0][2], 984 ias[0][3], ias[0][4], ias[0][5])); 985 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 986 | (ias[0][2] << 16) | (ias[0][1] << 8) 987 | (ias[0][0])); 988 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 989 | (ias[0][5])); 990 } 991 if (nma > 1) { 992 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 993 ias[1][0], ias[1][1], ias[1][2], 994 ias[1][3], ias[1][4], ias[1][5])); 995 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 996 | (ias[1][2] << 16) | (ias[1][1] << 8) 997 | (ias[1][0])); 998 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 999 | (ias[1][5])); 1000 } 1001 if (nma > 2) { 1002 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1003 ias[2][0], ias[2][1], ias[2][2], 1004 ias[2][3], ias[2][4], ias[2][5])); 1005 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1006 | (ias[2][2] << 16) | (ias[2][1] << 8) 1007 | (ias[2][0])); 1008 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1009 | (ias[2][5])); 1010 } 1011 CEMAC_GEM_WRITE(HSH, hashes[0]); 1012 CEMAC_GEM_WRITE(HSL, hashes[1]); 1013 CEMAC_WRITE(ETH_CFG, cfg); 1014 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1015 } 1016
Indexes created Thu Sep 25 16:09:42 GMT 2025