if_cemac.c revision 1.41
1 /* $NetBSD: if_cemac.c,v 1.41 2024/09/29 08:55:21 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.41 2024/09/29 08:55:21 skrll Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/types.h> 47 48 #include <sys/bus.h> 49 #include <sys/device.h> 50 #include <sys/kernel.h> 51 #include <sys/proc.h> 52 #include <sys/systm.h> 53 #include <sys/time.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 #include <net/bpf.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 73 #include <dev/cadence/cemacreg.h> 74 #include <dev/cadence/if_cemacvar.h> 75 76 #define DEFAULT_MDCDIV 32 77 78 #define CEMAC_READ(x) \ 79 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 80 #define CEMAC_WRITE(x, y) \ 81 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 82 #define CEMAC_GEM_WRITE(x, y) \ 83 do { \ 84 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 85 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 86 else \ 87 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 88 } while(0) 89 90 static void cemac_init(struct cemac_softc *); 91 static int cemac_gctx(struct cemac_softc *); 92 static int cemac_mediachange(struct ifnet *); 93 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 94 static int cemac_mii_readreg(device_t, int, int, uint16_t *); 95 static int cemac_mii_writereg(device_t, int, int, uint16_t); 96 static void cemac_statchg(struct ifnet *); 97 static void cemac_tick(void *); 98 static int cemac_ifioctl(struct ifnet *, u_long, void *); 99 static void cemac_ifstart(struct ifnet *); 100 static void cemac_ifwatchdog(struct ifnet *); 101 static int cemac_ifinit(struct ifnet *); 102 static void cemac_ifstop(struct ifnet *, int); 103 static void cemac_setaddr(struct ifnet *); 104 105 #ifdef CEMAC_DEBUG 106 int cemac_debug = CEMAC_DEBUG; 107 #define DPRINTFN(n, fmt) if (cemac_debug >= (n)) printf fmt 108 #else 109 #define DPRINTFN(n, fmt) 110 #endif 111 112 void 113 cemac_attach_common(struct cemac_softc *sc) 114 { 115 uint32_t u; 116 117 aprint_naive("\n"); 118 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 119 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 120 else 121 aprint_normal(": Cadence Ethernet Controller\n"); 122 123 /* configure emac: */ 124 CEMAC_WRITE(ETH_CTL, 0); // disable everything 125 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 126 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 127 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 128 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 129 CEMAC_WRITE(ETH_CFG, 130 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 131 else 132 CEMAC_WRITE(ETH_CFG, 133 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 134 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 135 //(void)CEMAC_READ(ETH_ISR); 136 u = CEMAC_READ(ETH_TSR); 137 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 138 | ETH_TSR_IDLE | ETH_TSR_RLE 139 | ETH_TSR_COL | ETH_TSR_OVR))); 140 u = CEMAC_READ(ETH_RSR); 141 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 142 143 /* Fetch the Ethernet address from property if set. */ 144 prop_dictionary_t prop = device_properties(sc->sc_dev); 145 prop_data_t enaddr = prop_dictionary_get(prop, "mac-address"); 146 147 if (enaddr != NULL) { 148 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 149 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 150 memcpy(sc->sc_enaddr, prop_data_value(enaddr), 151 ETHER_ADDR_LEN); 152 } else { 153 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 154 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 155 }; 156 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 157 } 158 159 cemac_init(sc); 160 } 161 162 static int 163 cemac_gctx(struct cemac_softc *sc) 164 { 165 uint32_t tsr; 166 167 tsr = CEMAC_READ(ETH_TSR); 168 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 169 // no space left 170 if (!(tsr & ETH_TSR_BNQ)) 171 return 0; 172 } else { 173 if (tsr & GEM_TSR_TXGO) 174 return 0; 175 } 176 CEMAC_WRITE(ETH_TSR, tsr); 177 178 // free sent frames 179 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 180 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 181 int bi = sc->txqi % TX_QLEN; 182 183 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 184 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 185 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 186 __FUNCTION__, bi, sc->TDSC[bi].Info)); 187 188 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 189 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 190 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 191 m_freem(sc->txq[bi].m); 192 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 193 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 194 sc->txq[bi].m = NULL; 195 sc->txqi = (bi + 1) % TX_QLEN; 196 sc->txqc--; 197 } 198 199 // mark we're free 200 if (sc->tx_busy) { 201 sc->tx_busy = false; 202 /* Disable transmit-buffer-free interrupt */ 203 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 204 } 205 206 return 1; 207 } 208 209 int 210 cemac_intr(void *arg) 211 { 212 struct cemac_softc * const sc = arg; 213 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 214 uint32_t imr, isr, ctl; 215 #ifdef CEMAC_DEBUG 216 uint32_t rsr; 217 #endif 218 int bi; 219 220 imr = ~CEMAC_READ(ETH_IMR); 221 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE | 222 ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM))) { 223 // interrupt not enabled, can't be us 224 return 0; 225 } 226 227 isr = CEMAC_READ(ETH_ISR); 228 CEMAC_WRITE(ETH_ISR, isr); 229 isr &= imr; 230 #ifdef CEMAC_DEBUG 231 rsr = CEMAC_READ(ETH_RSR); // get receive status register 232 #endif 233 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, 234 isr, rsr, imr)); 235 236 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 237 // out of receive buffers 238 if (isr & ETH_ISR_RBNA) { 239 // clear interrupt 240 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); 241 242 ctl = CEMAC_READ(ETH_CTL); 243 // disable receiver 244 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 245 // clear BNA bit 246 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); 247 // re-enable receiver 248 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 249 250 if_statinc_ref(ifp, nsr, if_ierrors); 251 if_statinc_ref(ifp, nsr, if_ipackets); 252 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 253 } 254 if (isr & ETH_ISR_ROVR) { 255 // clear interrupt 256 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); 257 if_statinc_ref(ifp, nsr, if_ierrors); 258 if_statinc_ref(ifp, nsr, if_ipackets); 259 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 260 } 261 262 // packet has been received! 263 if (isr & ETH_ISR_RCOM) { 264 uint32_t nfo; 265 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, 266 sc->RDSC[sc->rxqi % RX_QLEN].Info)); 267 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 268 int fl, csum; 269 struct mbuf *m; 270 271 nfo = sc->RDSC[bi].Info; 272 fl = (nfo & ETH_RDSC_I_LEN) - 4; 273 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 274 275 MGETHDR(m, M_DONTWAIT, MT_DATA); 276 if (m != NULL) 277 MCLGET(m, M_DONTWAIT); 278 if (m != NULL && (m->m_flags & M_EXT)) { 279 bus_dmamap_sync(sc->sc_dmat, 280 sc->rxq[bi].m_dmamap, 0, MCLBYTES, 281 BUS_DMASYNC_POSTREAD); 282 bus_dmamap_unload(sc->sc_dmat, 283 sc->rxq[bi].m_dmamap); 284 m_set_rcvif(sc->rxq[bi].m, ifp); 285 sc->rxq[bi].m->m_pkthdr.len = 286 sc->rxq[bi].m->m_len = fl; 287 switch (nfo & ETH_RDSC_I_CHKSUM) { 288 case ETH_RDSC_I_CHKSUM_IP: 289 csum = M_CSUM_IPv4; 290 break; 291 case ETH_RDSC_I_CHKSUM_UDP: 292 csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 293 M_CSUM_UDPv6; 294 break; 295 case ETH_RDSC_I_CHKSUM_TCP: 296 csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 297 M_CSUM_TCPv6; 298 break; 299 default: 300 csum = 0; 301 break; 302 } 303 sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 304 DPRINTFN(2,("received %u bytes packet\n", fl)); 305 if_percpuq_enqueue(ifp->if_percpuq, 306 sc->rxq[bi].m); 307 if (mtod(m, intptr_t) & 3) 308 m_adj(m, mtod(m, intptr_t) & 3); 309 sc->rxq[bi].m = m; 310 bus_dmamap_load(sc->sc_dmat, 311 sc->rxq[bi].m_dmamap, m->m_ext.ext_buf, 312 MCLBYTES, NULL, BUS_DMA_NOWAIT); 313 bus_dmamap_sync(sc->sc_dmat, 314 sc->rxq[bi].m_dmamap, 0, MCLBYTES, 315 BUS_DMASYNC_PREREAD); 316 sc->RDSC[bi].Info = 0; 317 sc->RDSC[bi].Addr = 318 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 319 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 320 } else { 321 /* Drop packets until we can get replacement 322 * empty mbufs for the RXDQ. 323 */ 324 m_freem(m); 325 if_statinc_ref(ifp, nsr, if_ierrors); 326 } 327 sc->rxqi++; 328 } 329 } 330 331 IF_STAT_PUTREF(ifp); 332 333 if (cemac_gctx(sc) > 0) 334 if_schedule_deferred_start(ifp); 335 #if 0 // reloop 336 irq = CEMAC_READ(IntStsC); 337 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 338 goto begin; 339 #endif 340 341 return 1; 342 } 343 344 345 static void 346 cemac_init(struct cemac_softc *sc) 347 { 348 bus_dma_segment_t segs; 349 int rsegs, err, i; 350 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 351 struct mii_data * const mii = &sc->sc_mii; 352 uint32_t u; 353 #if 0 354 int mdcdiv = DEFAULT_MDCDIV; 355 #endif 356 357 callout_init(&sc->cemac_tick_ch, 0); 358 359 // ok... 360 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 361 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 362 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 363 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 364 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 365 CEMAC_WRITE(ETH_CFG, 366 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 367 else 368 CEMAC_WRITE(ETH_CFG, 369 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 370 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 371 CEMAC_WRITE(GEM_DMA_CFG, 372 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 373 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 374 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 375 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 376 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 377 } 378 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 379 // (void)CEMAC_READ(ETH_ISR); 380 u = CEMAC_READ(ETH_TSR); 381 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 382 | ETH_TSR_IDLE | ETH_TSR_RLE 383 | ETH_TSR_COL | ETH_TSR_OVR))); 384 u = CEMAC_READ(ETH_RSR); 385 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 386 387 #if 0 388 if (device_cfdata(sc->sc_dev)->cf_flags) 389 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 390 #endif 391 /* set ethernet address */ 392 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 393 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 394 | (sc->sc_enaddr[0])); 395 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 396 | (sc->sc_enaddr[4])); 397 CEMAC_GEM_WRITE(SA2L, 0); 398 CEMAC_GEM_WRITE(SA2H, 0); 399 CEMAC_GEM_WRITE(SA3L, 0); 400 CEMAC_GEM_WRITE(SA3H, 0); 401 CEMAC_GEM_WRITE(SA4L, 0); 402 CEMAC_GEM_WRITE(SA4H, 0); 403 404 /* Allocate memory for receive queue descriptors */ 405 sc->rbqlen = roundup(ETH_DSC_SIZE * (RX_QLEN + 1) * 2, PAGE_SIZE); 406 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 407 408 // see EMAC errata why forced to 16384 byte boundary 409 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 410 MAX(16384, PAGE_SIZE), &segs, 1, &rsegs, BUS_DMA_WAITOK); 411 if (err == 0) { 412 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 413 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 414 &sc->rbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 415 } 416 if (err == 0) { 417 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 418 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 419 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 420 &sc->rbqpage_dmamap); 421 } 422 if (err == 0) { 423 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 424 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 425 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 426 } 427 if (err != 0) 428 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 429 430 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 431 memset(sc->rbqpage, 0, sc->rbqlen); 432 433 /* Allocate memory for transmit queue descriptors */ 434 sc->tbqlen = roundup(ETH_DSC_SIZE * (TX_QLEN + 1) * 2, PAGE_SIZE); 435 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 436 437 // see EMAC errata why forced to 16384 byte boundary 438 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 439 MAX(16384, PAGE_SIZE), &segs, 1, &rsegs, BUS_DMA_WAITOK); 440 if (err == 0) { 441 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 442 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 443 &sc->tbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 444 } 445 if (err == 0) { 446 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 447 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 448 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 449 &sc->tbqpage_dmamap); 450 } 451 if (err == 0) { 452 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 453 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 454 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 455 } 456 if (err != 0) 457 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 458 459 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 460 memset(sc->tbqpage, 0, sc->tbqlen); 461 462 /* Set up pointers to start of each queue in kernel addr space. 463 * Each descriptor queue or status queue entry uses 2 words 464 */ 465 sc->RDSC = (void *)sc->rbqpage; 466 sc->TDSC = (void *)sc->tbqpage; 467 468 /* init TX queue */ 469 for (i = 0; i < TX_QLEN; i++) { 470 sc->TDSC[i].Addr = 0; 471 sc->TDSC[i].Info = ETH_TDSC_I_USED | 472 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 473 } 474 475 /* Populate the RXQ with mbufs */ 476 sc->rxqi = 0; 477 for (i = 0; i < RX_QLEN; i++) { 478 struct mbuf *m; 479 480 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 481 PAGE_SIZE, BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 482 if (err) { 483 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, 484 err); 485 } 486 MGETHDR(m, M_WAIT, MT_DATA); 487 MCLGET(m, M_WAIT); 488 sc->rxq[i].m = m; 489 if (mtod(m, intptr_t) & 3) { 490 m_adj(m, mtod(m, intptr_t) & 3); 491 } 492 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 493 m->m_ext.ext_buf, MCLBYTES, NULL, 494 BUS_DMA_WAITOK); 495 if (err) { 496 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 497 } 498 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 499 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 500 sc->RDSC[i].Info = 0; 501 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 502 MCLBYTES, BUS_DMASYNC_PREREAD); 503 } 504 505 /* prepare transmit queue */ 506 for (i = 0; i < TX_QLEN; i++) { 507 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 508 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 509 &sc->txq[i].m_dmamap); 510 if (err) 511 panic("ARGH #1"); 512 sc->txq[i].m = NULL; 513 } 514 515 /* Program each queue's start addr, cur addr, and len registers 516 * with the physical addresses. 517 */ 518 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 519 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 520 521 /* Divide HCLK by 32 for MDC clock */ 522 sc->sc_ethercom.ec_mii = mii; 523 mii->mii_ifp = ifp; 524 mii->mii_readreg = cemac_mii_readreg; 525 mii->mii_writereg = cemac_mii_writereg; 526 mii->mii_statchg = cemac_statchg; 527 ifmedia_init(&mii->mii_media, IFM_IMASK, cemac_mediachange, 528 cemac_mediastatus); 529 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1, 0); 530 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 531 532 #if 0 533 // enable / disable interrupts 534 CEMAC_WRITE(ETH_IDR, -1); 535 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 536 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 537 // (void)CEMAC_READ(ETH_ISR); // why 538 539 // enable transmitter / receiver 540 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 541 | ETH_CTL_CSR | ETH_CTL_MPE); 542 #endif 543 /* 544 * We can support hardware checksumming. 545 */ 546 ifp->if_capabilities |= 547 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 548 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 549 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 550 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 551 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 552 553 /* 554 * We can support 802.1Q VLAN-sized frames. 555 */ 556 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 557 558 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 559 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 560 ifp->if_ioctl = cemac_ifioctl; 561 ifp->if_start = cemac_ifstart; 562 ifp->if_watchdog = cemac_ifwatchdog; 563 ifp->if_init = cemac_ifinit; 564 ifp->if_stop = cemac_ifstop; 565 ifp->if_timer = 0; 566 ifp->if_softc = sc; 567 IFQ_SET_READY(&ifp->if_snd); 568 if_attach(ifp); 569 if_deferred_start_init(ifp, NULL); 570 ether_ifattach(ifp, (sc)->sc_enaddr); 571 } 572 573 static int 574 cemac_mediachange(struct ifnet *ifp) 575 { 576 if (ifp->if_flags & IFF_UP) 577 cemac_ifinit(ifp); 578 return 0; 579 } 580 581 static void 582 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 583 { 584 struct cemac_softc * const sc = ifp->if_softc; 585 586 mii_pollstat(&sc->sc_mii); 587 ifmr->ifm_active = sc->sc_mii.mii_media_active; 588 ifmr->ifm_status = sc->sc_mii.mii_media_status; 589 } 590 591 592 static int 593 cemac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 594 { 595 struct cemac_softc * const sc = device_private(self); 596 597 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 598 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 599 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 600 | ETH_MAN_CODE_IEEE802_3)); 601 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 602 ; 603 604 *val = CEMAC_READ(ETH_MAN) & ETH_MAN_DATA; 605 return 0; 606 } 607 608 static int 609 cemac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 610 { 611 struct cemac_softc * const sc = device_private(self); 612 613 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 614 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 615 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 616 | ETH_MAN_CODE_IEEE802_3 617 | (val & ETH_MAN_DATA))); 618 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) 619 ; 620 621 return 0; 622 } 623 624 625 static void 626 cemac_statchg(struct ifnet *ifp) 627 { 628 struct cemac_softc * const sc = ifp->if_softc; 629 struct mii_data *mii = &sc->sc_mii; 630 uint32_t reg; 631 632 /* 633 * We must keep the MAC and the PHY in sync as 634 * to the status of full-duplex! 635 */ 636 reg = CEMAC_READ(ETH_CFG); 637 reg &= ~ETH_CFG_FD; 638 if (sc->sc_mii.mii_media_active & IFM_FDX) 639 reg |= ETH_CFG_FD; 640 641 reg &= ~ETH_CFG_SPD; 642 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 643 reg &= ~GEM_CFG_GEN; 644 switch (IFM_SUBTYPE(mii->mii_media_active)) { 645 case IFM_10_T: 646 break; 647 case IFM_100_TX: 648 reg |= ETH_CFG_SPD; 649 break; 650 case IFM_1000_T: 651 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 652 break; 653 default: 654 break; 655 } 656 CEMAC_WRITE(ETH_CFG, reg); 657 } 658 659 static void 660 cemac_tick(void *arg) 661 { 662 struct cemac_softc * const sc = arg; 663 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 664 int s; 665 666 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 667 if_statadd(ifp, if_collisions, 668 CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL)); 669 else 670 if_statadd(ifp, if_collisions, 671 CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL)); 672 673 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 674 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 675 uint32_t misses = CEMAC_READ(ETH_DRFC); 676 if (misses > 0) 677 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 678 } 679 680 s = splnet(); 681 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 682 cemac_ifstart(ifp); 683 splx(s); 684 685 mii_tick(&sc->sc_mii); 686 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 687 } 688 689 690 static int 691 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 692 { 693 int s, error; 694 695 s = splnet(); 696 switch (cmd) { 697 default: 698 error = ether_ioctl(ifp, cmd, data); 699 if (error != ENETRESET) 700 break; 701 error = 0; 702 703 if (cmd == SIOCSIFCAP) { 704 error = if_init(ifp); 705 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 706 ; 707 else if (ifp->if_flags & IFF_RUNNING) { 708 cemac_setaddr(ifp); 709 } 710 } 711 splx(s); 712 return error; 713 } 714 715 static void 716 cemac_ifstart(struct ifnet *ifp) 717 { 718 struct cemac_softc * const sc = ifp->if_softc; 719 struct mbuf *m; 720 bus_dma_segment_t *segs; 721 int s, bi, err, nsegs; 722 723 s = splnet(); 724 start: 725 if (cemac_gctx(sc) == 0) { 726 /* Enable transmit-buffer-free interrupt */ 727 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 728 sc->tx_busy = true; 729 ifp->if_timer = 10; 730 splx(s); 731 return; 732 } 733 734 ifp->if_timer = 0; 735 736 IFQ_POLL(&ifp->if_snd, m); 737 if (m == NULL) { 738 splx(s); 739 return; 740 } 741 742 bi = (sc->txqi + sc->txqc) % TX_QLEN; 743 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 744 BUS_DMA_NOWAIT)) || 745 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 746 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 747 /* Copy entire mbuf chain to new single */ 748 struct mbuf *mn; 749 750 if (err == 0) 751 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 752 753 MGETHDR(mn, M_DONTWAIT, MT_DATA); 754 if (mn == NULL) 755 goto stop; 756 if (m->m_pkthdr.len > MHLEN) { 757 MCLGET(mn, M_DONTWAIT); 758 if ((mn->m_flags & M_EXT) == 0) { 759 m_freem(mn); 760 goto stop; 761 } 762 } 763 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 764 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 765 IFQ_DEQUEUE(&ifp->if_snd, m); 766 m_freem(m); 767 m = mn; 768 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 769 BUS_DMA_NOWAIT); 770 } else { 771 IFQ_DEQUEUE(&ifp->if_snd, m); 772 } 773 774 bpf_mtap(ifp, m, BPF_D_OUT); 775 776 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 777 segs = sc->txq[bi].m_dmamap->dm_segs; 778 if (nsegs > 1) 779 panic("#### ARGH #2"); 780 781 sc->txq[bi].m = m; 782 sc->txqc++; 783 784 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), " 785 "len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, 786 (void *)segs->ds_addr, (unsigned)m->m_pkthdr.len)); 787 #ifdef DIAGNOSTIC 788 if (sc->txqc > TX_QLEN) 789 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 790 #endif 791 792 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 793 sc->txq[bi].m_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 794 795 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 796 sc->TDSC[bi].Addr = segs->ds_addr; 797 sc->TDSC[bi].Info = 798 __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 799 ETH_TDSC_I_LAST_BUF | 800 (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 801 802 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 803 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 804 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 805 __FUNCTION__, bi, sc->TDSC[bi].Info)); 806 807 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 808 CEMAC_WRITE(ETH_CTL, ctl); 809 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, 810 CEMAC_READ(ETH_CTL))); 811 } else { 812 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 813 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 814 } 815 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 816 goto start; 817 stop: 818 819 splx(s); 820 return; 821 } 822 823 static void 824 cemac_ifwatchdog(struct ifnet *ifp) 825 { 826 struct cemac_softc * const sc = ifp->if_softc; 827 828 if ((ifp->if_flags & IFF_RUNNING) == 0) 829 return; 830 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 831 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 832 } 833 834 static int 835 cemac_ifinit(struct ifnet *ifp) 836 { 837 struct cemac_softc * const sc = ifp->if_softc; 838 uint32_t dma, cfg; 839 int s = splnet(); 840 841 callout_stop(&sc->cemac_tick_ch); 842 843 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 844 845 if (ifp->if_capenable & 846 (IFCAP_CSUM_IPv4_Tx | 847 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 848 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 849 dma = CEMAC_READ(GEM_DMA_CFG); 850 dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 851 CEMAC_WRITE(GEM_DMA_CFG, dma); 852 } 853 if (ifp->if_capenable & 854 (IFCAP_CSUM_IPv4_Rx | 855 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 856 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 857 cfg = CEMAC_READ(ETH_CFG); 858 cfg |= GEM_CFG_RXCOEN; 859 CEMAC_WRITE(ETH_CFG, cfg); 860 } 861 } 862 863 // enable interrupts 864 CEMAC_WRITE(ETH_IDR, -1); 865 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 866 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 867 868 // enable transmitter / receiver 869 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 870 | ETH_CTL_CSR | ETH_CTL_MPE); 871 872 mii_mediachg(&sc->sc_mii); 873 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 874 ifp->if_flags |= IFF_RUNNING; 875 splx(s); 876 return 0; 877 } 878 879 static void 880 cemac_ifstop(struct ifnet *ifp, int disable) 881 { 882 // uint32_t u; 883 struct cemac_softc * const sc = ifp->if_softc; 884 885 #if 0 886 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 887 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 888 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 889 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 890 CEMAC_WRITE(ETH_CFG, 891 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 892 else 893 CEMAC_WRITE(ETH_CFG, 894 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 895 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 896 // (void)CEMAC_READ(ETH_ISR); 897 u = CEMAC_READ(ETH_TSR); 898 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 899 | ETH_TSR_IDLE | ETH_TSR_RLE 900 | ETH_TSR_COL | ETH_TSR_OVR))); 901 u = CEMAC_READ(ETH_RSR); 902 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 903 #endif 904 callout_stop(&sc->cemac_tick_ch); 905 906 /* Down the MII. */ 907 mii_down(&sc->sc_mii); 908 909 ifp->if_flags &= ~IFF_RUNNING; 910 ifp->if_timer = 0; 911 sc->tx_busy = false; 912 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 913 } 914 915 static void 916 cemac_setaddr(struct ifnet *ifp) 917 { 918 struct cemac_softc * const sc = ifp->if_softc; 919 struct ethercom *ec = &sc->sc_ethercom; 920 struct ether_multi *enm; 921 struct ether_multistep step; 922 uint8_t ias[3][ETHER_ADDR_LEN]; 923 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 924 uint32_t ctl = CEMAC_READ(ETH_CTL); 925 uint32_t cfg = CEMAC_READ(ETH_CFG); 926 927 /* disable receiver temporarily */ 928 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 929 930 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 931 932 if (ifp->if_flags & IFF_PROMISC) { 933 cfg |= ETH_CFG_CAF; 934 } else { 935 cfg &= ~ETH_CFG_CAF; 936 } 937 938 // ETH_CFG_BIG? 939 940 ifp->if_flags &= ~IFF_ALLMULTI; 941 942 ETHER_LOCK(ec); 943 ETHER_FIRST_MULTI(step, ec, enm); 944 while (enm != NULL) { 945 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 946 /* 947 * We must listen to a range of multicast addresses. 948 * For now, just accept all multicasts, rather than 949 * trying to set only those filter bits needed to match 950 * the range. (At this time, the only use of address 951 * ranges is for IP multicast routing, for which the 952 * range is big enough to require all bits set.) 953 */ 954 cfg |= ETH_CFG_MTI; 955 hashes[0] = 0xffffffffUL; 956 hashes[1] = 0xffffffffUL; 957 ifp->if_flags |= IFF_ALLMULTI; 958 nma = 0; 959 break; 960 } 961 962 if (nma < 3) { 963 /* We can program 3 perfect address filters for mcast */ 964 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 965 } else { 966 /* 967 * XXX: Datasheet is not very clear here, I'm not sure 968 * if I'm doing this right. --joff 969 */ 970 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 971 972 /* Just want the 6 most-significant bits. */ 973 h = h >> 26; 974 #if 0 975 hashes[h / 32] |= (1 << (h % 32)); 976 #else 977 hashes[0] = 0xffffffffUL; 978 hashes[1] = 0xffffffffUL; 979 #endif 980 cfg |= ETH_CFG_MTI; 981 } 982 ETHER_NEXT_MULTI(step, enm); 983 nma++; 984 } 985 ETHER_UNLOCK(ec); 986 987 // program... 988 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 989 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 990 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 991 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 992 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 993 | (sc->sc_enaddr[0])); 994 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 995 | (sc->sc_enaddr[4])); 996 if (nma > 0) { 997 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", 998 __FUNCTION__, 999 ias[0][0], ias[0][1], ias[0][2], 1000 ias[0][3], ias[0][4], ias[0][5])); 1001 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 1002 | (ias[0][2] << 16) | (ias[0][1] << 8) 1003 | (ias[0][0])); 1004 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 1005 | (ias[0][5])); 1006 } 1007 if (nma > 1) { 1008 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", 1009 __FUNCTION__, 1010 ias[1][0], ias[1][1], ias[1][2], 1011 ias[1][3], ias[1][4], ias[1][5])); 1012 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1013 | (ias[1][2] << 16) | (ias[1][1] << 8) 1014 | (ias[1][0])); 1015 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1016 | (ias[1][5])); 1017 } 1018 if (nma > 2) { 1019 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", 1020 __FUNCTION__, 1021 ias[2][0], ias[2][1], ias[2][2], 1022 ias[2][3], ias[2][4], ias[2][5])); 1023 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1024 | (ias[2][2] << 16) | (ias[2][1] << 8) 1025 | (ias[2][0])); 1026 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1027 | (ias[2][5])); 1028 } 1029 CEMAC_GEM_WRITE(HSH, hashes[0]); 1030 CEMAC_GEM_WRITE(HSL, hashes[1]); 1031 CEMAC_WRITE(ETH_CFG, cfg); 1032 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1033 } 1034
Indexes created Wed Sep 24 05:09:52 GMT 2025