if_cemac.c revision 1.6
1 /* $NetBSD: if_cemac.c,v 1.6 2015/08/24 18:40:57 rjs Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.6 2015/08/24 18:40:57 rjs Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/kernel.h> 50 #include <sys/proc.h> 51 #include <sys/malloc.h> 52 #include <sys/time.h> 53 #include <sys/device.h> 54 #include <uvm/uvm_extern.h> 55 56 #include <sys/bus.h> 57 #include <machine/intr.h> 58 59 #include <arm/cpufunc.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_types.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #ifdef INET 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 #include <netinet/if_inarp.h> 76 #endif 77 78 #include <net/bpf.h> 79 #include <net/bpfdesc.h> 80 81 #ifdef IPKDB_AT91 // @@@ 82 #include <ipkdb/ipkdb.h> 83 #endif 84 85 #include <dev/cadence/cemacreg.h> 86 #include <dev/cadence/if_cemacvar.h> 87 88 #define DEFAULT_MDCDIV 32 89 90 #define CEMAC_READ(x) \ 91 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 92 #define CEMAC_WRITE(x, y) \ 93 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 94 #define CEMAC_GEM_WRITE(x, y) \ 95 do { \ 96 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 97 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 98 else \ 99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 100 } while(0) 101 102 #define RX_QLEN 64 103 #define TX_QLEN 2 /* I'm very sorry but that's where we can get */ 104 105 struct cemac_qmeta { 106 struct mbuf *m; 107 bus_dmamap_t m_dmamap; 108 }; 109 110 struct cemac_softc { 111 device_t sc_dev; 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_ioh; 114 bus_dma_tag_t sc_dmat; 115 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 116 struct ethercom sc_ethercom; 117 mii_data_t sc_mii; 118 119 void *rbqpage; 120 unsigned rbqlen; 121 bus_addr_t rbqpage_dsaddr; 122 bus_dmamap_t rbqpage_dmamap; 123 void *tbqpage; 124 unsigned tbqlen; 125 bus_addr_t tbqpage_dsaddr; 126 bus_dmamap_t tbqpage_dmamap; 127 128 volatile struct eth_dsc *RDSC; 129 int rxqi; 130 struct cemac_qmeta rxq[RX_QLEN]; 131 volatile struct eth_dsc *TDSC; 132 int txqi, txqc; 133 struct cemac_qmeta txq[TX_QLEN]; 134 callout_t cemac_tick_ch; 135 136 int cemac_flags; 137 }; 138 139 static void cemac_init(struct cemac_softc *); 140 static int cemac_gctx(struct cemac_softc *); 141 static int cemac_mediachange(struct ifnet *); 142 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 143 static int cemac_mii_readreg(device_t, int, int); 144 static void cemac_mii_writereg(device_t, int, int, int); 145 static void cemac_statchg(struct ifnet *); 146 static void cemac_tick(void *); 147 static int cemac_ifioctl(struct ifnet *, u_long, void *); 148 static void cemac_ifstart(struct ifnet *); 149 static void cemac_ifwatchdog(struct ifnet *); 150 static int cemac_ifinit(struct ifnet *); 151 static void cemac_ifstop(struct ifnet *, int); 152 static void cemac_setaddr(struct ifnet *); 153 154 #ifdef CEMAC_DEBUG 155 int cemac_debug = CEMAC_DEBUG; 156 #define DPRINTFN(n,fmt) if (cemac_debug >= (n)) printf fmt 157 #else 158 #define DPRINTFN(n,fmt) 159 #endif 160 161 CFATTACH_DECL_NEW(cemac, sizeof(struct cemac_softc), 162 cemac_match, cemac_attach, NULL, NULL); 163 164 int 165 cemac_match_common(device_t parent, cfdata_t match, void *aux) 166 { 167 if (strcmp(match->cf_name, "cemac") == 0) 168 return 1; 169 return 0; 170 } 171 172 void 173 cemac_attach_common(device_t self, bus_space_tag_t iot, 174 bus_space_handle_t ioh, bus_dma_tag_t dmat, int flags) 175 { 176 struct cemac_softc *sc = device_private(self); 177 prop_data_t enaddr; 178 uint32_t u; 179 180 181 sc->sc_dev = self; 182 sc->sc_ioh = ioh; 183 sc->sc_iot = iot; 184 sc->sc_dmat = dmat; 185 sc->cemac_flags = flags; 186 187 aprint_naive("\n"); 188 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 189 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 190 else 191 aprint_normal(": Cadence Ethernet Controller\n"); 192 193 /* configure emac: */ 194 CEMAC_WRITE(ETH_CTL, 0); // disable everything 195 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 196 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 197 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 198 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 199 CEMAC_WRITE(ETH_CFG, 200 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 201 else 202 CEMAC_WRITE(ETH_CFG, 203 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 204 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 205 //(void)CEMAC_READ(ETH_ISR); 206 u = CEMAC_READ(ETH_TSR); 207 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 208 | ETH_TSR_IDLE | ETH_TSR_RLE 209 | ETH_TSR_COL|ETH_TSR_OVR))); 210 u = CEMAC_READ(ETH_RSR); 211 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 212 213 /* Fetch the Ethernet address from property if set. */ 214 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 215 216 if (enaddr != NULL) { 217 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 218 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 219 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 220 ETHER_ADDR_LEN); 221 } else { 222 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 223 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 224 }; 225 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 226 } 227 228 cemac_init(sc); 229 } 230 231 static int 232 cemac_gctx(struct cemac_softc *sc) 233 { 234 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 235 uint32_t tsr; 236 237 tsr = CEMAC_READ(ETH_TSR); 238 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 239 // no space left 240 if (!(tsr & ETH_TSR_BNQ)) 241 return 0; 242 } else { 243 if (tsr & GEM_TSR_TXGO) 244 return 0; 245 } 246 CEMAC_WRITE(ETH_TSR, tsr); 247 248 // free sent frames 249 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 250 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 251 int bi = sc->txqi % TX_QLEN; 252 253 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 254 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 255 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 256 __FUNCTION__, bi, sc->TDSC[bi].Info)); 257 258 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 259 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 260 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 261 m_freem(sc->txq[bi].m); 262 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 263 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 264 sc->txq[bi].m = NULL; 265 sc->txqi = (bi + 1) % TX_QLEN; 266 sc->txqc--; 267 } 268 269 // mark we're free 270 if (ifp->if_flags & IFF_OACTIVE) { 271 ifp->if_flags &= ~IFF_OACTIVE; 272 /* Disable transmit-buffer-free interrupt */ 273 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 274 } 275 276 return 1; 277 } 278 279 int 280 cemac_intr(void *arg) 281 { 282 struct cemac_softc *sc = (struct cemac_softc *)arg; 283 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 284 uint32_t imr, isr, ctl; 285 #ifdef CEMAC_DEBUG 286 uint32_t rsr; 287 #endif 288 int bi; 289 290 imr = ~CEMAC_READ(ETH_IMR); 291 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR|ETH_ISR_TCOM))) { 292 // interrupt not enabled, can't be us 293 return 0; 294 } 295 296 isr = CEMAC_READ(ETH_ISR); 297 CEMAC_WRITE(ETH_ISR, isr); 298 isr &= imr; 299 #ifdef CEMAC_DEBUG 300 rsr = CEMAC_READ(ETH_RSR); // get receive status register 301 #endif 302 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 303 304 if (isr & ETH_ISR_RBNA) { // out of receive buffers 305 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 306 ctl = CEMAC_READ(ETH_CTL); // get current control register value 307 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 308 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 309 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 310 ifp->if_ierrors++; 311 ifp->if_ipackets++; 312 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 313 } 314 if (isr & ETH_ISR_ROVR) { 315 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 316 ifp->if_ierrors++; 317 ifp->if_ipackets++; 318 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 319 } 320 321 if (isr & ETH_ISR_RCOM) { // packet has been received! 322 uint32_t nfo; 323 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 324 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 325 int fl; 326 struct mbuf *m; 327 328 nfo = sc->RDSC[bi].Info; 329 fl = (nfo & ETH_RDSC_I_LEN) - 4; 330 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 331 332 MGETHDR(m, M_DONTWAIT, MT_DATA); 333 if (m != NULL) MCLGET(m, M_DONTWAIT); 334 if (m != NULL && (m->m_flags & M_EXT)) { 335 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 336 MCLBYTES, BUS_DMASYNC_POSTREAD); 337 bus_dmamap_unload(sc->sc_dmat, 338 sc->rxq[bi].m_dmamap); 339 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 340 sc->rxq[bi].m->m_pkthdr.len = 341 sc->rxq[bi].m->m_len = fl; 342 bpf_mtap(ifp, sc->rxq[bi].m); 343 DPRINTFN(2,("received %u bytes packet\n", fl)); 344 (*ifp->if_input)(ifp, sc->rxq[bi].m); 345 if (mtod(m, intptr_t) & 3) 346 m_adj(m, mtod(m, intptr_t) & 3); 347 sc->rxq[bi].m = m; 348 bus_dmamap_load(sc->sc_dmat, 349 sc->rxq[bi].m_dmamap, 350 m->m_ext.ext_buf, MCLBYTES, 351 NULL, BUS_DMA_NOWAIT); 352 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 353 MCLBYTES, BUS_DMASYNC_PREREAD); 354 sc->RDSC[bi].Info = 0; 355 sc->RDSC[bi].Addr = 356 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 357 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 358 } else { 359 /* Drop packets until we can get replacement 360 * empty mbufs for the RXDQ. 361 */ 362 if (m != NULL) 363 m_freem(m); 364 ifp->if_ierrors++; 365 } 366 sc->rxqi++; 367 } 368 } 369 370 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 371 cemac_ifstart(ifp); 372 #if 0 // reloop 373 irq = CEMAC_READ(IntStsC); 374 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 375 goto begin; 376 #endif 377 378 return (1); 379 } 380 381 382 static void 383 cemac_init(struct cemac_softc *sc) 384 { 385 bus_dma_segment_t segs; 386 int rsegs, err, i; 387 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 388 uint32_t u; 389 #if 0 390 int mdcdiv = DEFAULT_MDCDIV; 391 #endif 392 393 callout_init(&sc->cemac_tick_ch, 0); 394 395 // ok... 396 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 397 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 398 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 399 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 400 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 401 CEMAC_WRITE(ETH_CFG, 402 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 403 else 404 CEMAC_WRITE(ETH_CFG, 405 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 406 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 407 CEMAC_WRITE(GEM_DMA_CFG, 408 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 409 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 410 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 411 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 412 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 413 } 414 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 415 // (void)CEMAC_READ(ETH_ISR); 416 u = CEMAC_READ(ETH_TSR); 417 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 418 | ETH_TSR_IDLE | ETH_TSR_RLE 419 | ETH_TSR_COL|ETH_TSR_OVR))); 420 u = CEMAC_READ(ETH_RSR); 421 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 422 423 #if 0 424 if (device_cfdata(sc->sc_dev)->cf_flags) 425 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 426 #endif 427 /* set ethernet address */ 428 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 429 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 430 | (sc->sc_enaddr[0])); 431 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 432 | (sc->sc_enaddr[4])); 433 CEMAC_GEM_WRITE(SA2L, 0); 434 CEMAC_GEM_WRITE(SA2H, 0); 435 CEMAC_GEM_WRITE(SA3L, 0); 436 CEMAC_GEM_WRITE(SA3H, 0); 437 CEMAC_GEM_WRITE(SA4L, 0); 438 CEMAC_GEM_WRITE(SA4H, 0); 439 440 /* Allocate a page of memory for receive queue descriptors */ 441 sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 442 sc->rbqlen *= PAGE_SIZE; 443 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 444 445 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 446 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 447 &segs, 1, &rsegs, BUS_DMA_WAITOK); 448 if (err == 0) { 449 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 450 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 451 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 452 } 453 if (err == 0) { 454 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 455 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 456 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 457 &sc->rbqpage_dmamap); 458 } 459 if (err == 0) { 460 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 461 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 462 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 463 } 464 if (err != 0) 465 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 466 467 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 468 memset(sc->rbqpage, 0, sc->rbqlen); 469 470 /* Allocate a page of memory for transmit queue descriptors */ 471 sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 472 sc->tbqlen *= PAGE_SIZE; 473 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 474 475 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 476 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 477 &segs, 1, &rsegs, BUS_DMA_WAITOK); 478 if (err == 0) { 479 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 480 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 481 &sc->tbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 482 } 483 if (err == 0) { 484 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 485 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 486 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 487 &sc->tbqpage_dmamap); 488 } 489 if (err == 0) { 490 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 491 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 492 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 493 } 494 if (err != 0) 495 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 496 497 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 498 memset(sc->tbqpage, 0, sc->tbqlen); 499 500 /* Set up pointers to start of each queue in kernel addr space. 501 * Each descriptor queue or status queue entry uses 2 words 502 */ 503 sc->RDSC = (void *)sc->rbqpage; 504 sc->TDSC = (void *)sc->tbqpage; 505 506 /* init TX queue */ 507 for (i = 0; i < TX_QLEN; i++) { 508 sc->TDSC[i].Addr = 0; 509 sc->TDSC[i].Info = ETH_TDSC_I_USED | 510 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 511 } 512 513 /* Populate the RXQ with mbufs */ 514 sc->rxqi = 0; 515 for(i = 0; i < RX_QLEN; i++) { 516 struct mbuf *m; 517 518 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 519 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 520 if (err) { 521 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 522 } 523 MGETHDR(m, M_WAIT, MT_DATA); 524 MCLGET(m, M_WAIT); 525 sc->rxq[i].m = m; 526 if (mtod(m, intptr_t) & 3) { 527 m_adj(m, mtod(m, intptr_t) & 3); 528 } 529 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 530 m->m_ext.ext_buf, MCLBYTES, NULL, 531 BUS_DMA_WAITOK); 532 if (err) { 533 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 534 } 535 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 536 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 537 sc->RDSC[i].Info = 0; 538 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 539 MCLBYTES, BUS_DMASYNC_PREREAD); 540 } 541 542 /* prepare transmit queue */ 543 for (i = 0; i < TX_QLEN; i++) { 544 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 545 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 546 &sc->txq[i].m_dmamap); 547 if (err) 548 panic("ARGH #1"); 549 sc->txq[i].m = NULL; 550 } 551 552 /* Program each queue's start addr, cur addr, and len registers 553 * with the physical addresses. 554 */ 555 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 556 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 557 558 /* Divide HCLK by 32 for MDC clock */ 559 sc->sc_ethercom.ec_mii = &sc->sc_mii; 560 sc->sc_mii.mii_ifp = ifp; 561 sc->sc_mii.mii_readreg = cemac_mii_readreg; 562 sc->sc_mii.mii_writereg = cemac_mii_writereg; 563 sc->sc_mii.mii_statchg = cemac_statchg; 564 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, cemac_mediachange, 565 cemac_mediastatus); 566 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 567 MII_OFFSET_ANY, 0); 568 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 569 570 #if 0 571 // enable / disable interrupts 572 CEMAC_WRITE(ETH_IDR, -1); 573 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 574 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 575 // (void)CEMAC_READ(ETH_ISR); // why 576 577 // enable transmitter / receiver 578 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 579 | ETH_CTL_CSR | ETH_CTL_MPE); 580 #endif 581 /* 582 * We can support 802.1Q VLAN-sized frames. 583 */ 584 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 585 586 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 587 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 588 ifp->if_ioctl = cemac_ifioctl; 589 ifp->if_start = cemac_ifstart; 590 ifp->if_watchdog = cemac_ifwatchdog; 591 ifp->if_init = cemac_ifinit; 592 ifp->if_stop = cemac_ifstop; 593 ifp->if_timer = 0; 594 ifp->if_softc = sc; 595 IFQ_SET_READY(&ifp->if_snd); 596 if_attach(ifp); 597 ether_ifattach(ifp, (sc)->sc_enaddr); 598 } 599 600 static int 601 cemac_mediachange(struct ifnet *ifp) 602 { 603 if (ifp->if_flags & IFF_UP) 604 cemac_ifinit(ifp); 605 return (0); 606 } 607 608 static void 609 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 610 { 611 struct cemac_softc *sc = ifp->if_softc; 612 613 mii_pollstat(&sc->sc_mii); 614 ifmr->ifm_active = sc->sc_mii.mii_media_active; 615 ifmr->ifm_status = sc->sc_mii.mii_media_status; 616 } 617 618 619 static int 620 cemac_mii_readreg(device_t self, int phy, int reg) 621 { 622 struct cemac_softc *sc; 623 624 sc = device_private(self); 625 626 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 627 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 628 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 629 | ETH_MAN_CODE_IEEE802_3)); 630 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)); 631 632 return (CEMAC_READ(ETH_MAN) & ETH_MAN_DATA); 633 } 634 635 static void 636 cemac_mii_writereg(device_t self, int phy, int reg, int val) 637 { 638 struct cemac_softc *sc; 639 640 sc = device_private(self); 641 642 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 643 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 644 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 645 | ETH_MAN_CODE_IEEE802_3 646 | (val & ETH_MAN_DATA))); 647 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 648 } 649 650 651 static void 652 cemac_statchg(struct ifnet *ifp) 653 { 654 struct cemac_softc *sc = ifp->if_softc; 655 struct mii_data *mii = &sc->sc_mii; 656 uint32_t reg; 657 658 /* 659 * We must keep the MAC and the PHY in sync as 660 * to the status of full-duplex! 661 */ 662 reg = CEMAC_READ(ETH_CFG); 663 reg &= ~ETH_CFG_FD; 664 if (sc->sc_mii.mii_media_active & IFM_FDX) 665 reg |= ETH_CFG_FD; 666 667 reg &= ~ETH_CFG_SPD; 668 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 669 reg &= ~GEM_CFG_GEN; 670 switch (IFM_SUBTYPE(mii->mii_media_active)) { 671 case IFM_10_T: 672 break; 673 case IFM_100_TX: 674 reg |= ETH_CFG_SPD; 675 break; 676 case IFM_1000_T: 677 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 678 break; 679 default: 680 break; 681 } 682 CEMAC_WRITE(ETH_CFG, reg); 683 } 684 685 static void 686 cemac_tick(void *arg) 687 { 688 struct cemac_softc* sc = (struct cemac_softc *)arg; 689 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 690 int s; 691 692 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 693 ifp->if_collisions += CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL); 694 else 695 ifp->if_collisions += CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL); 696 697 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 698 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 699 uint32_t misses = CEMAC_READ(ETH_DRFC); 700 if (misses > 0) 701 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 702 } 703 704 s = splnet(); 705 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 706 cemac_ifstart(ifp); 707 splx(s); 708 709 mii_tick(&sc->sc_mii); 710 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 711 } 712 713 714 static int 715 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 716 { 717 struct cemac_softc *sc = ifp->if_softc; 718 struct ifreq *ifr = (struct ifreq *)data; 719 int s, error; 720 721 s = splnet(); 722 switch(cmd) { 723 case SIOCSIFMEDIA: 724 case SIOCGIFMEDIA: 725 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 726 break; 727 default: 728 error = ether_ioctl(ifp, cmd, data); 729 if (error == ENETRESET) { 730 if (ifp->if_flags & IFF_RUNNING) 731 cemac_setaddr(ifp); 732 error = 0; 733 } 734 } 735 splx(s); 736 return error; 737 } 738 739 static void 740 cemac_ifstart(struct ifnet *ifp) 741 { 742 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 743 struct mbuf *m; 744 bus_dma_segment_t *segs; 745 int s, bi, err, nsegs; 746 747 s = splnet(); 748 start: 749 if (cemac_gctx(sc) == 0) { 750 /* Enable transmit-buffer-free interrupt */ 751 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 752 ifp->if_flags |= IFF_OACTIVE; 753 ifp->if_timer = 10; 754 splx(s); 755 return; 756 } 757 758 ifp->if_timer = 0; 759 760 IFQ_POLL(&ifp->if_snd, m); 761 if (m == NULL) { 762 splx(s); 763 return; 764 } 765 766 bi = (sc->txqi + sc->txqc) % TX_QLEN; 767 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 768 BUS_DMA_NOWAIT)) || 769 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 770 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 771 /* Copy entire mbuf chain to new single */ 772 struct mbuf *mn; 773 774 if (err == 0) 775 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 776 777 MGETHDR(mn, M_DONTWAIT, MT_DATA); 778 if (mn == NULL) goto stop; 779 if (m->m_pkthdr.len > MHLEN) { 780 MCLGET(mn, M_DONTWAIT); 781 if ((mn->m_flags & M_EXT) == 0) { 782 m_freem(mn); 783 goto stop; 784 } 785 } 786 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 787 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 788 IFQ_DEQUEUE(&ifp->if_snd, m); 789 m_freem(m); 790 m = mn; 791 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 792 BUS_DMA_NOWAIT); 793 } else { 794 IFQ_DEQUEUE(&ifp->if_snd, m); 795 } 796 797 bpf_mtap(ifp, m); 798 799 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 800 segs = sc->txq[bi].m_dmamap->dm_segs; 801 if (nsegs > 1) 802 panic("#### ARGH #2"); 803 804 sc->txq[bi].m = m; 805 sc->txqc++; 806 807 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 808 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 809 (unsigned)m->m_pkthdr.len)); 810 #ifdef DIAGNOSTIC 811 if (sc->txqc > TX_QLEN) 812 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 813 #endif 814 815 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 816 sc->txq[bi].m_dmamap->dm_mapsize, 817 BUS_DMASYNC_PREWRITE); 818 819 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 820 sc->TDSC[bi].Addr = segs->ds_addr; 821 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 822 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 823 824 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 825 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 826 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 827 __FUNCTION__, bi, sc->TDSC[bi].Info)); 828 829 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 830 CEMAC_WRITE(ETH_CTL, ctl); 831 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 832 } else { 833 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 834 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 835 } 836 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 837 goto start; 838 stop: 839 840 splx(s); 841 return; 842 } 843 844 static void 845 cemac_ifwatchdog(struct ifnet *ifp) 846 { 847 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 848 849 if ((ifp->if_flags & IFF_RUNNING) == 0) 850 return; 851 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 852 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 853 } 854 855 static int 856 cemac_ifinit(struct ifnet *ifp) 857 { 858 struct cemac_softc *sc = ifp->if_softc; 859 int s = splnet(); 860 861 callout_stop(&sc->cemac_tick_ch); 862 863 // enable interrupts 864 CEMAC_WRITE(ETH_IDR, -1); 865 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 866 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 867 868 // enable transmitter / receiver 869 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 870 | ETH_CTL_CSR | ETH_CTL_MPE); 871 872 mii_mediachg(&sc->sc_mii); 873 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 874 ifp->if_flags |= IFF_RUNNING; 875 splx(s); 876 return 0; 877 } 878 879 static void 880 cemac_ifstop(struct ifnet *ifp, int disable) 881 { 882 // uint32_t u; 883 struct cemac_softc *sc = ifp->if_softc; 884 885 #if 0 886 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 887 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 888 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 889 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 890 CEMAC_WRITE(ETH_CFG, 891 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 892 else 893 CEMAC_WRITE(ETH_CFG, 894 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 895 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 896 // (void)CEMAC_READ(ETH_ISR); 897 u = CEMAC_READ(ETH_TSR); 898 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 899 | ETH_TSR_IDLE | ETH_TSR_RLE 900 | ETH_TSR_COL|ETH_TSR_OVR))); 901 u = CEMAC_READ(ETH_RSR); 902 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 903 #endif 904 callout_stop(&sc->cemac_tick_ch); 905 906 /* Down the MII. */ 907 mii_down(&sc->sc_mii); 908 909 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 910 ifp->if_timer = 0; 911 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 912 } 913 914 static void 915 cemac_setaddr(struct ifnet *ifp) 916 { 917 struct cemac_softc *sc = ifp->if_softc; 918 struct ethercom *ac = &sc->sc_ethercom; 919 struct ether_multi *enm; 920 struct ether_multistep step; 921 uint8_t ias[3][ETHER_ADDR_LEN]; 922 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 923 uint32_t ctl = CEMAC_READ(ETH_CTL); 924 uint32_t cfg = CEMAC_READ(ETH_CFG); 925 926 /* disable receiver temporarily */ 927 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 928 929 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 930 931 if (ifp->if_flags & IFF_PROMISC) { 932 cfg |= ETH_CFG_CAF; 933 } else { 934 cfg &= ~ETH_CFG_CAF; 935 } 936 937 // ETH_CFG_BIG? 938 939 ifp->if_flags &= ~IFF_ALLMULTI; 940 941 ETHER_FIRST_MULTI(step, ac, enm); 942 while (enm != NULL) { 943 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 944 /* 945 * We must listen to a range of multicast addresses. 946 * For now, just accept all multicasts, rather than 947 * trying to set only those filter bits needed to match 948 * the range. (At this time, the only use of address 949 * ranges is for IP multicast routing, for which the 950 * range is big enough to require all bits set.) 951 */ 952 cfg |= ETH_CFG_MTI; 953 hashes[0] = 0xffffffffUL; 954 hashes[1] = 0xffffffffUL; 955 ifp->if_flags |= IFF_ALLMULTI; 956 nma = 0; 957 break; 958 } 959 960 if (nma < 3) { 961 /* We can program 3 perfect address filters for mcast */ 962 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 963 } else { 964 /* 965 * XXX: Datasheet is not very clear here, I'm not sure 966 * if I'm doing this right. --joff 967 */ 968 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 969 970 /* Just want the 6 most-significant bits. */ 971 h = h >> 26; 972 #if 0 973 hashes[h / 32] |= (1 << (h % 32)); 974 #else 975 hashes[0] = 0xffffffffUL; 976 hashes[1] = 0xffffffffUL; 977 #endif 978 cfg |= ETH_CFG_MTI; 979 } 980 ETHER_NEXT_MULTI(step, enm); 981 nma++; 982 } 983 984 // program... 985 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 986 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 987 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 988 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 989 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 990 | (sc->sc_enaddr[0])); 991 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 992 | (sc->sc_enaddr[4])); 993 if (nma > 0) { 994 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 995 ias[0][0], ias[0][1], ias[0][2], 996 ias[0][3], ias[0][4], ias[0][5])); 997 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 998 | (ias[0][2] << 16) | (ias[0][1] << 8) 999 | (ias[0][0])); 1000 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 1001 | (ias[0][5])); 1002 } 1003 if (nma > 1) { 1004 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1005 ias[1][0], ias[1][1], ias[1][2], 1006 ias[1][3], ias[1][4], ias[1][5])); 1007 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1008 | (ias[1][2] << 16) | (ias[1][1] << 8) 1009 | (ias[1][0])); 1010 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1011 | (ias[1][5])); 1012 } 1013 if (nma > 2) { 1014 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1015 ias[2][0], ias[2][1], ias[2][2], 1016 ias[2][3], ias[2][4], ias[2][5])); 1017 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1018 | (ias[2][2] << 16) | (ias[2][1] << 8) 1019 | (ias[2][0])); 1020 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1021 | (ias[2][5])); 1022 } 1023 CEMAC_GEM_WRITE(HSH, hashes[0]); 1024 CEMAC_GEM_WRITE(HSL, hashes[1]); 1025 CEMAC_WRITE(ETH_CFG, cfg); 1026 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1027 } 1028
Indexes created Tue Sep 23 02:09:52 GMT 2025