if_cemac.c revision 1.8
1 /* $NetBSD: if_cemac.c,v 1.8 2016/02/09 08:32:10 ozaki-r Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.8 2016/02/09 08:32:10 ozaki-r Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/kernel.h> 50 #include <sys/proc.h> 51 #include <sys/malloc.h> 52 #include <sys/time.h> 53 #include <sys/device.h> 54 #include <uvm/uvm_extern.h> 55 56 #include <sys/bus.h> 57 #include <machine/intr.h> 58 59 #include <arm/cpufunc.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_types.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #ifdef INET 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 #include <netinet/if_inarp.h> 76 #endif 77 78 #include <net/bpf.h> 79 #include <net/bpfdesc.h> 80 81 #ifdef IPKDB_AT91 // @@@ 82 #include <ipkdb/ipkdb.h> 83 #endif 84 85 #include <dev/cadence/cemacreg.h> 86 #include <dev/cadence/if_cemacvar.h> 87 88 #define DEFAULT_MDCDIV 32 89 90 #define CEMAC_READ(x) \ 91 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 92 #define CEMAC_WRITE(x, y) \ 93 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 94 #define CEMAC_GEM_WRITE(x, y) \ 95 do { \ 96 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 97 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 98 else \ 99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 100 } while(0) 101 102 #define RX_QLEN 64 103 #define TX_QLEN 2 /* I'm very sorry but that's where we can get */ 104 105 struct cemac_qmeta { 106 struct mbuf *m; 107 bus_dmamap_t m_dmamap; 108 }; 109 110 struct cemac_softc { 111 device_t sc_dev; 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_ioh; 114 bus_dma_tag_t sc_dmat; 115 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 116 struct ethercom sc_ethercom; 117 mii_data_t sc_mii; 118 119 void *rbqpage; 120 unsigned rbqlen; 121 bus_addr_t rbqpage_dsaddr; 122 bus_dmamap_t rbqpage_dmamap; 123 void *tbqpage; 124 unsigned tbqlen; 125 bus_addr_t tbqpage_dsaddr; 126 bus_dmamap_t tbqpage_dmamap; 127 128 volatile struct eth_dsc *RDSC; 129 int rxqi; 130 struct cemac_qmeta rxq[RX_QLEN]; 131 volatile struct eth_dsc *TDSC; 132 int txqi, txqc; 133 struct cemac_qmeta txq[TX_QLEN]; 134 callout_t cemac_tick_ch; 135 136 int cemac_flags; 137 }; 138 139 static void cemac_init(struct cemac_softc *); 140 static int cemac_gctx(struct cemac_softc *); 141 static int cemac_mediachange(struct ifnet *); 142 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 143 static int cemac_mii_readreg(device_t, int, int); 144 static void cemac_mii_writereg(device_t, int, int, int); 145 static void cemac_statchg(struct ifnet *); 146 static void cemac_tick(void *); 147 static int cemac_ifioctl(struct ifnet *, u_long, void *); 148 static void cemac_ifstart(struct ifnet *); 149 static void cemac_ifwatchdog(struct ifnet *); 150 static int cemac_ifinit(struct ifnet *); 151 static void cemac_ifstop(struct ifnet *, int); 152 static void cemac_setaddr(struct ifnet *); 153 154 #ifdef CEMAC_DEBUG 155 int cemac_debug = CEMAC_DEBUG; 156 #define DPRINTFN(n,fmt) if (cemac_debug >= (n)) printf fmt 157 #else 158 #define DPRINTFN(n,fmt) 159 #endif 160 161 CFATTACH_DECL_NEW(cemac, sizeof(struct cemac_softc), 162 cemac_match, cemac_attach, NULL, NULL); 163 164 int 165 cemac_match_common(device_t parent, cfdata_t match, void *aux) 166 { 167 if (strcmp(match->cf_name, "cemac") == 0) 168 return 1; 169 return 0; 170 } 171 172 void 173 cemac_attach_common(device_t self, bus_space_tag_t iot, 174 bus_space_handle_t ioh, bus_dma_tag_t dmat, int flags) 175 { 176 struct cemac_softc *sc = device_private(self); 177 prop_data_t enaddr; 178 uint32_t u; 179 180 181 sc->sc_dev = self; 182 sc->sc_ioh = ioh; 183 sc->sc_iot = iot; 184 sc->sc_dmat = dmat; 185 sc->cemac_flags = flags; 186 187 aprint_naive("\n"); 188 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 189 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 190 else 191 aprint_normal(": Cadence Ethernet Controller\n"); 192 193 /* configure emac: */ 194 CEMAC_WRITE(ETH_CTL, 0); // disable everything 195 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 196 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 197 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 198 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 199 CEMAC_WRITE(ETH_CFG, 200 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 201 else 202 CEMAC_WRITE(ETH_CFG, 203 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 204 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 205 //(void)CEMAC_READ(ETH_ISR); 206 u = CEMAC_READ(ETH_TSR); 207 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 208 | ETH_TSR_IDLE | ETH_TSR_RLE 209 | ETH_TSR_COL|ETH_TSR_OVR))); 210 u = CEMAC_READ(ETH_RSR); 211 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 212 213 /* Fetch the Ethernet address from property if set. */ 214 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 215 216 if (enaddr != NULL) { 217 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 218 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 219 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 220 ETHER_ADDR_LEN); 221 } else { 222 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 223 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 224 }; 225 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 226 } 227 228 cemac_init(sc); 229 } 230 231 static int 232 cemac_gctx(struct cemac_softc *sc) 233 { 234 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 235 uint32_t tsr; 236 237 tsr = CEMAC_READ(ETH_TSR); 238 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 239 // no space left 240 if (!(tsr & ETH_TSR_BNQ)) 241 return 0; 242 } else { 243 if (tsr & GEM_TSR_TXGO) 244 return 0; 245 } 246 CEMAC_WRITE(ETH_TSR, tsr); 247 248 // free sent frames 249 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 250 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 251 int bi = sc->txqi % TX_QLEN; 252 253 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 254 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 255 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 256 __FUNCTION__, bi, sc->TDSC[bi].Info)); 257 258 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 259 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 260 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 261 m_freem(sc->txq[bi].m); 262 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 263 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 264 sc->txq[bi].m = NULL; 265 sc->txqi = (bi + 1) % TX_QLEN; 266 sc->txqc--; 267 } 268 269 // mark we're free 270 if (ifp->if_flags & IFF_OACTIVE) { 271 ifp->if_flags &= ~IFF_OACTIVE; 272 /* Disable transmit-buffer-free interrupt */ 273 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 274 } 275 276 return 1; 277 } 278 279 int 280 cemac_intr(void *arg) 281 { 282 struct cemac_softc *sc = (struct cemac_softc *)arg; 283 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 284 uint32_t imr, isr, ctl; 285 #ifdef CEMAC_DEBUG 286 uint32_t rsr; 287 #endif 288 int bi; 289 290 imr = ~CEMAC_READ(ETH_IMR); 291 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR|ETH_ISR_TCOM))) { 292 // interrupt not enabled, can't be us 293 return 0; 294 } 295 296 isr = CEMAC_READ(ETH_ISR); 297 CEMAC_WRITE(ETH_ISR, isr); 298 isr &= imr; 299 #ifdef CEMAC_DEBUG 300 rsr = CEMAC_READ(ETH_RSR); // get receive status register 301 #endif 302 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 303 304 if (isr & ETH_ISR_RBNA) { // out of receive buffers 305 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 306 ctl = CEMAC_READ(ETH_CTL); // get current control register value 307 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 308 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 309 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 310 ifp->if_ierrors++; 311 ifp->if_ipackets++; 312 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 313 } 314 if (isr & ETH_ISR_ROVR) { 315 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 316 ifp->if_ierrors++; 317 ifp->if_ipackets++; 318 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 319 } 320 321 if (isr & ETH_ISR_RCOM) { // packet has been received! 322 uint32_t nfo; 323 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 324 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 325 int fl, csum; 326 struct mbuf *m; 327 328 nfo = sc->RDSC[bi].Info; 329 fl = (nfo & ETH_RDSC_I_LEN) - 4; 330 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 331 332 MGETHDR(m, M_DONTWAIT, MT_DATA); 333 if (m != NULL) MCLGET(m, M_DONTWAIT); 334 if (m != NULL && (m->m_flags & M_EXT)) { 335 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 336 MCLBYTES, BUS_DMASYNC_POSTREAD); 337 bus_dmamap_unload(sc->sc_dmat, 338 sc->rxq[bi].m_dmamap); 339 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 340 sc->rxq[bi].m->m_pkthdr.len = 341 sc->rxq[bi].m->m_len = fl; 342 switch (nfo & ETH_RDSC_I_CHKSUM) { 343 case ETH_RDSC_I_CHKSUM_IP: 344 csum = M_CSUM_IPv4; 345 break; 346 case ETH_RDSC_I_CHKSUM_UDP: 347 csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 348 M_CSUM_UDPv6; 349 break; 350 case ETH_RDSC_I_CHKSUM_TCP: 351 csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 352 M_CSUM_TCPv6; 353 break; 354 default: 355 csum = 0; 356 break; 357 } 358 sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 359 bpf_mtap(ifp, sc->rxq[bi].m); 360 DPRINTFN(2,("received %u bytes packet\n", fl)); 361 if_percpuq_enqueue(ifp->if_percpuq, 362 sc->rxq[bi].m); 363 if (mtod(m, intptr_t) & 3) 364 m_adj(m, mtod(m, intptr_t) & 3); 365 sc->rxq[bi].m = m; 366 bus_dmamap_load(sc->sc_dmat, 367 sc->rxq[bi].m_dmamap, 368 m->m_ext.ext_buf, MCLBYTES, 369 NULL, BUS_DMA_NOWAIT); 370 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 371 MCLBYTES, BUS_DMASYNC_PREREAD); 372 sc->RDSC[bi].Info = 0; 373 sc->RDSC[bi].Addr = 374 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 375 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 376 } else { 377 /* Drop packets until we can get replacement 378 * empty mbufs for the RXDQ. 379 */ 380 if (m != NULL) 381 m_freem(m); 382 ifp->if_ierrors++; 383 } 384 sc->rxqi++; 385 } 386 } 387 388 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 389 cemac_ifstart(ifp); 390 #if 0 // reloop 391 irq = CEMAC_READ(IntStsC); 392 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 393 goto begin; 394 #endif 395 396 return (1); 397 } 398 399 400 static void 401 cemac_init(struct cemac_softc *sc) 402 { 403 bus_dma_segment_t segs; 404 int rsegs, err, i; 405 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 406 uint32_t u; 407 #if 0 408 int mdcdiv = DEFAULT_MDCDIV; 409 #endif 410 411 callout_init(&sc->cemac_tick_ch, 0); 412 413 // ok... 414 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 415 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 416 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 417 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 418 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 419 CEMAC_WRITE(ETH_CFG, 420 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 421 else 422 CEMAC_WRITE(ETH_CFG, 423 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 424 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 425 CEMAC_WRITE(GEM_DMA_CFG, 426 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 427 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 428 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 429 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 430 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 431 } 432 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 433 // (void)CEMAC_READ(ETH_ISR); 434 u = CEMAC_READ(ETH_TSR); 435 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 436 | ETH_TSR_IDLE | ETH_TSR_RLE 437 | ETH_TSR_COL|ETH_TSR_OVR))); 438 u = CEMAC_READ(ETH_RSR); 439 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 440 441 #if 0 442 if (device_cfdata(sc->sc_dev)->cf_flags) 443 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 444 #endif 445 /* set ethernet address */ 446 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 447 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 448 | (sc->sc_enaddr[0])); 449 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 450 | (sc->sc_enaddr[4])); 451 CEMAC_GEM_WRITE(SA2L, 0); 452 CEMAC_GEM_WRITE(SA2H, 0); 453 CEMAC_GEM_WRITE(SA3L, 0); 454 CEMAC_GEM_WRITE(SA3H, 0); 455 CEMAC_GEM_WRITE(SA4L, 0); 456 CEMAC_GEM_WRITE(SA4H, 0); 457 458 /* Allocate a page of memory for receive queue descriptors */ 459 sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 460 sc->rbqlen *= PAGE_SIZE; 461 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 462 463 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 464 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 465 &segs, 1, &rsegs, BUS_DMA_WAITOK); 466 if (err == 0) { 467 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 468 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 469 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 470 } 471 if (err == 0) { 472 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 473 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 474 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 475 &sc->rbqpage_dmamap); 476 } 477 if (err == 0) { 478 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 479 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 480 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 481 } 482 if (err != 0) 483 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 484 485 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 486 memset(sc->rbqpage, 0, sc->rbqlen); 487 488 /* Allocate a page of memory for transmit queue descriptors */ 489 sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 490 sc->tbqlen *= PAGE_SIZE; 491 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 492 493 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 494 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 495 &segs, 1, &rsegs, BUS_DMA_WAITOK); 496 if (err == 0) { 497 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 498 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 499 &sc->tbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 500 } 501 if (err == 0) { 502 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 503 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 504 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 505 &sc->tbqpage_dmamap); 506 } 507 if (err == 0) { 508 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 509 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 510 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 511 } 512 if (err != 0) 513 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 514 515 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 516 memset(sc->tbqpage, 0, sc->tbqlen); 517 518 /* Set up pointers to start of each queue in kernel addr space. 519 * Each descriptor queue or status queue entry uses 2 words 520 */ 521 sc->RDSC = (void *)sc->rbqpage; 522 sc->TDSC = (void *)sc->tbqpage; 523 524 /* init TX queue */ 525 for (i = 0; i < TX_QLEN; i++) { 526 sc->TDSC[i].Addr = 0; 527 sc->TDSC[i].Info = ETH_TDSC_I_USED | 528 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 529 } 530 531 /* Populate the RXQ with mbufs */ 532 sc->rxqi = 0; 533 for(i = 0; i < RX_QLEN; i++) { 534 struct mbuf *m; 535 536 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 537 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 538 if (err) { 539 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 540 } 541 MGETHDR(m, M_WAIT, MT_DATA); 542 MCLGET(m, M_WAIT); 543 sc->rxq[i].m = m; 544 if (mtod(m, intptr_t) & 3) { 545 m_adj(m, mtod(m, intptr_t) & 3); 546 } 547 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 548 m->m_ext.ext_buf, MCLBYTES, NULL, 549 BUS_DMA_WAITOK); 550 if (err) { 551 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 552 } 553 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 554 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 555 sc->RDSC[i].Info = 0; 556 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 557 MCLBYTES, BUS_DMASYNC_PREREAD); 558 } 559 560 /* prepare transmit queue */ 561 for (i = 0; i < TX_QLEN; i++) { 562 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 563 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 564 &sc->txq[i].m_dmamap); 565 if (err) 566 panic("ARGH #1"); 567 sc->txq[i].m = NULL; 568 } 569 570 /* Program each queue's start addr, cur addr, and len registers 571 * with the physical addresses. 572 */ 573 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 574 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 575 576 /* Divide HCLK by 32 for MDC clock */ 577 sc->sc_ethercom.ec_mii = &sc->sc_mii; 578 sc->sc_mii.mii_ifp = ifp; 579 sc->sc_mii.mii_readreg = cemac_mii_readreg; 580 sc->sc_mii.mii_writereg = cemac_mii_writereg; 581 sc->sc_mii.mii_statchg = cemac_statchg; 582 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, cemac_mediachange, 583 cemac_mediastatus); 584 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 585 MII_OFFSET_ANY, 0); 586 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 587 588 #if 0 589 // enable / disable interrupts 590 CEMAC_WRITE(ETH_IDR, -1); 591 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 592 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 593 // (void)CEMAC_READ(ETH_ISR); // why 594 595 // enable transmitter / receiver 596 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 597 | ETH_CTL_CSR | ETH_CTL_MPE); 598 #endif 599 /* 600 * We can support hardware checksumming. 601 */ 602 ifp->if_capabilities |= 603 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 604 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 605 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 606 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 607 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 608 609 /* 610 * We can support 802.1Q VLAN-sized frames. 611 */ 612 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 613 614 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 615 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 616 ifp->if_ioctl = cemac_ifioctl; 617 ifp->if_start = cemac_ifstart; 618 ifp->if_watchdog = cemac_ifwatchdog; 619 ifp->if_init = cemac_ifinit; 620 ifp->if_stop = cemac_ifstop; 621 ifp->if_timer = 0; 622 ifp->if_softc = sc; 623 IFQ_SET_READY(&ifp->if_snd); 624 if_attach(ifp); 625 ether_ifattach(ifp, (sc)->sc_enaddr); 626 } 627 628 static int 629 cemac_mediachange(struct ifnet *ifp) 630 { 631 if (ifp->if_flags & IFF_UP) 632 cemac_ifinit(ifp); 633 return (0); 634 } 635 636 static void 637 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 638 { 639 struct cemac_softc *sc = ifp->if_softc; 640 641 mii_pollstat(&sc->sc_mii); 642 ifmr->ifm_active = sc->sc_mii.mii_media_active; 643 ifmr->ifm_status = sc->sc_mii.mii_media_status; 644 } 645 646 647 static int 648 cemac_mii_readreg(device_t self, int phy, int reg) 649 { 650 struct cemac_softc *sc; 651 652 sc = device_private(self); 653 654 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 655 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 656 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 657 | ETH_MAN_CODE_IEEE802_3)); 658 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)); 659 660 return (CEMAC_READ(ETH_MAN) & ETH_MAN_DATA); 661 } 662 663 static void 664 cemac_mii_writereg(device_t self, int phy, int reg, int val) 665 { 666 struct cemac_softc *sc; 667 668 sc = device_private(self); 669 670 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 671 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 672 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 673 | ETH_MAN_CODE_IEEE802_3 674 | (val & ETH_MAN_DATA))); 675 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 676 } 677 678 679 static void 680 cemac_statchg(struct ifnet *ifp) 681 { 682 struct cemac_softc *sc = ifp->if_softc; 683 struct mii_data *mii = &sc->sc_mii; 684 uint32_t reg; 685 686 /* 687 * We must keep the MAC and the PHY in sync as 688 * to the status of full-duplex! 689 */ 690 reg = CEMAC_READ(ETH_CFG); 691 reg &= ~ETH_CFG_FD; 692 if (sc->sc_mii.mii_media_active & IFM_FDX) 693 reg |= ETH_CFG_FD; 694 695 reg &= ~ETH_CFG_SPD; 696 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 697 reg &= ~GEM_CFG_GEN; 698 switch (IFM_SUBTYPE(mii->mii_media_active)) { 699 case IFM_10_T: 700 break; 701 case IFM_100_TX: 702 reg |= ETH_CFG_SPD; 703 break; 704 case IFM_1000_T: 705 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 706 break; 707 default: 708 break; 709 } 710 CEMAC_WRITE(ETH_CFG, reg); 711 } 712 713 static void 714 cemac_tick(void *arg) 715 { 716 struct cemac_softc* sc = (struct cemac_softc *)arg; 717 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 718 int s; 719 720 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 721 ifp->if_collisions += CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL); 722 else 723 ifp->if_collisions += CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL); 724 725 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 726 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 727 uint32_t misses = CEMAC_READ(ETH_DRFC); 728 if (misses > 0) 729 aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 730 } 731 732 s = splnet(); 733 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 734 cemac_ifstart(ifp); 735 splx(s); 736 737 mii_tick(&sc->sc_mii); 738 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 739 } 740 741 742 static int 743 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 744 { 745 struct cemac_softc *sc = ifp->if_softc; 746 struct ifreq *ifr = (struct ifreq *)data; 747 int s, error; 748 749 s = splnet(); 750 switch(cmd) { 751 case SIOCSIFMEDIA: 752 case SIOCGIFMEDIA: 753 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 754 break; 755 default: 756 error = ether_ioctl(ifp, cmd, data); 757 if (error != ENETRESET) 758 break; 759 error = 0; 760 761 if (cmd == SIOCSIFCAP) { 762 error = (*ifp->if_init)(ifp); 763 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 764 ; 765 else if (ifp->if_flags & IFF_RUNNING) { 766 cemac_setaddr(ifp); 767 } 768 } 769 splx(s); 770 return error; 771 } 772 773 static void 774 cemac_ifstart(struct ifnet *ifp) 775 { 776 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 777 struct mbuf *m; 778 bus_dma_segment_t *segs; 779 int s, bi, err, nsegs; 780 781 s = splnet(); 782 start: 783 if (cemac_gctx(sc) == 0) { 784 /* Enable transmit-buffer-free interrupt */ 785 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 786 ifp->if_flags |= IFF_OACTIVE; 787 ifp->if_timer = 10; 788 splx(s); 789 return; 790 } 791 792 ifp->if_timer = 0; 793 794 IFQ_POLL(&ifp->if_snd, m); 795 if (m == NULL) { 796 splx(s); 797 return; 798 } 799 800 bi = (sc->txqi + sc->txqc) % TX_QLEN; 801 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 802 BUS_DMA_NOWAIT)) || 803 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 804 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 805 /* Copy entire mbuf chain to new single */ 806 struct mbuf *mn; 807 808 if (err == 0) 809 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 810 811 MGETHDR(mn, M_DONTWAIT, MT_DATA); 812 if (mn == NULL) goto stop; 813 if (m->m_pkthdr.len > MHLEN) { 814 MCLGET(mn, M_DONTWAIT); 815 if ((mn->m_flags & M_EXT) == 0) { 816 m_freem(mn); 817 goto stop; 818 } 819 } 820 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 821 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 822 IFQ_DEQUEUE(&ifp->if_snd, m); 823 m_freem(m); 824 m = mn; 825 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 826 BUS_DMA_NOWAIT); 827 } else { 828 IFQ_DEQUEUE(&ifp->if_snd, m); 829 } 830 831 bpf_mtap(ifp, m); 832 833 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 834 segs = sc->txq[bi].m_dmamap->dm_segs; 835 if (nsegs > 1) 836 panic("#### ARGH #2"); 837 838 sc->txq[bi].m = m; 839 sc->txqc++; 840 841 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 842 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 843 (unsigned)m->m_pkthdr.len)); 844 #ifdef DIAGNOSTIC 845 if (sc->txqc > TX_QLEN) 846 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 847 #endif 848 849 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 850 sc->txq[bi].m_dmamap->dm_mapsize, 851 BUS_DMASYNC_PREWRITE); 852 853 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 854 sc->TDSC[bi].Addr = segs->ds_addr; 855 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 856 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 857 858 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 859 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 860 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 861 __FUNCTION__, bi, sc->TDSC[bi].Info)); 862 863 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 864 CEMAC_WRITE(ETH_CTL, ctl); 865 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 866 } else { 867 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 868 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 869 } 870 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 871 goto start; 872 stop: 873 874 splx(s); 875 return; 876 } 877 878 static void 879 cemac_ifwatchdog(struct ifnet *ifp) 880 { 881 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 882 883 if ((ifp->if_flags & IFF_RUNNING) == 0) 884 return; 885 aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 886 CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 887 } 888 889 static int 890 cemac_ifinit(struct ifnet *ifp) 891 { 892 struct cemac_softc *sc = ifp->if_softc; 893 uint32_t dma, cfg; 894 int s = splnet(); 895 896 callout_stop(&sc->cemac_tick_ch); 897 898 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 899 900 if (ifp->if_capenable & 901 (IFCAP_CSUM_IPv4_Tx | 902 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 903 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 904 dma = CEMAC_READ(GEM_DMA_CFG); 905 dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 906 CEMAC_WRITE(GEM_DMA_CFG, dma); 907 } 908 if (ifp->if_capenable & 909 (IFCAP_CSUM_IPv4_Rx | 910 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 911 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 912 cfg = CEMAC_READ(ETH_CFG); 913 cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN; 914 CEMAC_WRITE(ETH_CFG, cfg); 915 } 916 } 917 918 // enable interrupts 919 CEMAC_WRITE(ETH_IDR, -1); 920 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 921 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 922 923 // enable transmitter / receiver 924 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 925 | ETH_CTL_CSR | ETH_CTL_MPE); 926 927 mii_mediachg(&sc->sc_mii); 928 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 929 ifp->if_flags |= IFF_RUNNING; 930 splx(s); 931 return 0; 932 } 933 934 static void 935 cemac_ifstop(struct ifnet *ifp, int disable) 936 { 937 // uint32_t u; 938 struct cemac_softc *sc = ifp->if_softc; 939 940 #if 0 941 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 942 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 943 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 944 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 945 CEMAC_WRITE(ETH_CFG, 946 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 947 else 948 CEMAC_WRITE(ETH_CFG, 949 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 950 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 951 // (void)CEMAC_READ(ETH_ISR); 952 u = CEMAC_READ(ETH_TSR); 953 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 954 | ETH_TSR_IDLE | ETH_TSR_RLE 955 | ETH_TSR_COL|ETH_TSR_OVR))); 956 u = CEMAC_READ(ETH_RSR); 957 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 958 #endif 959 callout_stop(&sc->cemac_tick_ch); 960 961 /* Down the MII. */ 962 mii_down(&sc->sc_mii); 963 964 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 965 ifp->if_timer = 0; 966 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 967 } 968 969 static void 970 cemac_setaddr(struct ifnet *ifp) 971 { 972 struct cemac_softc *sc = ifp->if_softc; 973 struct ethercom *ac = &sc->sc_ethercom; 974 struct ether_multi *enm; 975 struct ether_multistep step; 976 uint8_t ias[3][ETHER_ADDR_LEN]; 977 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 978 uint32_t ctl = CEMAC_READ(ETH_CTL); 979 uint32_t cfg = CEMAC_READ(ETH_CFG); 980 981 /* disable receiver temporarily */ 982 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 983 984 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 985 986 if (ifp->if_flags & IFF_PROMISC) { 987 cfg |= ETH_CFG_CAF; 988 } else { 989 cfg &= ~ETH_CFG_CAF; 990 } 991 992 // ETH_CFG_BIG? 993 994 ifp->if_flags &= ~IFF_ALLMULTI; 995 996 ETHER_FIRST_MULTI(step, ac, enm); 997 while (enm != NULL) { 998 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 999 /* 1000 * We must listen to a range of multicast addresses. 1001 * For now, just accept all multicasts, rather than 1002 * trying to set only those filter bits needed to match 1003 * the range. (At this time, the only use of address 1004 * ranges is for IP multicast routing, for which the 1005 * range is big enough to require all bits set.) 1006 */ 1007 cfg |= ETH_CFG_MTI; 1008 hashes[0] = 0xffffffffUL; 1009 hashes[1] = 0xffffffffUL; 1010 ifp->if_flags |= IFF_ALLMULTI; 1011 nma = 0; 1012 break; 1013 } 1014 1015 if (nma < 3) { 1016 /* We can program 3 perfect address filters for mcast */ 1017 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 1018 } else { 1019 /* 1020 * XXX: Datasheet is not very clear here, I'm not sure 1021 * if I'm doing this right. --joff 1022 */ 1023 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1024 1025 /* Just want the 6 most-significant bits. */ 1026 h = h >> 26; 1027 #if 0 1028 hashes[h / 32] |= (1 << (h % 32)); 1029 #else 1030 hashes[0] = 0xffffffffUL; 1031 hashes[1] = 0xffffffffUL; 1032 #endif 1033 cfg |= ETH_CFG_MTI; 1034 } 1035 ETHER_NEXT_MULTI(step, enm); 1036 nma++; 1037 } 1038 1039 // program... 1040 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1041 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 1042 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 1043 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 1044 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 1045 | (sc->sc_enaddr[0])); 1046 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 1047 | (sc->sc_enaddr[4])); 1048 if (nma > 0) { 1049 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1050 ias[0][0], ias[0][1], ias[0][2], 1051 ias[0][3], ias[0][4], ias[0][5])); 1052 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 1053 | (ias[0][2] << 16) | (ias[0][1] << 8) 1054 | (ias[0][0])); 1055 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 1056 | (ias[0][5])); 1057 } 1058 if (nma > 1) { 1059 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1060 ias[1][0], ias[1][1], ias[1][2], 1061 ias[1][3], ias[1][4], ias[1][5])); 1062 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1063 | (ias[1][2] << 16) | (ias[1][1] << 8) 1064 | (ias[1][0])); 1065 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1066 | (ias[1][5])); 1067 } 1068 if (nma > 2) { 1069 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1070 ias[2][0], ias[2][1], ias[2][2], 1071 ias[2][3], ias[2][4], ias[2][5])); 1072 CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1073 | (ias[2][2] << 16) | (ias[2][1] << 8) 1074 | (ias[2][0])); 1075 CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1076 | (ias[2][5])); 1077 } 1078 CEMAC_GEM_WRITE(HSH, hashes[0]); 1079 CEMAC_GEM_WRITE(HSL, hashes[1]); 1080 CEMAC_WRITE(ETH_CFG, cfg); 1081 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1082 } 1083
Indexes created Tue Sep 23 14:10:03 GMT 2025