1 /* $NetBSD: dzreg.h,v 1.4 2005/12/11 12:21:20 christos Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the author may not be used to endorse or promote products 11 * derived from this software without specific prior written permission 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25 #ifndef _DEV_DEC_DZREG_H 26 #define _DEV_DEC_DZREG_H 27 28 union w_b 29 { 30 u_short word; 31 struct { 32 u_char byte_lo; 33 u_char byte_hi; 34 } bytes; 35 }; 36 37 struct DZregs 38 { 39 volatile u_short dz_csr; /* Control/Status Register (R/W) */ 40 volatile u_short dz_rbuf; /* Receive Buffer (R only) */ 41 #define dz_lpr dz_rbuf /* Line Parameter Register (W only) */ 42 volatile union w_b u_tcr; /* Transmit Control Register (R/W) */ 43 volatile union w_b u_msr; /* Modem Status Register (R only) */ 44 #define u_tdr u_msr /* Transmit Data Register (W only) */ 45 }; 46 47 #define dz_tcr u_tcr.bytes.byte_lo /* tx enable bits */ 48 #define dz_dtr u_tcr.bytes.byte_hi /* DTR status bits */ 49 #define dz_ring u_msr.bytes.byte_lo /* RI status bits */ 50 #define dz_dcd u_msr.bytes.byte_hi /* DCD status bits */ 51 #define dz_tbuf u_tdr.bytes.byte_lo /* transmit character */ 52 #define dz_break u_tdr.bytes.byte_hi /* BREAK set/clr bits */ 53 54 typedef struct DZregs dzregs; 55 56 struct dz_regs { 57 bus_addr_t dr_csr; 58 bus_addr_t dr_rbuf; 59 #define dr_lpr dr_rbuf 60 bus_addr_t dr_dtr; 61 bus_addr_t dr_break; 62 bus_addr_t dr_tbuf; 63 bus_addr_t dr_tcr; 64 bus_addr_t dr_tcrw; 65 bus_addr_t dr_ring; 66 bus_addr_t dr_dcd; 67 68 bus_addr_t dr_firstreg; 69 bus_addr_t dr_winsize; 70 }; 71 #define DZ_UBA_CSR 0 72 #define DZ_UBA_RBUF 2 73 #define DZ_UBA_DTR 5 74 #define DZ_UBA_BREAK 7 75 #define DZ_UBA_TBUF 6 76 #define DZ_UBA_TCR 4 77 #define DZ_UBA_DCD 7 78 #define DZ_UBA_RING 6 79 80 #define DZ_UBA_FIRSTREG 0 81 #define DZ_UBA_WINSIZE 8 82 83 /* CSR bits */ 84 85 #define DZ_CSR_TX_READY 0100000 /* Transmitter Ready */ 86 #define DZ_CSR_TXIE 0040000 /* Transmitter Interrupt Enable */ 87 #define DZ_CSR_SA 0020000 /* Silo Alarm */ 88 #define DZ_CSR_SAE 0010000 /* Silo Alarm Enable */ 89 #define DZ_CSR_TX_LINE_MASK 0007400 /* Which TX line */ 90 91 #define DZ_CSR_RX_DONE 0000200 /* Receiver Done */ 92 #define DZ_CSR_RXIE 0000100 /* Receiver Interrupt Enable */ 93 #define DZ_CSR_MSE 0000040 /* Master Scan Enable */ 94 #define DZ_CSR_RESET 0000020 /* Clear (reset) Controller */ 95 #define DZ_CSR_MAINTENANCE 0000010 96 #define DZ_CSR_UNUSED 0000007 97 98 /* RBUF bits */ 99 100 #define DZ_RBUF_DATA_VALID 0100000 101 #define DZ_RBUF_OVERRUN_ERR 0040000 102 #define DZ_RBUF_FRAMING_ERR 0020000 103 #define DZ_RBUF_PARITY_ERR 0010000 104 #define DZ_RBUF_RX_LINE_MASK 0007400 105 106 /* LPR bits */ 107 108 #define DZ_LPR_UNUSED 0160000 109 #define DZ_LPR_RX_ENABLE 0010000 110 111 #define DZ_LPR_B50 0x0 112 #define DZ_LPR_B75 0x1 113 #define DZ_LPR_B110 0x2 114 #define DZ_LPR_B134 0x3 115 #define DZ_LPR_B150 0x4 116 #define DZ_LPR_B300 0x5 117 #define DZ_LPR_B600 0x6 118 #define DZ_LPR_B1200 0x7 119 #define DZ_LPR_B1800 0x8 120 #define DZ_LPR_B2000 0x9 121 #define DZ_LPR_B2400 0xA 122 #define DZ_LPR_B3600 0xB 123 #define DZ_LPR_B4800 0xC 124 #define DZ_LPR_B7200 0xD 125 #define DZ_LPR_B9600 0xE 126 #define DZ_LPR_B19200 0xF 127 128 #define DZ_LPR_OPAR 0000200 129 #define DZ_LPR_PARENB 0000100 130 #define DZ_LPR_2_STOP 0000040 131 132 #define DZ_LPR_5_BIT_CHAR 0000000 133 #define DZ_LPR_6_BIT_CHAR 0000010 134 #define DZ_LPR_7_BIT_CHAR 0000020 135 #define DZ_LPR_8_BIT_CHAR 0000030 136 137 #define DZ_LPR_CHANNEL_MASK 0000007 138 139 #endif /* _DEV_DEC_DZREG_H */ 140
Indexes created Sat Sep 20 22:09:52 GMT 2025