dzreg.h revision 1.1
1 /* $NetBSD: dzreg.h,v 1.1 2002/02/25 14:58:08 ad Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the author may not be used to endorse or promote products 11 * derived from this software without specific prior written permission 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25 union w_b 26 { 27 u_short word; 28 struct { 29 u_char byte_lo; 30 u_char byte_hi; 31 } bytes; 32 }; 33 34 struct DZregs 35 { 36 volatile u_short dz_csr; /* Control/Status Register (R/W) */ 37 volatile u_short dz_rbuf; /* Receive Buffer (R only) */ 38 #define dz_lpr dz_rbuf /* Line Parameter Register (W only) */ 39 volatile union w_b u_tcr; /* Transmit Control Register (R/W) */ 40 volatile union w_b u_msr; /* Modem Status Register (R only) */ 41 #define u_tdr u_msr /* Transmit Data Register (W only) */ 42 }; 43 44 #define dz_tcr u_tcr.bytes.byte_lo /* tx enable bits */ 45 #define dz_dtr u_tcr.bytes.byte_hi /* DTR status bits */ 46 #define dz_ring u_msr.bytes.byte_lo /* RI status bits */ 47 #define dz_dcd u_msr.bytes.byte_hi /* DCD status bits */ 48 #define dz_tbuf u_tdr.bytes.byte_lo /* transmit character */ 49 #define dz_break u_tdr.bytes.byte_hi /* BREAK set/clr bits */ 50 51 typedef struct DZregs dzregs; 52 53 #if 0 54 struct dz_regs { 55 volatile unsigned short *dr_csr; 56 volatile unsigned short *dr_rbuf; 57 #define dr_lpr dr_rbuf 58 volatile unsigned char *dr_dtr; 59 volatile unsigned char *dr_break; 60 volatile unsigned char *dr_tbuf; 61 volatile unsigned char *dr_tcr; 62 volatile unsigned short *dr_tcrw; 63 volatile unsigned char *dr_ring; 64 volatile unsigned char *dr_dcd; 65 }; 66 #else 67 struct dz_regs { 68 bus_addr_t dr_csr; 69 bus_addr_t dr_rbuf; 70 #define dr_lpr dr_rbuf 71 bus_addr_t dr_dtr; 72 bus_addr_t dr_break; 73 bus_addr_t dr_tbuf; 74 bus_addr_t dr_tcr; 75 bus_addr_t dr_tcrw; 76 bus_addr_t dr_ring; 77 bus_addr_t dr_dcd; 78 }; 79 #define DZ_UBA_CSR 0 80 #define DZ_UBA_RBUF 2 81 #define DZ_UBA_DTR 5 82 #define DZ_UBA_BREAK 7 83 #define DZ_UBA_TBUF 6 84 #define DZ_UBA_TCR 4 85 #define DZ_UBA_DCD 7 86 #define DZ_UBA_RING 6 87 88 #endif 89 90 /* CSR bits */ 91 92 #define DZ_CSR_TX_READY 0100000 /* Transmitter Ready */ 93 #define DZ_CSR_TXIE 0040000 /* Transmitter Interrupt Enable */ 94 #define DZ_CSR_SA 0020000 /* Silo Alarm */ 95 #define DZ_CSR_SAE 0010000 /* Silo Alarm Enable */ 96 #define DZ_CSR_TX_LINE_MASK 0007400 /* Which TX line */ 97 98 #define DZ_CSR_RX_DONE 0000200 /* Receiver Done */ 99 #define DZ_CSR_RXIE 0000100 /* Receiver Interrupt Enable */ 100 #define DZ_CSR_MSE 0000040 /* Master Scan Enable */ 101 #define DZ_CSR_RESET 0000020 /* Clear (reset) Controller */ 102 #define DZ_CSR_MAINTENANCE 0000010 103 #define DZ_CSR_UNUSED 0000007 104 105 /* RBUF bits */ 106 107 #define DZ_RBUF_DATA_VALID 0100000 108 #define DZ_RBUF_OVERRUN_ERR 0040000 109 #define DZ_RBUF_FRAMING_ERR 0020000 110 #define DZ_RBUF_PARITY_ERR 0010000 111 #define DZ_RBUF_RX_LINE_MASK 0007400 112 113 /* LPR bits */ 114 115 #define DZ_LPR_UNUSED 0160000 116 #define DZ_LPR_RX_ENABLE 0010000 117 118 #define DZ_LPR_B50 0x0 119 #define DZ_LPR_B75 0x1 120 #define DZ_LPR_B110 0x2 121 #define DZ_LPR_B134 0x3 122 #define DZ_LPR_B150 0x4 123 #define DZ_LPR_B300 0x5 124 #define DZ_LPR_B600 0x6 125 #define DZ_LPR_B1200 0x7 126 #define DZ_LPR_B1800 0x8 127 #define DZ_LPR_B2000 0x9 128 #define DZ_LPR_B2400 0xA 129 #define DZ_LPR_B3600 0xB 130 #define DZ_LPR_B4800 0xC 131 #define DZ_LPR_B7200 0xD 132 #define DZ_LPR_B9600 0xE 133 #define DZ_LPR_B19200 0xF 134 135 #define DZ_LPR_OPAR 0000200 136 #define DZ_LPR_PARENB 0000100 137 #define DZ_LPR_2_STOP 0000040 138 139 #define DZ_LPR_5_BIT_CHAR 0000000 140 #define DZ_LPR_6_BIT_CHAR 0000010 141 #define DZ_LPR_7_BIT_CHAR 0000020 142 #define DZ_LPR_8_BIT_CHAR 0000030 143 144 #define DZ_LPR_CHANNEL_MASK 0000007 145
Indexes created Mon Sep 29 21:09:56 GMT 2025