1 /* $NetBSD: dwc3_fdt.c,v 1.20 2022/06/12 08:04:07 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dwc3_fdt.c,v 1.20 2022/06/12 08:04:07 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usbdi.h> 41 #include <dev/usb/usbdivar.h> 42 #include <dev/usb/usb_mem.h> 43 #include <dev/usb/xhcireg.h> 44 #include <dev/usb/xhcivar.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define DWC3_GCTL 0xc110 49 #define GCTL_PRTCAP __BITS(13,12) 50 #define GCTL_PRTCAP_HOST 1 51 #define GCTL_PRTCAP_DEVICE 2 52 #define GCTL_PRTCAP_OTG 3 53 #define GCTL_CORESOFTRESET __BIT(11) 54 55 #define DWC3_GUCTL1 0xc11c 56 #define GUCTL1_TX_IPGAP_LINECHECK_DIS __BIT(28) 57 58 #define DWC3_SNPSID 0xc120 59 #define DWC3_SNPSID_REV __BITS(15,0) 60 61 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 4)) 62 #define GUSB2PHYCFG_PHYSOFTRST __BIT(31) 63 #define GUSB2PHYCFG_U2_FREECLK_EXISTS __BIT(30) 64 #define GUSB2PHYCFG_USBTRDTIM __BITS(13,10) 65 #define GUSB2PHYCFG_SUSPHY __BIT(6) 66 #define GUSB2PHYCFG_PHYIF __BIT(3) 67 #define GUSB2PHYCFG_ENBLSLPM __BIT(0) 68 69 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 4)) 70 #define GUSB3PIPECTL_PHYSOFTRST __BIT(31) 71 #define GUSB3PIPECTL_UX_EXIT_PX __BIT(27) 72 #define GUSB3PIPECTL_DEPOCHANGE __BIT(18) 73 #define GUSB3PIPECTL_SUSPHY __BIT(17) 74 75 #define DWC3_DCFG 0xc700 76 #define DCFG_SPEED __BITS(2,0) 77 #define DCFG_SPEED_HS 0 78 #define DCFG_SPEED_FS 1 79 #define DCFG_SPEED_LS 2 80 #define DCFG_SPEED_SS 4 81 #define DCFG_SPEED_SS_PLUS 5 82 83 static int dwc3_fdt_match(device_t, cfdata_t, void *); 84 static void dwc3_fdt_attach(device_t, device_t, void *); 85 86 CFATTACH_DECL2_NEW(dwc3_fdt, sizeof(struct xhci_softc), 87 dwc3_fdt_match, dwc3_fdt_attach, NULL, 88 xhci_activate, NULL, xhci_childdet); 89 90 #define RD4(sc, reg) \ 91 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 92 #define WR4(sc, reg, val) \ 93 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 94 #define SET4(sc, reg, mask) \ 95 WR4((sc), (reg), RD4((sc), (reg)) | (mask)) 96 #define CLR4(sc, reg, mask) \ 97 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask)) 98 99 static void 100 dwc3_fdt_soft_reset(struct xhci_softc *sc) 101 { 102 /* Put core in reset */ 103 SET4(sc, DWC3_GCTL, GCTL_CORESOFTRESET); 104 105 /* Assert USB3 PHY reset */ 106 SET4(sc, DWC3_GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST); 107 108 /* Assert USB2 PHY reset */ 109 SET4(sc, DWC3_GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST); 110 111 delay(100000); 112 113 /* Clear USB3 PHY reset */ 114 CLR4(sc, DWC3_GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST); 115 116 /* Clear USB2 PHY reset */ 117 CLR4(sc, DWC3_GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST); 118 119 delay(100000); 120 121 /* Take core out of reset */ 122 CLR4(sc, DWC3_GCTL, GCTL_CORESOFTRESET); 123 } 124 125 static void 126 dwc3_fdt_enable_phy(struct xhci_softc *sc, const int phandle, u_int rev) 127 { 128 const char *max_speed, *phy_type; 129 u_int phyif_utmi_bits; 130 uint32_t val; 131 132 val = RD4(sc, DWC3_GUSB2PHYCFG(0)); 133 if (of_getprop_uint32(phandle, "snps,phyif-utmi-bits", &phyif_utmi_bits) != 0) { 134 phy_type = fdtbus_get_string(phandle, "phy_type"); 135 if (phy_type && strcmp(phy_type, "utmi_wide") == 0) 136 phyif_utmi_bits = 16; 137 else if (phy_type && strcmp(phy_type, "utmi") == 0) 138 phyif_utmi_bits = 8; 139 else 140 phyif_utmi_bits = 0; 141 } 142 if (phyif_utmi_bits == 16) { 143 val |= GUSB2PHYCFG_PHYIF; 144 val &= ~GUSB2PHYCFG_USBTRDTIM; 145 val |= __SHIFTIN(5, GUSB2PHYCFG_USBTRDTIM); 146 } else if (phyif_utmi_bits == 8) { 147 val &= ~GUSB2PHYCFG_PHYIF; 148 val &= ~GUSB2PHYCFG_USBTRDTIM; 149 val |= __SHIFTIN(9, GUSB2PHYCFG_USBTRDTIM); 150 } 151 if (of_hasprop(phandle, "snps,dis-enblslpm-quirk") || 152 of_hasprop(phandle, "snps,dis_enblslpm_quirk")) 153 val &= ~GUSB2PHYCFG_ENBLSLPM; 154 if (of_hasprop(phandle, "snps,dis-u2-freeclk-exists-quirk")) 155 val &= ~GUSB2PHYCFG_U2_FREECLK_EXISTS; 156 if (of_hasprop(phandle, "snps,dis_u2_susphy_quirk")) 157 val &= ~GUSB2PHYCFG_SUSPHY; 158 WR4(sc, DWC3_GUSB2PHYCFG(0), val); 159 160 val = RD4(sc, DWC3_GUSB3PIPECTL(0)); 161 val &= ~GUSB3PIPECTL_UX_EXIT_PX; 162 if (of_hasprop(phandle, "snps,dis_u3_susphy_quirk")) 163 val &= ~GUSB3PIPECTL_SUSPHY; 164 if (of_hasprop(phandle, "snps,dis-del-phy-power-chg-quirk")) 165 val &= ~GUSB3PIPECTL_DEPOCHANGE; 166 WR4(sc, DWC3_GUSB3PIPECTL(0), val); 167 168 if (rev >= 0x250a) { 169 val = RD4(sc, DWC3_GUCTL1); 170 if (of_hasprop(phandle, "snps,dis-tx-ipgap-linecheck-quirk")) 171 val |= GUCTL1_TX_IPGAP_LINECHECK_DIS; 172 WR4(sc, DWC3_GUCTL1, val); 173 } 174 175 max_speed = fdtbus_get_string(phandle, "maximum-speed"); 176 if (max_speed == NULL) 177 max_speed = "super-speed"; 178 179 val = RD4(sc, DWC3_DCFG); 180 val &= ~DCFG_SPEED; 181 if (strcmp(max_speed, "low-speed") == 0) 182 val |= __SHIFTIN(DCFG_SPEED_LS, DCFG_SPEED); 183 else if (strcmp(max_speed, "full-speed") == 0) 184 val |= __SHIFTIN(DCFG_SPEED_FS, DCFG_SPEED); 185 else if (strcmp(max_speed, "high-speed") == 0) 186 val |= __SHIFTIN(DCFG_SPEED_HS, DCFG_SPEED); 187 else if (strcmp(max_speed, "super-speed") == 0) 188 val |= __SHIFTIN(DCFG_SPEED_SS, DCFG_SPEED); 189 else 190 val |= __SHIFTIN(DCFG_SPEED_SS, DCFG_SPEED); /* default to super speed */ 191 WR4(sc, DWC3_DCFG, val); 192 } 193 194 static void 195 dwc3_fdt_set_mode(struct xhci_softc *sc, u_int mode) 196 { 197 uint32_t val; 198 199 val = RD4(sc, DWC3_GCTL); 200 val &= ~GCTL_PRTCAP; 201 val |= __SHIFTIN(mode, GCTL_PRTCAP); 202 WR4(sc, DWC3_GCTL, val); 203 } 204 205 static const struct device_compatible_entry compat_data[] = { 206 { .compat = "allwinner,sun50i-h6-dwc3" }, 207 { .compat = "amlogic,meson-gxl-dwc3" }, 208 { .compat = "fsl,imx8mq-dwc3" }, 209 { .compat = "rockchip,rk3328-dwc3" }, 210 { .compat = "rockchip,rk3399-dwc3" }, 211 { .compat = "samsung,exynos5250-dwusb3" }, 212 { .compat = "snps,dwc3" }, 213 DEVICE_COMPAT_EOL 214 }; 215 216 static const struct device_compatible_entry compat_data_dwc3[] = { 217 { .compat = "snps,dwc3" }, 218 DEVICE_COMPAT_EOL 219 }; 220 221 static int 222 dwc3_fdt_match(device_t parent, cfdata_t cf, void *aux) 223 { 224 struct fdt_attach_args * const faa = aux; 225 226 return of_compatible_match(faa->faa_phandle, compat_data); 227 } 228 229 static void 230 dwc3_fdt_attach(device_t parent, device_t self, void *aux) 231 { 232 struct xhci_softc * const sc = device_private(self); 233 struct fdt_attach_args * const faa = aux; 234 const int phandle = faa->faa_phandle; 235 struct fdtbus_reset *rst; 236 struct fdtbus_phy *phy; 237 struct clk *clk; 238 char intrstr[128]; 239 bus_addr_t addr; 240 bus_size_t size; 241 int error, dwc3_phandle; 242 void *ih; 243 u_int n; 244 245 /* Find dwc3 sub-node */ 246 if (of_compatible_lookup(phandle, compat_data_dwc3) == NULL) { 247 dwc3_phandle = of_find_bycompat(phandle, "snps,dwc3"); 248 if (dwc3_phandle <= 0) { 249 dwc3_phandle = of_find_firstchild_byname(phandle, "dwc3"); 250 } 251 } else { 252 dwc3_phandle = phandle; 253 } 254 if (dwc3_phandle <= 0) { 255 aprint_error(": couldn't find dwc3 child node\n"); 256 return; 257 } 258 259 /* 260 * Only host mode is supported, but this includes otg devices 261 * that have 'usb-role-switch' and 'role-switch-default-mode' of 262 * 'host' 263 */ 264 const char *dr_mode = fdtbus_get_string(dwc3_phandle, "dr_mode"); 265 if (dr_mode == NULL || strcmp(dr_mode, "otg") == 0) { 266 bool ok = false; 267 if (of_hasprop(dwc3_phandle, "usb-role-switch")) { 268 const char *rsdm = fdtbus_get_string(dwc3_phandle, 269 "role-switch-default-mode"); 270 if (rsdm != NULL && strcmp(rsdm, "host") == 0) 271 ok = true; 272 273 if (!ok) { 274 aprint_error(": host is not default mode\n"); 275 return; 276 } 277 } 278 if (!ok) { 279 aprint_error(": cannot switch 'otg' mode to host\n"); 280 return; 281 } 282 } else if (strcmp(dr_mode, "host") != 0) { 283 aprint_error(": '%s' not supported\n", dr_mode); 284 return; 285 } 286 287 /* Enable clocks */ 288 fdtbus_clock_assign(phandle); 289 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 290 if (clk_enable(clk) != 0) { 291 aprint_error(": couldn't enable clock #%d\n", n); 292 return; 293 } 294 /* De-assert resets */ 295 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 296 if (fdtbus_reset_deassert(rst) != 0) { 297 aprint_error(": couldn't de-assert reset #%d\n", n); 298 return; 299 } 300 301 /* Get resources */ 302 if (fdtbus_get_reg(dwc3_phandle, 0, &addr, &size) != 0) { 303 aprint_error(": couldn't get registers\n"); 304 return; 305 } 306 307 sc->sc_dev = self; 308 sc->sc_bus.ub_hcpriv = sc; 309 sc->sc_bus.ub_dmatag = faa->faa_dmat; 310 sc->sc_ios = size; 311 sc->sc_iot = faa->faa_bst; 312 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 313 aprint_error(": couldn't map registers\n"); 314 return; 315 } 316 317 aprint_naive("\n"); 318 aprint_normal(": DesignWare USB3 XHCI"); 319 const uint32_t snpsid = RD4(sc, DWC3_SNPSID); 320 const u_int rev = __SHIFTOUT(snpsid, DWC3_SNPSID_REV); 321 aprint_normal(" (rev. %d.%03x)\n", rev >> 12, rev & 0xfff); 322 323 /* Enable PHY devices */ 324 for (n = 0; (phy = fdtbus_phy_get_index(dwc3_phandle, n)) != NULL; n++) { 325 if (fdtbus_phy_enable(phy, true) != 0) 326 aprint_error_dev(self, "couldn't enable phy #%d\n", n); 327 } 328 329 dwc3_fdt_soft_reset(sc); 330 dwc3_fdt_enable_phy(sc, dwc3_phandle, rev); 331 dwc3_fdt_set_mode(sc, GCTL_PRTCAP_HOST); 332 333 if (!fdtbus_intr_str(dwc3_phandle, 0, intrstr, sizeof(intrstr))) { 334 aprint_error_dev(self, "failed to decode interrupt\n"); 335 return; 336 } 337 338 ih = fdtbus_intr_establish_xname(dwc3_phandle, 0, IPL_USB, 339 FDT_INTR_MPSAFE, xhci_intr, sc, device_xname(self)); 340 if (ih == NULL) { 341 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 342 intrstr); 343 return; 344 } 345 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 346 347 sc->sc_bus.ub_revision = USBREV_3_0; 348 error = xhci_init(sc); 349 if (error) { 350 aprint_error_dev(self, "init failed, error = %d\n", error); 351 return; 352 } 353 354 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint, CFARGS_NONE); 355 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint, 356 CFARGS_NONE); 357 } 358
Indexes created Sun Sep 21 20:09:37 GMT 2025