dwc3_fdt.c revision 1.1
1 /* $NetBSD: dwc3_fdt.c,v 1.1 2018/05/01 23:59:15 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dwc3_fdt.c,v 1.1 2018/05/01 23:59:15 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usbdi.h> 41 #include <dev/usb/usbdivar.h> 42 #include <dev/usb/usb_mem.h> 43 #include <dev/usb/xhcireg.h> 44 #include <dev/usb/xhcivar.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define DWC3_GCTL 0xc110 49 #define GCTL_PRTCAP __BITS(13,12) 50 #define GCTL_PRTCAP_HOST 1 51 #define GCTL_PRTCAP_DEVICE 2 52 #define GCTL_PRTCAP_OTG 3 53 #define GCTL_CORESOFTRESET __BIT(11) 54 55 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 4)) 56 #define GUSB2PHYCFG_PHYSOFTRST __BIT(31) 57 58 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 4)) 59 #define GUSB3PIPECTL_PHYSOFTRST __BIT(31) 60 61 static int dwc3_fdt_match(device_t, cfdata_t, void *); 62 static void dwc3_fdt_attach(device_t, device_t, void *); 63 64 CFATTACH_DECL2_NEW(dwc3_fdt, sizeof(struct xhci_softc), 65 dwc3_fdt_match, dwc3_fdt_attach, NULL, 66 xhci_activate, NULL, xhci_childdet); 67 68 #define RD4(sc, reg) \ 69 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 70 #define WR4(sc, reg, val) \ 71 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 72 #define SET4(sc, reg, mask) \ 73 WR4((sc), (reg), RD4((sc), (reg)) | (mask)) 74 #define CLR4(sc, reg, mask) \ 75 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask)) 76 77 static void 78 dwc3_fdt_soft_reset(struct xhci_softc *sc) 79 { 80 /* Put core in reset */ 81 SET4(sc, DWC3_GCTL, GCTL_CORESOFTRESET); 82 83 /* Assert USB3 PHY reset */ 84 SET4(sc, DWC3_GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST); 85 86 /* Assert USB2 PHY reset */ 87 SET4(sc, DWC3_GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST); 88 89 delay(100000); 90 91 /* Clear USB3 PHY reset */ 92 CLR4(sc, DWC3_GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST); 93 94 /* Clear USB2 PHY reset */ 95 CLR4(sc, DWC3_GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST); 96 97 delay(100000); 98 99 /* Take core out of reset */ 100 CLR4(sc, DWC3_GCTL, GCTL_CORESOFTRESET); 101 } 102 103 static void 104 dwc3_fdt_set_mode(struct xhci_softc *sc, u_int mode) 105 { 106 uint32_t val; 107 108 val = RD4(sc, DWC3_GCTL); 109 val &= ~GCTL_PRTCAP; 110 val |= __SHIFTIN(mode, GCTL_PRTCAP); 111 WR4(sc, DWC3_GCTL, val); 112 } 113 114 static int 115 dwc3_fdt_match(device_t parent, cfdata_t cf, void *aux) 116 { 117 const char * const compatible[] = { 118 "allwinner,sun50i-h6-dwc3", 119 NULL 120 }; 121 struct fdt_attach_args * const faa = aux; 122 123 return of_match_compatible(faa->faa_phandle, compatible); 124 } 125 126 static void 127 dwc3_fdt_attach(device_t parent, device_t self, void *aux) 128 { 129 struct xhci_softc * const sc = device_private(self); 130 struct fdt_attach_args * const faa = aux; 131 const int phandle = faa->faa_phandle; 132 struct fdtbus_reset *rst; 133 struct fdtbus_phy *phy; 134 struct clk *clk; 135 char intrstr[128]; 136 bus_addr_t addr; 137 bus_size_t size; 138 int error; 139 void *ih; 140 u_int n; 141 142 /* Find dwc3 sub-node */ 143 const int dwc3_phandle = of_find_firstchild_byname(phandle, "dwc3"); 144 if (dwc3_phandle <= 0) { 145 aprint_error(": couldn't find dwc3 child node\n"); 146 return; 147 } 148 149 /* Only host mode is supported */ 150 const char *dr_mode = fdtbus_get_string(dwc3_phandle, "dr_mode"); 151 if (dr_mode == NULL || strcmp(dr_mode, "host") != 0) { 152 aprint_error(": '%s' not supported\n", dr_mode); 153 return; 154 } 155 156 /* Enable clocks */ 157 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 158 if (clk_enable(clk) != 0) { 159 aprint_error(": couldn't enable clock #%d\n", n); 160 return; 161 } 162 /* De-assert resets */ 163 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 164 if (fdtbus_reset_deassert(rst) != 0) { 165 aprint_error(": couldn't de-assert reset #%d\n", n); 166 return; 167 } 168 169 /* Enable phy */ 170 phy = fdtbus_phy_get(dwc3_phandle, "usb3-phy"); 171 if (!phy || fdtbus_phy_enable(phy, true) != 0) { 172 aprint_error(": couldn't enable phy\n"); 173 return; 174 } 175 176 /* Get resources */ 177 if (fdtbus_get_reg(dwc3_phandle, 0, &addr, &size) != 0) { 178 aprint_error(": couldn't get registers\n"); 179 return; 180 } 181 182 sc->sc_dev = self; 183 sc->sc_bus.ub_hcpriv = sc; 184 sc->sc_bus.ub_dmatag = faa->faa_dmat; 185 sc->sc_iot = faa->faa_bst; 186 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 187 aprint_error(": couldn't map registers\n"); 188 return; 189 } 190 191 aprint_naive("\n"); 192 aprint_normal(": DesignWare USB3 XHCI\n"); 193 194 dwc3_fdt_soft_reset(sc); 195 dwc3_fdt_set_mode(sc, GCTL_PRTCAP_HOST); 196 197 if (!fdtbus_intr_str(dwc3_phandle, 0, intrstr, sizeof(intrstr))) { 198 aprint_error_dev(self, "failed to decode interrupt\n"); 199 return; 200 } 201 202 ih = fdtbus_intr_establish(dwc3_phandle, 0, IPL_USB, FDT_INTR_MPSAFE, 203 xhci_intr, sc); 204 if (ih == NULL) { 205 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 206 intrstr); 207 return; 208 } 209 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 210 211 error = xhci_init(sc); 212 if (error) { 213 aprint_error_dev(self, "init failed, error = %d\n", error); 214 return; 215 } 216 217 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 218 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 219 } 220
Indexes created Wed Sep 24 22:09:59 GMT 2025