dwc3_fdt.c revision 1.1.2.4
1 /* $NetBSD: dwc3_fdt.c,v 1.1.2.4 2018/07/28 04:37:44 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dwc3_fdt.c,v 1.1.2.4 2018/07/28 04:37:44 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usbdi.h> 41 #include <dev/usb/usbdivar.h> 42 #include <dev/usb/usb_mem.h> 43 #include <dev/usb/xhcireg.h> 44 #include <dev/usb/xhcivar.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define DWC3_GCTL 0xc110 49 #define GCTL_PRTCAP __BITS(13,12) 50 #define GCTL_PRTCAP_HOST 1 51 #define GCTL_PRTCAP_DEVICE 2 52 #define GCTL_PRTCAP_OTG 3 53 #define GCTL_CORESOFTRESET __BIT(11) 54 55 #define DWC3_SNPSID 0xc120 56 #define DWC3_SNPSID_REV __BITS(15,0) 57 58 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 4)) 59 #define GUSB2PHYCFG_PHYSOFTRST __BIT(31) 60 #define GUSB2PHYCFG_U2_FREECLK_EXISTS __BIT(30) 61 #define GUSB2PHYCFG_USBTRDTIM __BITS(13,10) 62 #define GUSB2PHYCFG_SUSPHY __BIT(6) 63 #define GUSB2PHYCFG_PHYIF __BIT(3) 64 #define GUSB2PHYCFG_ENBLSLPM __BIT(0) 65 66 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 4)) 67 #define GUSB3PIPECTL_PHYSOFTRST __BIT(31) 68 #define GUSB3PIPECTL_UX_EXIT_PX __BIT(27) 69 #define GUSB3PIPECTL_SUSPHY __BIT(17) 70 71 #define DWC3_DCFG 0xc700 72 #define DCFG_SPEED __BITS(2,0) 73 #define DCFG_SPEED_HS 0 74 #define DCFG_SPEED_FS 1 75 #define DCFG_SPEED_LS 2 76 #define DCFG_SPEED_SS 4 77 #define DCFG_SPEED_SS_PLUS 5 78 79 static int dwc3_fdt_match(device_t, cfdata_t, void *); 80 static void dwc3_fdt_attach(device_t, device_t, void *); 81 82 CFATTACH_DECL2_NEW(dwc3_fdt, sizeof(struct xhci_softc), 83 dwc3_fdt_match, dwc3_fdt_attach, NULL, 84 xhci_activate, NULL, xhci_childdet); 85 86 #define RD4(sc, reg) \ 87 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 88 #define WR4(sc, reg, val) \ 89 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 90 #define SET4(sc, reg, mask) \ 91 WR4((sc), (reg), RD4((sc), (reg)) | (mask)) 92 #define CLR4(sc, reg, mask) \ 93 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask)) 94 95 static void 96 dwc3_fdt_soft_reset(struct xhci_softc *sc) 97 { 98 /* Put core in reset */ 99 SET4(sc, DWC3_GCTL, GCTL_CORESOFTRESET); 100 101 /* Assert USB3 PHY reset */ 102 SET4(sc, DWC3_GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST); 103 104 /* Assert USB2 PHY reset */ 105 SET4(sc, DWC3_GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST); 106 107 delay(100000); 108 109 /* Clear USB3 PHY reset */ 110 CLR4(sc, DWC3_GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST); 111 112 /* Clear USB2 PHY reset */ 113 CLR4(sc, DWC3_GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST); 114 115 delay(100000); 116 117 /* Take core out of reset */ 118 CLR4(sc, DWC3_GCTL, GCTL_CORESOFTRESET); 119 } 120 121 static void 122 dwc3_fdt_enable_phy(struct xhci_softc *sc, const int phandle) 123 { 124 const char *max_speed; 125 u_int phyif_utmi_bits; 126 uint32_t val; 127 128 val = RD4(sc, DWC3_GUSB2PHYCFG(0)); 129 if (of_getprop_uint32(phandle, "snps,phyif-utmi-bits", &phyif_utmi_bits) == 0) { 130 if (phyif_utmi_bits == 16) { 131 val |= GUSB2PHYCFG_PHYIF; 132 val &= ~GUSB2PHYCFG_USBTRDTIM; 133 val |= __SHIFTIN(5, GUSB2PHYCFG_USBTRDTIM); 134 } else if (phyif_utmi_bits == 8) { 135 val &= ~GUSB2PHYCFG_PHYIF; 136 val &= ~GUSB2PHYCFG_USBTRDTIM; 137 val |= __SHIFTIN(9, GUSB2PHYCFG_USBTRDTIM); 138 } 139 } 140 if (of_hasprop(phandle, "snps,dis-enblslpm-quirk")) 141 val &= ~GUSB2PHYCFG_ENBLSLPM; 142 if (of_hasprop(phandle, "snps,dis-u2-freeclk-exists-quirk")) 143 val &= ~GUSB2PHYCFG_U2_FREECLK_EXISTS; 144 if (of_hasprop(phandle, "snps,dis_u2_susphy_quirk")) 145 val &= ~GUSB2PHYCFG_SUSPHY; 146 WR4(sc, DWC3_GUSB2PHYCFG(0), val); 147 148 val = RD4(sc, DWC3_GUSB3PIPECTL(0)); 149 val &= ~GUSB3PIPECTL_UX_EXIT_PX; 150 if (of_hasprop(phandle, "snps,dis_u3_susphy_quirk")) 151 val &= ~GUSB3PIPECTL_SUSPHY; 152 WR4(sc, DWC3_GUSB3PIPECTL(0), val); 153 154 max_speed = fdtbus_get_string(phandle, "maximum-speed"); 155 if (max_speed == NULL) 156 max_speed = "super-speed"; 157 158 val = RD4(sc, DWC3_DCFG); 159 val &= ~DCFG_SPEED; 160 if (strcmp(max_speed, "low-speed") == 0) 161 val |= __SHIFTIN(DCFG_SPEED_LS, DCFG_SPEED); 162 else if (strcmp(max_speed, "full-speed") == 0) 163 val |= __SHIFTIN(DCFG_SPEED_FS, DCFG_SPEED); 164 else if (strcmp(max_speed, "high-speed") == 0) 165 val |= __SHIFTIN(DCFG_SPEED_HS, DCFG_SPEED); 166 else if (strcmp(max_speed, "super-speed") == 0) 167 val |= __SHIFTIN(DCFG_SPEED_SS, DCFG_SPEED); 168 else 169 val |= __SHIFTIN(DCFG_SPEED_SS, DCFG_SPEED); /* default to super speed */ 170 WR4(sc, DWC3_DCFG, val); 171 } 172 173 static void 174 dwc3_fdt_set_mode(struct xhci_softc *sc, u_int mode) 175 { 176 uint32_t val; 177 178 val = RD4(sc, DWC3_GCTL); 179 val &= ~GCTL_PRTCAP; 180 val |= __SHIFTIN(mode, GCTL_PRTCAP); 181 WR4(sc, DWC3_GCTL, val); 182 } 183 184 static int 185 dwc3_fdt_match(device_t parent, cfdata_t cf, void *aux) 186 { 187 const char * const compatible[] = { 188 "allwinner,sun50i-h6-dwc3", 189 "rockchip,rk3328-dwc3", 190 "samsung,exynos5250-dwusb3", 191 NULL 192 }; 193 struct fdt_attach_args * const faa = aux; 194 195 return of_match_compatible(faa->faa_phandle, compatible); 196 } 197 198 static void 199 dwc3_fdt_attach(device_t parent, device_t self, void *aux) 200 { 201 struct xhci_softc * const sc = device_private(self); 202 struct fdt_attach_args * const faa = aux; 203 const int phandle = faa->faa_phandle; 204 struct fdtbus_reset *rst; 205 struct fdtbus_phy *phy; 206 struct clk *clk; 207 char intrstr[128]; 208 bus_addr_t addr; 209 bus_size_t size; 210 int error; 211 void *ih; 212 u_int n; 213 214 /* Find dwc3 sub-node */ 215 const int dwc3_phandle = of_find_firstchild_byname(phandle, "dwc3"); 216 if (dwc3_phandle <= 0) { 217 aprint_error(": couldn't find dwc3 child node\n"); 218 return; 219 } 220 221 /* Only host mode is supported */ 222 const char *dr_mode = fdtbus_get_string(dwc3_phandle, "dr_mode"); 223 if (dr_mode == NULL || strcmp(dr_mode, "host") != 0) { 224 aprint_error(": '%s' not supported\n", dr_mode); 225 return; 226 } 227 228 /* Enable clocks */ 229 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 230 if (clk_enable(clk) != 0) { 231 aprint_error(": couldn't enable clock #%d\n", n); 232 return; 233 } 234 /* De-assert resets */ 235 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 236 if (fdtbus_reset_deassert(rst) != 0) { 237 aprint_error(": couldn't de-assert reset #%d\n", n); 238 return; 239 } 240 241 /* Get resources */ 242 if (fdtbus_get_reg(dwc3_phandle, 0, &addr, &size) != 0) { 243 aprint_error(": couldn't get registers\n"); 244 return; 245 } 246 247 sc->sc_dev = self; 248 sc->sc_bus.ub_hcpriv = sc; 249 sc->sc_bus.ub_dmatag = faa->faa_dmat; 250 sc->sc_iot = faa->faa_bst; 251 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 252 aprint_error(": couldn't map registers\n"); 253 return; 254 } 255 256 aprint_naive("\n"); 257 aprint_normal(": DesignWare USB3 XHCI"); 258 const uint32_t snpsid = RD4(sc, DWC3_SNPSID); 259 const u_int rev = __SHIFTOUT(snpsid, DWC3_SNPSID_REV); 260 aprint_normal(" (rev. %d.%03x)\n", rev >> 12, rev & 0xfff); 261 262 /* Enable PHY devices */ 263 phy = fdtbus_phy_get(dwc3_phandle, "usb2-phy"); 264 if (phy && fdtbus_phy_enable(phy, true) != 0) 265 aprint_error_dev(self, "couldn't enable usb2-phy\n"); 266 phy = fdtbus_phy_get(dwc3_phandle, "usb3-phy"); 267 if (phy && fdtbus_phy_enable(phy, true) != 0) 268 aprint_error_dev(self, "couldn't enable usb3-phy\n"); 269 270 dwc3_fdt_soft_reset(sc); 271 dwc3_fdt_enable_phy(sc, phandle); 272 dwc3_fdt_set_mode(sc, GCTL_PRTCAP_HOST); 273 274 if (!fdtbus_intr_str(dwc3_phandle, 0, intrstr, sizeof(intrstr))) { 275 aprint_error_dev(self, "failed to decode interrupt\n"); 276 return; 277 } 278 279 ih = fdtbus_intr_establish(dwc3_phandle, 0, IPL_USB, FDT_INTR_MPSAFE, 280 xhci_intr, sc); 281 if (ih == NULL) { 282 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 283 intrstr); 284 return; 285 } 286 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 287 288 sc->sc_bus.ub_revision = USBREV_3_0; 289 error = xhci_init(sc); 290 if (error) { 291 aprint_error_dev(self, "init failed, error = %d\n", error); 292 return; 293 } 294 295 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 296 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 297 } 298
Indexes created Tue Sep 30 17:09:57 GMT 2025