1 /* $NetBSD: pcihost_fdt.c,v 1.1 2026/09/20 11:00:34 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.1 2026/09/20 11:00:34 skrll Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/lwp.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/systm.h> 43 44 #include <machine/cpu.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pciconf.h> 49 50 #include <dev/fdt/fdtvar.h> 51 #include <dev/fdt/pcihost_fdtvar.h> 52 53 #define PCIHOST_DEFAULT_BUS_MIN 0 54 #define PCIHOST_DEFAULT_BUS_MAX 255 55 56 #define PCIHOST_CACHELINE_SIZE MD_PCI_CACHELINE_SIZE 57 58 int pcihost_segment = 0; 59 60 static int pcihost_match(device_t, cfdata_t, void *); 61 static void pcihost_attach(device_t, device_t, void *); 62 63 static int pcihost_config(struct pcihost_softc *); 64 65 static void pcihost_attach_hook(device_t, device_t, 66 struct pcibus_attach_args *); 67 static int pcihost_bus_maxdevs(void *, int); 68 static pcitag_t pcihost_make_tag(void *, int, int, int); 69 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 70 static u_int pcihost_get_segment(void *); 71 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 72 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 73 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 74 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 75 76 static int pcihost_intr_map(const struct pci_attach_args *, 77 pci_intr_handle_t *); 78 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 79 char *, size_t); 80 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 81 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 82 uint64_t); 83 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 84 int, int (*)(void *), void *, 85 const char *); 86 static void pcihost_intr_disestablish(void *, void *); 87 88 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 89 int, bus_space_handle_t *); 90 91 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 92 pcihost_match, pcihost_attach, NULL, NULL); 93 94 static const struct device_compatible_entry compat_data[] = { 95 { .compat = "pci-host-cam-generic", .value = PCIHOST_CAM }, 96 { .compat = "pci-host-ecam-generic", .value = PCIHOST_ECAM }, 97 DEVICE_COMPAT_EOL 98 }; 99 100 #ifdef __HAVE_PCI_MSI_MSIX 101 struct pcihost_msi_handler { 102 LIST_ENTRY(pcihost_msi_handler) pmh_next; 103 void *pmh_ih; 104 }; 105 #endif 106 107 static int 108 pcihost_match(device_t parent, cfdata_t cf, void *aux) 109 { 110 struct fdt_attach_args * const faa = aux; 111 112 return of_compatible_match(faa->faa_phandle, compat_data); 113 } 114 115 static void 116 pcihost_attach(device_t parent, device_t self, void *aux) 117 { 118 struct pcihost_softc * const sc = device_private(self); 119 struct fdt_attach_args * const faa = aux; 120 bus_addr_t cs_addr; 121 bus_size_t cs_size; 122 int error; 123 124 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 125 aprint_error(": couldn't get registers\n"); 126 return; 127 } 128 129 sc->sc_dev = self; 130 sc->sc_dmat = faa->faa_dmat; 131 sc->sc_bst = faa->faa_bst; 132 sc->sc_pci_bst = faa->faa_bst; 133 sc->sc_phandle = faa->faa_phandle; 134 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 135 MD_PCI_CONFIG_MAP_FLAGS, &sc->sc_bsh); 136 if (error) { 137 aprint_error(": couldn't map registers: %d\n", error); 138 return; 139 } 140 sc->sc_type = of_compatible_lookup(sc->sc_phandle, compat_data)->value; 141 142 #ifdef __HAVE_PCI_MSI_MSIX 143 if (sc->sc_type == PCIHOST_ECAM) { 144 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 145 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 146 } 147 #endif 148 149 aprint_naive("\n"); 150 aprint_normal(": Generic PCI host controller\n"); 151 152 pcihost_init(&sc->sc_pc, sc); 153 pcihost_init2(sc); 154 } 155 156 void 157 pcihost_init2(struct pcihost_softc *sc) 158 { 159 struct pcibus_attach_args pba; 160 const u_int *data; 161 int len; 162 163 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 164 if (len != 8) { 165 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 166 return; 167 } 168 sc->sc_bus_min = be32toh(data[0]); 169 sc->sc_bus_max = be32toh(data[1]); 170 } else { 171 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 172 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 173 } 174 175 /* 176 * Assign a fixed PCI segment ("domain") number. If the property is not 177 * present, assign one. The binding spec says if this property is used to 178 * assign static segment numbers, all host bridges should have segments 179 * astatic assigned to prevent overlaps. 180 */ 181 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 182 sc->sc_seg = pcihost_segment++; 183 184 #ifdef __HAVE_PCI_MSI_MSIX 185 mutex_init(&sc->sc_msi_handlers_mutex, MUTEX_DEFAULT, IPL_NONE); 186 187 /* Rely on softc being zero initialised. */ 188 KASSERT(LIST_EMPTY(&sc->sc_msi_handlers)); 189 #endif 190 191 if (pcihost_config(sc) != 0) 192 return; 193 194 memset(&pba, 0, sizeof(pba)); 195 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 196 PCI_FLAGS_MRM_OKAY | 197 PCI_FLAGS_MWI_OKAY | 198 sc->sc_pci_flags; 199 pba.pba_iot = &sc->sc_io.bst; 200 pba.pba_memt = &sc->sc_mem.bst; 201 pba.pba_dmat = sc->sc_dmat; 202 #ifdef _PCI_HAVE_DMA64 203 pba.pba_dmat64 = sc->sc_dmat; 204 #endif 205 pba.pba_pc = &sc->sc_pc; 206 pba.pba_bus = sc->sc_bus_min; 207 208 config_found(sc->sc_dev, &pba, pcibusprint, 209 CFARGS(.devhandle = device_handle(sc->sc_dev))); 210 } 211 212 void 213 pcihost_init(pci_chipset_tag_t pc, void *priv) 214 { 215 pc->pc_conf_v = priv; 216 pc->pc_attach_hook = pcihost_attach_hook; 217 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 218 pc->pc_make_tag = pcihost_make_tag; 219 pc->pc_decompose_tag = pcihost_decompose_tag; 220 pc->pc_get_segment = pcihost_get_segment; 221 pc->pc_conf_read = pcihost_conf_read; 222 pc->pc_conf_write = pcihost_conf_write; 223 pc->pc_conf_hook = pcihost_conf_hook; 224 pc->pc_conf_interrupt = pcihost_conf_interrupt; 225 226 pc->pc_intr_v = priv; 227 pc->pc_intr_map = pcihost_intr_map; 228 pc->pc_intr_string = pcihost_intr_string; 229 pc->pc_intr_evcnt = pcihost_intr_evcnt; 230 pc->pc_intr_setattr = pcihost_intr_setattr; 231 pc->pc_intr_establish = pcihost_intr_establish; 232 pc->pc_intr_disestablish = pcihost_intr_disestablish; 233 } 234 235 static int 236 pcihost_config(struct pcihost_softc *sc) 237 { 238 const u_int *ranges; 239 u_int probe_only; 240 int error, len, type; 241 bool swap; 242 243 struct pcih_bus_space * const pibs = &sc->sc_io; 244 pibs->bst = *sc->sc_pci_bst; 245 pibs->bst.bs_cookie = pibs; 246 pibs->map = pibs->bst.bs_map; 247 pibs->flags = PCI_FLAGS_IO_OKAY; 248 pibs->bst.bs_map = pcihost_bus_space_map; 249 250 struct pcih_bus_space * const pmbs = &sc->sc_mem; 251 pmbs->bst = *sc->sc_pci_bst; 252 pmbs->bst.bs_cookie = pmbs; 253 pmbs->map = pmbs->bst.bs_map; 254 pmbs->flags = PCI_FLAGS_MEM_OKAY; 255 pmbs->bst.bs_map = pcihost_bus_space_map; 256 257 /* 258 * If this flag is set, skip configuration of the PCI bus and use 259 * existing config. 260 */ 261 const int chosen = OF_finddevice("/chosen"); 262 if (chosen <= 0 || of_getprop_uint32(chosen, "linux,pci-probe-only", &probe_only)) 263 probe_only = 0; 264 #if 0 265 266 if (sc->sc_pci_ranges != NULL) { 267 ranges = sc->sc_pci_ranges; 268 len = sc->sc_pci_ranges_cells * 4; 269 swap = false; 270 } else { 271 #endif 272 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 273 if (ranges == NULL) { 274 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 275 return EINVAL; 276 } 277 swap = true; 278 #if 0 279 } 280 #endif 281 struct pciconf_resources *pcires = pciconf_resource_init(); 282 283 /* 284 * Each entry in the ranges table contains: 285 * - bus address (3 cells) 286 * - cpu physical address (2 cells) 287 * - size (2 cells) 288 * Total size for each entry is 28 bytes (7 cells). 289 */ 290 while (len >= 28) { 291 #define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o]) 292 #define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1])) 293 const uint32_t phys_hi = DECODE32(ranges, 0); 294 uint64_t bus_phys = DECODE64(ranges, 1); 295 const uint64_t cpu_phys = DECODE64(ranges, 3); 296 uint64_t size = DECODE64(ranges, 5); 297 #undef DECODE32 298 #undef DECODE64 299 300 len -= 28; 301 ranges += 7; 302 303 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 304 PHYS_HI_SPACE_MEM64) ? true : false; 305 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 306 case PHYS_HI_SPACE_IO: 307 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 308 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 309 continue; 310 } 311 pibs->ranges[pibs->nranges].bpci = bus_phys; 312 pibs->ranges[pibs->nranges].bbus = cpu_phys; 313 pibs->ranges[pibs->nranges].size = size; 314 ++pibs->nranges; 315 aprint_verbose_dev(sc->sc_dev, 316 "IO: 0x%016" PRIx64 " + 0x%016" PRIx64 " @ 0x%016" PRIx64 "\n", 317 bus_phys, size, cpu_phys); 318 /* 319 * Reserve a PC-like legacy IO ports range, perhaps 320 * for access to VGA registers. 321 */ 322 if (bus_phys == 0 && size >= 0x10000) { 323 bus_phys += 0x1000; 324 size -= 0x1000; 325 } 326 error = pciconf_resource_add(pcires, 327 PCICONF_RESOURCE_IO, bus_phys, size); 328 if (error == 0) 329 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY; 330 break; 331 case PHYS_HI_SPACE_MEM64: 332 /* FALLTHROUGH */ 333 case PHYS_HI_SPACE_MEM32: 334 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 335 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 336 continue; 337 } 338 /* both pmem and mem spaces are in the same tag */ 339 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 340 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 341 pmbs->ranges[pmbs->nranges].size = size; 342 ++pmbs->nranges; 343 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 344 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 345 type = PCICONF_RESOURCE_PREFETCHABLE_MEM; 346 aprint_verbose_dev(sc->sc_dev, 347 "MMIO (%d-bit prefetchable) : 0x%016" PRIx64 " + 0x%016" PRIx64 " @ 0x%016" PRIx64 "\n", 348 is64 ? 64 : 32, bus_phys, size, cpu_phys); 349 } else { 350 type = PCICONF_RESOURCE_MEM; 351 aprint_verbose_dev(sc->sc_dev, 352 "MMIO (%d-bit non-prefetchable): 0x%016" PRIx64 " + 0x%016" PRIx64 " @ 0x%016" PRIx64 "\n", 353 is64 ? 64 : 32, bus_phys, size, cpu_phys); 354 } 355 error = pciconf_resource_add(pcires, type, bus_phys, 356 size); 357 if (error == 0) 358 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY; 359 break; 360 default: 361 break; 362 } 363 } 364 365 if (probe_only) { 366 error = 0; 367 } else { 368 error = pci_configure_bus(&sc->sc_pc, pcires, sc->sc_bus_min, 369 PCIHOST_CACHELINE_SIZE); 370 } 371 372 pciconf_resource_fini(pcires); 373 if (error) { 374 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 375 return error; 376 } 377 378 return 0; 379 } 380 381 static void 382 pcihost_attach_hook(device_t parent, device_t self, 383 struct pcibus_attach_args *pba) 384 { 385 } 386 387 static int 388 pcihost_bus_maxdevs(void *v, int busno) 389 { 390 return 32; 391 } 392 393 static pcitag_t 394 pcihost_make_tag(void *v, int b, int d, int f) 395 { 396 return (b << 16) | (d << 11) | (f << 8); 397 } 398 399 static void 400 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 401 { 402 if (bp) 403 *bp = (tag >> 16) & 0xff; 404 if (dp) 405 *dp = (tag >> 11) & 0x1f; 406 if (fp) 407 *fp = (tag >> 8) & 0x7; 408 } 409 410 static u_int 411 pcihost_get_segment(void *v) 412 { 413 struct pcihost_softc *sc = v; 414 415 return sc->sc_seg; 416 } 417 418 static pcireg_t 419 pcihost_conf_read(void *v, pcitag_t tag, int offset) 420 { 421 struct pcihost_softc *sc = v; 422 int b, d, f; 423 u_int reg; 424 425 pcihost_decompose_tag(v, tag, &b, &d, &f); 426 427 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 428 return (pcireg_t) -1; 429 430 if (sc->sc_type == PCIHOST_CAM) { 431 if (offset & ~0xff) 432 return (pcireg_t) -1; 433 reg = (b << 16) | (d << 11) | (f << 8) | offset; 434 } else if (sc->sc_type == PCIHOST_ECAM) { 435 if (offset & ~0xfff) 436 return (pcireg_t) -1; 437 reg = (b << 20) | (d << 15) | (f << 12) | offset; 438 } else { 439 return (pcireg_t) -1; 440 } 441 442 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 443 } 444 445 static void 446 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 447 { 448 struct pcihost_softc *sc = v; 449 int b, d, f; 450 u_int reg; 451 452 pcihost_decompose_tag(v, tag, &b, &d, &f); 453 454 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 455 return; 456 457 if (sc->sc_type == PCIHOST_CAM) { 458 if (offset & ~0xff) 459 return; 460 reg = (b << 16) | (d << 11) | (f << 8) | offset; 461 } else if (sc->sc_type == PCIHOST_ECAM) { 462 if (offset & ~0xfff) 463 return; 464 reg = (b << 20) | (d << 15) | (f << 12) | offset; 465 } else { 466 return; 467 } 468 469 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 470 } 471 472 static int 473 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 474 { 475 return PCI_CONF_DEFAULT; 476 } 477 478 static void 479 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 480 { 481 } 482 483 static int 484 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 485 { 486 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 487 u_int addr_cells, interrupt_cells; 488 const u_int *imap, *imask; 489 int imaplen, imasklen; 490 u_int match[4]; 491 int index; 492 493 if (pa->pa_intrpin == 0) 494 return EINVAL; 495 496 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 497 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 498 if (imap == NULL || imask == NULL || imasklen != 16) 499 return EINVAL; 500 501 /* Convert attach args to specifier */ 502 match[0] = htobe32( 503 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 504 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 505 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 506 ) & imask[0]; 507 match[1] = htobe32(0) & imask[1]; 508 match[2] = htobe32(0) & imask[2]; 509 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 510 511 index = 0; 512 while (imaplen >= 20) { 513 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 514 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 515 addr_cells = 2; 516 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 517 interrupt_cells = 0; 518 if (imaplen < (addr_cells + interrupt_cells) * 4) 519 return ENXIO; 520 521 if ((imap[0] & imask[0]) == match[0] && 522 (imap[1] & imask[1]) == match[1] && 523 (imap[2] & imask[2]) == match[2] && 524 (imap[3] & imask[3]) == match[3]) { 525 *ih = index; 526 return 0; 527 } 528 529 imap += (5 + addr_cells + interrupt_cells); 530 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 531 index++; 532 } 533 534 return EINVAL; 535 } 536 537 static const u_int * 538 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 539 { 540 u_int addr_cells, interrupt_cells; 541 int imaplen, index; 542 const u_int *imap; 543 544 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 545 KASSERT(imap != NULL); 546 547 index = 0; 548 while (imaplen >= 20) { 549 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 550 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 551 addr_cells = 2; 552 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 553 interrupt_cells = 0; 554 if (imaplen < (addr_cells + interrupt_cells) * 4) 555 return NULL; 556 557 if (index == ih) { 558 *pihandle = map_ihandle; 559 return imap + 5 + addr_cells; 560 } 561 562 imap += (5 + addr_cells + interrupt_cells); 563 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 564 index++; 565 } 566 567 return NULL; 568 } 569 570 static const char * 571 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 572 { 573 const int irq = __SHIFTOUT(ih, MD_PCI_INTR_IRQ); 574 const int vec = __SHIFTOUT(ih, MD_PCI_INTR_MSI_VEC); 575 struct pcihost_softc *sc = v; 576 const u_int *specifier; 577 int ihandle; 578 579 if (ih & MD_PCI_INTR_MSIX) { 580 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 581 } else if (ih & MD_PCI_INTR_MSI) { 582 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 583 } else { 584 specifier = pcihost_find_intr(sc, ih & MD_PCI_INTR_IRQ, &ihandle); 585 if (specifier == NULL) 586 return NULL; 587 588 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 589 return NULL; 590 } 591 592 return buf; 593 } 594 595 const struct evcnt * 596 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 597 { 598 return NULL; 599 } 600 601 static int 602 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 603 { 604 switch (attr) { 605 case PCI_INTR_MPSAFE: 606 if (data) 607 *ih |= MD_PCI_INTR_MPSAFE; 608 else 609 *ih &= ~MD_PCI_INTR_MPSAFE; 610 return 0; 611 default: 612 return ENODEV; 613 } 614 } 615 616 static void * 617 pcihost_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 618 int (*callback)(void *), void *arg, const char *xname) 619 { 620 struct pcihost_softc *sc = v; 621 const int flags = (pih & MD_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 622 const u_int *specifier; 623 int ihandle; 624 625 #ifdef __HAVE_PCI_MSI_MSIX 626 if ((pih & (MD_PCI_INTR_MSI | MD_PCI_INTR_MSIX)) != 0) { 627 void *ih = md_pci_msi_intr_establish(&sc->sc_pc, pih, ipl, 628 callback, arg, xname); 629 630 if (ih) { 631 struct pcihost_msi_handler * const pmh = 632 kmem_alloc(sizeof(*pmh), KM_SLEEP); 633 pmh->pmh_ih = ih; 634 mutex_enter(&sc->sc_msi_handlers_mutex); 635 LIST_INSERT_HEAD(&sc->sc_msi_handlers, pmh, pmh_next); 636 mutex_exit(&sc->sc_msi_handlers_mutex); 637 } 638 return ih; 639 } 640 #endif 641 642 specifier = pcihost_find_intr(sc, pih & MD_PCI_INTR_IRQ, &ihandle); 643 if (specifier == NULL) 644 return NULL; 645 646 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, 647 callback, arg, xname); 648 } 649 650 static void 651 pcihost_intr_disestablish(void *v, void *vih) 652 { 653 struct pcihost_softc *sc = v; 654 655 #ifdef __HAVE_PCI_MSI_MSIX 656 mutex_enter(&sc->sc_msi_handlers_mutex); 657 struct pcihost_msi_handler *pmh; 658 LIST_FOREACH(pmh, &sc->sc_msi_handlers, pmh_next) { 659 if (pmh->pmh_ih == vih) { 660 LIST_REMOVE(pmh, pmh_next); 661 mutex_exit(&sc->sc_msi_handlers_mutex); 662 kmem_free(pmh, sizeof(*pmh)); 663 return; 664 } 665 } 666 mutex_exit(&sc->sc_msi_handlers_mutex); 667 #endif 668 669 fdtbus_intr_disestablish(sc->sc_phandle, vih); 670 } 671 672 static int 673 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 674 bus_space_handle_t *bshp) 675 { 676 struct pcih_bus_space * const pbs = t; 677 678 if ((pbs->flags & PCI_FLAGS_IO_OKAY) != 0) { 679 flag = MD_PCI_IO_MAP_FLAGS; 680 } 681 682 for (size_t i = 0; i < pbs->nranges; i++) { 683 const bus_addr_t rmin = pbs->ranges[i].bpci; 684 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 685 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 686 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 687 } 688 } 689 690 return ERANGE; 691 } 692
Indexes created Sun Sep 27 00:26:35 UTC 2026