1 /* $NetBSD: pl061gpio_fdt.c,v 1.5 2021/01/27 03:10:21 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2018 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pl061gpio_fdt.c,v 1.5 2021/01/27 03:10:21 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 41 #include <dev/gpio/gpiovar.h> 42 43 #include <dev/ic/pl061reg.h> 44 #include <dev/ic/pl061var.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 static int plgpio_fdt_match(device_t, cfdata_t, void *); 49 static void plgpio_fdt_attach(device_t, device_t, void *); 50 51 static void * plgpio_fdt_acquire(device_t, const void *, 52 size_t, int); 53 static void plgpio_fdt_release(device_t, void *); 54 static int plgpio_fdt_read(device_t, void *, bool); 55 static void plgpio_fdt_write(device_t, void *, int, bool); 56 57 struct fdtbus_gpio_controller_func plgpio_fdt_funcs = { 58 .acquire = plgpio_fdt_acquire, 59 .release = plgpio_fdt_release, 60 .read = plgpio_fdt_read, 61 .write = plgpio_fdt_write 62 }; 63 64 struct plgpio_fdt_pin { 65 struct plgpio_softc * pin_sc; 66 int pin_no; 67 u_int pin_flags; 68 bool pin_actlo; 69 }; 70 71 CFATTACH_DECL_NEW(plgpio_fdt, sizeof(struct plgpio_softc), 72 plgpio_fdt_match, plgpio_fdt_attach, NULL, NULL); 73 74 static const struct device_compatible_entry compat_data[] = { 75 { .compat = "arm,pl061" }, 76 DEVICE_COMPAT_EOL 77 }; 78 79 static int 80 plgpio_fdt_match(device_t parent, cfdata_t cf, void *aux) 81 { 82 struct fdt_attach_args * const faa = aux; 83 84 return of_compatible_match(faa->faa_phandle, compat_data); 85 } 86 87 static void 88 plgpio_fdt_attach(device_t parent, device_t self, void *aux) 89 { 90 struct plgpio_softc * const sc = device_private(self); 91 struct fdt_attach_args * const faa = aux; 92 bus_addr_t addr; 93 bus_size_t size; 94 int error; 95 96 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 97 aprint_error(": couldn't get registers\n"); 98 return; 99 } 100 101 sc->sc_dev = self; 102 sc->sc_bst = faa->faa_bst; 103 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 104 if (error) { 105 aprint_error(": couldn't map %#"PRIx64": %d", (uint64_t)addr, error); 106 return; 107 } 108 109 aprint_naive("\n"); 110 aprint_normal(": GPIO\n"); 111 112 plgpio_attach(sc); 113 114 fdtbus_register_gpio_controller(self, faa->faa_phandle, 115 &plgpio_fdt_funcs); 116 } 117 118 static void * 119 plgpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags) 120 { 121 struct plgpio_softc * const sc = device_private(dev); 122 struct plgpio_fdt_pin *gpin; 123 const u_int *gpio = data; 124 125 if (len != 12) 126 return NULL; 127 128 const u_int pin = be32toh(gpio[1]); 129 const bool actlo = be32toh(gpio[2]) & 1; 130 131 if (pin > 8) 132 return NULL; 133 134 const uint32_t cnf = PLGPIO_READ(sc, PL061_GPIOAFSEL_REG); 135 if ((cnf & __BIT(pin)) != 0) 136 PLGPIO_WRITE(sc, PL061_GPIOAFSEL_REG, cnf & ~__BIT(pin)); 137 138 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 139 gpin->pin_sc = sc; 140 gpin->pin_no = pin; 141 gpin->pin_flags = flags; 142 gpin->pin_actlo = actlo; 143 144 plgpio_pin_ctl(gpin->pin_sc, gpin->pin_no, gpin->pin_flags); 145 146 return gpin; 147 } 148 149 static void 150 plgpio_fdt_release(device_t dev, void *priv) 151 { 152 struct plgpio_fdt_pin * const gpin = priv; 153 154 plgpio_pin_ctl(gpin->pin_sc, gpin->pin_no, GPIO_PIN_INPUT); 155 kmem_free(gpin, sizeof(*gpin)); 156 } 157 158 static int 159 plgpio_fdt_read(device_t dev, void *priv, bool raw) 160 { 161 struct plgpio_fdt_pin * const gpin = priv; 162 int val; 163 164 val = plgpio_pin_read(gpin->pin_sc, gpin->pin_no); 165 166 if (!raw && gpin->pin_actlo) 167 val = !val; 168 169 return val; 170 } 171 172 static void 173 plgpio_fdt_write(device_t dev, void *priv, int val, bool raw) 174 { 175 struct plgpio_fdt_pin * const gpin = priv; 176 177 if (!raw && gpin->pin_actlo) 178 val = !val; 179 180 plgpio_pin_write(gpin->pin_sc, gpin->pin_no, val); 181 } 182
Indexes created Sat Sep 20 22:09:52 GMT 2025