1 /* $NetBSD: adt7462reg.h,v 1.3 2026/09/03 05:26:58 jdc Exp $ */ 2 3 /*- 4 * Copyright (c) 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Julian Coleman. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_I2C_ADT7462REG_H_ 33 #define _DEV_I2C_ADT7462REG_H_ 34 35 /* 36 * Register definitions for "ADT7462 Flexible Temperature, Voltage Monitor, 37 * and System Fan Controller". 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: adt7462reg.h,v 1.3 2026/09/03 05:26:58 jdc Exp $"); 42 43 #define ADT7462_ADDR1 0x58 44 #define ADT7462_ADDR2 0x5c 45 46 #define ADT7462_CONF0 0x00 47 #define ADT7462_CONF1 0x01 48 #define ADT7462_CONF2 0x02 49 #define ADT7462_CONF3 0x03 50 #define ADT7462_TACH_EN 0x07 51 #define ADT7462_TACH_CFG 0x08 52 #define ADT7462_GPIO1_CFG 0x09 53 #define ADT7462_GPIO2_CFG 0x0a 54 #define ADT7462_TMIN_CAL1 0x0b 55 #define ADT7462_TMIN_CAL2 0x0c 56 #define ADT7462_THERM_CONF 0x0d 57 #define ADT7462_CONF_THERM1 0x0e 58 #define ADT7462_CONF_THERM2 0x0f 59 #define ADT7462_PIN_CONF1 0x10 60 #define ADT7462_PIN_CONF2 0x11 61 #define ADT7462_PIN_CONF3 0x12 62 #define ADT7462_PIN_CONF4 0x13 63 #define ADT7462_EASY_CONF 0x14 64 #define ADT7462_EDO_ENABLE 0x16 65 #define ADT7462_ATTEN1_EN 0x18 66 #define ADT7462_ATTEN2_EN 0x19 67 #define ADT7462_ACCOUSTICS1 0x1a 68 #define ADT7462_ACCOUSTICS2 0x1b 69 #define ADT7462_FAN_TEST 0x1c 70 #define ADT7462_FANS_PRESENT 0x1d 71 #define ADT7462_FAN_TEST_EN 0x1e 72 #define ADT7462_PWM1_CFG 0x21 73 #define ADT7462_PWM2_CFG 0x22 74 #define ADT7462_PWM3_CFG 0x23 75 #define ADT7462_PWM4_CFG 0x24 76 #define ADT7462_PWM12_FREQ 0x25 77 #define ADT7462_PWM34_FREQ 0x26 78 #define ADT7462_PWM1_MIN 0x28 /* Minimum PWM1 duty cycle */ 79 #define ADT7462_PWM2_MIN 0x29 /* Minimum PWM2 duty cycle */ 80 #define ADT7462_PWM3_MIN 0x2a /* Minimum PWM3 duty cycle */ 81 #define ADT7462_PWM4_MIN 0x2b /* Minimum PWM4 duty cycle */ 82 #define ADT7462_PWM1234_MAX 0x2c /* Maximum all PWM duty cycle */ 83 #define ADT7462_THERM_MASK1 0x30 84 #define ADT7462_THERM_MASK2 0x31 85 #define ADT7462_VOLT_MASK1 0x32 86 #define ADT7462_VOLT_MASK2 0x33 87 #define ADT7462_FAN_MASK 0x34 88 #define ADT7462_DIG_MASK 0x35 89 #define ADT7462_GPIO_MASK 0x36 90 #define ADT7462_EDO_MASK1 0x37 91 #define ADT7462_EDO_MASK2 0x38 92 #define ADT7462_DEV_ID 0x3d 93 #define ADT7462_COMP_ID 0x3e 94 #define ADT7462_REV_ID 0x3f 95 #define ADT7462_LOCAL_LOW 0x44 96 #define ADT7462_REM1_LOW 0x45 /* Register contents depend on */ 97 #define ADT7462_PIN15V_LOW 0x45 /* pin configuration. */ 98 #define ADT7462_REM2_LOW 0x46 99 #define ADT7462_REM3_LOW 0x47 100 #define ADT7462_PIN19V_LOW 0x47 101 #define ADT7462_LOCAL_HIGH 0x48 102 #define ADT7462_REM1_HIGH 0x49 103 #define ADT7462_PIN15V_HIGH 0x49 104 #define ADT7462_REM2_HIGH 0x4a 105 #define ADT7462_REM3_HIGH 0x4b 106 #define ADT7462_PIN19V_HIGH 0x4b 107 #define ADT7462_LOCAL_THERM1 0x4c 108 #define ADT7462_15V2_HIGH 0x4c 109 #define ADT7462_REM1_THERM1 0x4d 110 #define ADT7462_REM2_THERM1 0x4e 111 #define ADT7462_REM3_THERM1 0x4f 112 #define ADT7462_LOCAL_THERM2 0x50 113 #define ADT7462_15V1_HIGH 0x50 114 #define ADT7462_REM1_THERM2 0x51 115 #define ADT7462_REM2_THERM2 0x52 116 #define ADT7462_REM3_THERM2 0x53 117 #define ADT7462_LOCREM1_HYST 0x54 118 #define ADT7462_REM23_HYST 0x55 119 #define ADT7462_LOCAL_OFF 0x56 120 #define ADT7462_REM1_OFF 0x57 121 #define ADT7462_REM2_OFF 0x58 122 #define ADT7462_REM3_OFF 0x59 123 #define ADT7462_REM1_OPP 0x5a 124 #define ADT7462_REM2_OPP 0x5b 125 #define ADT7462_LOCAL_MIN 0x5c 126 #define ADT7462_REM1_MIN 0x5d 127 #define ADT7462_REM2_MIN 0x5e 128 #define ADT7462_REM3_MIN 0x5f 129 #define ADT7462_LOCAL_RANGE 0x60 130 #define ADT7462_REM1_RANGE 0x61 131 #define ADT7462_REM2_RANGE 0x62 132 #define ADT7462_REM3_RANGE 0x63 133 #define ADT7462_OPP_HYST 0x64 134 #define ADT7462_33V_HIGH 0x68 135 #define ADT7462_PIN23V_HIGH 0x69 136 #define ADT7462_PIN24V_HIGH 0x6a 137 #define ADT7462_PIN25V_HIGH 0x6b 138 #define ADT7462_PIN26V_HIGH 0x6c 139 #define ADT7462_12V1_LOW 0x6d 140 #define ADT7462_12V2_LOW 0x6e 141 #define ADT7462_12V3_LOW 0x6f 142 #define ADT7462_33V_LOW 0x70 143 #define ADT7462_5V_LOW 0x71 144 #define ADT7462_PIN23V_LOW 0x72 145 #define ADT7462_PIN24V_LOW 0x73 146 #define ADT7462_PIN25V_LOW 0x74 147 #define ADT7462_PIN26V_LOW 0x75 148 #define ADT7462_15V1_LOW 0x76 149 #define ADT7462_15V2_LOW 0x77 150 #define ADT7462_TACH1_LIMIT 0x78 151 #define ADT7462_VID_LIMIT 0x78 152 #define ADT7462_TACH2_LIMIT 0x79 153 #define ADT7462_TACH3_LIMIT 0x7a 154 #define ADT7462_TACH4_LIMIT 0x7b 155 #define ADT7462_TACH5_LIMIT 0x7c 156 #define ADT7462_12V1_HIGH 0x7c 157 #define ADT7462_TACH6_LIMIT 0x7d 158 #define ADT7462_12V2_HIGH 0x7d 159 #define ADT7462_TACH7_LIMIT 0x7e 160 #define ADT7462_5V_HIGH 0x7e 161 #define ADT7462_TACH8_LIMIT 0x7f 162 #define ADT7462_12V3_HIGH 0x7f 163 #define ADT7462_THERM1_TIMELIM 0x80 164 #define ADT7462_THERM2_TIMELIM 0x81 165 #define ADT7462_LOCAL_VAL_LSB 0x88 166 #define ADT7462_LOCAL_VAL_MSB 0x89 167 #define ADT7462_REM1_VAL_LSB 0x8a 168 #define ADT7462_REM1_VAL_MSB 0x8b 169 #define ADT7462_PIN15V_VAL 0x8b 170 #define ADT7462_REM2_VAL_LSB 0x8c 171 #define ADT7462_REM2_VAL_MSB 0x8d 172 #define ADT7462_REM3_VAL_LSB 0x8e 173 #define ADT7462_REM3_VAL_MSB 0x8f 174 #define ADT7462_PIN19V_VAL 0x8f 175 #define ADT7462_PIN23V_VAL 0x90 176 #define ADT7462_PIN24V_VAL 0x91 177 #define ADT7462_PIN25V_VAL 0x92 178 #define ADT7462_PIN26V_VAL 0x93 179 #define ADT7462_15V1_VAL 0x94 180 #define ADT7462_15V2_VAL 0x95 181 #define ADT7462_33V_VAL 0x96 182 #define ADT7462_VID_VAL 0x97 183 #define ADT7462_TACH1_VAL_LSB 0x98 184 #define ADT7462_TACH1_VAL_MSB 0x99 185 #define ADT7462_TACH2_VAL_LSB 0x9a 186 #define ADT7462_TACH2_VAL_MSB 0x9b 187 #define ADT7462_TACH3_VAL_LSB 0x9c 188 #define ADT7462_TACH3_VAL_MSB 0x9d 189 #define ADT7462_TACH4_VAL_LSB 0x9e 190 #define ADT7462_TACH4_VAL_MSB 0x9f 191 #define ADT7462_TACH5_VAL_LSB 0xa2 192 #define ADT7462_TACH5_VAL_MSB 0xa3 193 #define ADT7462_12V1_VAL 0xa3 194 #define ADT7462_TACH6_VAL_LSB 0xa4 195 #define ADT7462_TACH6_VAL_MSB 0xa5 196 #define ADT7462_12V2_VAL 0xa5 197 #define ADT7462_TACH7_VAL_LSB 0xa6 198 #define ADT7462_TACH7_VAL_MSB 0xa7 199 #define ADT7462_5V_VAL 0xa7 200 #define ADT7462_TACH8_VAL_LSB 0xa8 201 #define ADT7462_TACH8_VAL_MSB 0xa9 202 #define ADT7462_12V3_VAL 0xa9 203 #define ADT7462_PWM1_DUTY 0xaa 204 #define ADT7462_PWM2_DUTY 0xab 205 #define ADT7462_PWM3_DUTY 0xac 206 #define ADT7462_PWM4_DUTY 0xad 207 #define ADT7462_THERM1_ON_TIM 0xae 208 #define ADT7462_THERM2_ON_TIM 0xaf 209 #define ADT7462_TEMP1_STAT_H 0xb8 210 #define ADT7462_TEMP2_STAT_H 0xb9 211 #define ADT7462_TEMP3_STAT_H 0xba 212 #define ADT7462_VOLT1_STAT_H 0xbb 213 #define ADT7462_VOLT2_STAT_H 0xbc 214 #define ADT7462_FAN_STAT_H 0xbd 215 #define ADT7462_DIG_STAT_H 0xbe 216 #define ADT7462_GPIO_STAT_H 0xbf 217 #define ADT7462_TEMP1_STAT_B 0xc0 218 #define ADT7462_TEMP2_STAT_B 0xc1 219 #define ADT7462_VOLT1_STAT_B 0xc3 220 #define ADT7462_VOLT2_STAT_B 0xc4 221 #define ADT7462_FAN_STAT_B 0xc5 222 #define ADT7462_DIG_STAT_B 0xc6 223 224 /* 0x00: Configuration register 0 */ 225 #define ADT7462_CONF0_BLK_MASK 0x3f /* # registers for block read */ 226 #define ADT7462_CONF0_VID_SPEC 0x40 /* 0 = VR10, 1 = VR11 */ 227 #define ADT7462_CONF0_RESET 0x80 /* Reset all unlocked registers */ 228 229 /* 0x01: Configuration register 1 */ 230 #define ADT7462_CONF1_MONITOR 0x01 /* Start monitoring temps and volts */ 231 #define ADT7462_CONF1_ALERT 0x08 /* 0 = SMB, 1 = comparator */ 232 #define ADT7462_CONF1_FAST_SPIN 0x10 /* 1 = no fast spin-up */ 233 #define ADT7462_CONF1_COMPLETE 0x20 /* Setup complete, start monitoring */ 234 #define ADT7462_CONF1_LOCK 0x40 /* Lock limit registers */ 235 #define ADT7462_CONF1_READY 0x80 /* Ready to start monitoring */ 236 237 /* 0x02: Configuration register 2 */ 238 #define ADT7462_CONF2_FAN_HF 0x01 /* Fast fan measurements */ 239 #define ADT7462_CONF2_PWM_HF 0x04 /* High frequency PWM measurements */ 240 #define ADT7462_CONF2_VRD1 0x08 /* Full speed fans on VRD1 */ 241 #define ADT7462_CONF2_VRD2 0x10 /* Full speed fans on VRD2 */ 242 #define ADT7462_CONF2_FFULL 0x20 /* Full speed fans */ 243 #define ADT7462_CONF2_TACH 0xc0 /* Tach pulse to measure */ 244 #define ADT7462_CONF2_TACH1 0x00 /* 1 */ 245 #define ADT7462_CONF2_TACH2 0x40 /* 2 */ 246 #define ADT7462_CONF2_TACH3 0x80 /* 3 */ 247 #define ADT7462_CONF2_TACH4 0xc0 /* 4 */ 248 249 /* 0x03: Configuration register 3 */ 250 #define ADT7462_CONF3_GPIO_EN 0x01 /* Enable GPIO's */ 251 #define ADT7462_CONF3_SCL_TO 0x02 /* Enable SCL timeout */ 252 #define ADT7462_CONF3_SDA_TO 0x04 /* Enable SDA timeout */ 253 #define ADT7462_CONF3_VID_LVL 0x08 /* Set low VID threshold */ 254 #define ADT7462_CONF3_THERM_LVL 0x10 /* Set low therm threshold */ 255 #define ADT7462_CONF3_CI_RESET 0x20 /* Reset chassis intrusion circuit */ 256 #define ADT7462_CONF3_XOR_TEST 0x40 /* Enable XOR tree test */ 257 #define ADT7462_CONF3_VCORE_LOW 0x80 /* Set V_core_low */ 258 259 /* 0x07: Tach enable register */ 260 #define ADT7462_TACH1_ENABLE 0x01 /* Enable tach1 measurement */ 261 #define ADT7462_TACH2_ENABLE 0x02 /* Enable tach2 measurement */ 262 #define ADT7462_TACH3_ENABLE 0x04 /* Enable tach3 measurement */ 263 #define ADT7462_TACH4_ENABLE 0x08 /* Enable tach4 measurement */ 264 #define ADT7462_TACH5_ENABLE 0x10 /* Enable tach5 measurement */ 265 #define ADT7462_TACH6_ENABLE 0x20 /* Enable tach6 measurement */ 266 #define ADT7462_TACH7_ENABLE 0x40 /* Enable tach7 measurement */ 267 #define ADT7462_TACH8_ENABLE 0x80 /* Enable tach8 measurement */ 268 269 #define ADT7462_FAN_TACH_EN(val, x) ((val & (1 << x)) != 0) 270 271 /* 0x08: Tach configuration register */ 272 #define ADT7462_TACH15_CONT 0x01 /* Continuous tach1+5 measurement */ 273 #define ADT7462_TACH26_CONT 0x02 /* Continuous tach2+6 measurement */ 274 #define ADT7462_TACH37_CONT 0x04 /* Continuous tach3+7 measurement */ 275 #define ADT7462_TACH48_CONT 0x08 /* Continuous tach4+8 measurement */ 276 277 /* 0x09: GPIO configuration register 1 */ 278 #define ADT7462_GPIO1_POL 0x01 /* GPIO1 polarity (0 low, 1 high) */ 279 #define ADT7462_GPIO1_DIR 0x02 /* GPIO1 direction (0 in, 1 out) */ 280 #define ADT7462_GPIO2_POL 0x04 /* GPIO2 polarity (0 low, 1 high) */ 281 #define ADT7462_GPIO2_DIR 0x08 /* GPIO2 direction (0 in, 1 out) */ 282 #define ADT7462_GPIO3_POL 0x10 /* GPIO3 polarity (0 low, 1 high) */ 283 #define ADT7462_GPIO3_DIR 0x20 /* GPIO3 direction (0 in, 1 out) */ 284 #define ADT7462_GPIO4_POL 0x40 /* GPIO4 polarity (0 low, 1 high) */ 285 #define ADT7462_GPIO4_DIR 0x80 /* GPIO4 direction (0 in, 1 out) */ 286 287 /* 0x0a: GPIO configuration register 2 */ 288 #define ADT7462_GPIO5_POL 0x01 /* GPIO5 polarity (0 low, 1 high) */ 289 #define ADT7462_GPIO5_DIR 0x02 /* GPIO5 direction (0 in, 1 out) */ 290 #define ADT7462_GPIO6_POL 0x04 /* GPIO6 polarity (0 low, 1 high) */ 291 #define ADT7462_GPIO6_DIR 0x08 /* GPIO6 direction (0 in, 1 out) */ 292 #define ADT7462_GPIO7_POL 0x10 /* GPIO7 polarity (0 low, 1 high) */ 293 #define ADT7462_GPIO7_DIR 0x20 /* GPIO7 direction (0 in, 1 out) */ 294 #define ADT7462_GPIO8_POL 0x40 /* GPIO8 polarity (0 low, 1 high) */ 295 #define ADT7462_GPIO8_DIR 0x80 /* GPIO8 direction (0 in, 1 out) */ 296 297 #define ADT7462_GPIO_POL(val, x) (val & (1 << (i * 2)) ? 1 : 0) 298 #define ADT7462_GPIO_DIR(val, x) (val & (1 << (i * 2 + 1)) ? 1 : 0) 299 300 /* 0x0b: Dynamix Tmin control register 1 */ 301 #define ADT7462_REM1_EN 0x01 /* Enable dynamic rem 1 Tmin control */ 302 #define ADT7462_REM2_EN 0x02 /* Enable dynamic rem 2 Tmin control */ 303 #define ADT7462_P1_R1 0x04 /* Copy rem 1 val to op if therm1 */ 304 #define ADT7462_P1_R2 0x08 /* Copy rem 2 val to op if therm1 */ 305 #define ADT7462_P2_R1 0x10 /* Copy rem 1 val to op if therm2 */ 306 #define ADT7462_P2_R2 0x20 /* Copy rem 2 val to op if therm2 */ 307 308 /* 0x0c: Dynamic Tmin control register 2 */ 309 #define ADT7462_REM1_CYCLE 0x07 /* Rem 1 cycle mask */ 310 #define ADT7462_REM2_CYCLE 0x38 /* Rem 2 cycle mask */ 311 #define ADT7462_CTRL_LOOP 0x40 /* Control loop select */ 312 313 /* 0x0d: Therm configuration register */ 314 #define ADT7462_BOOST1 0x01 /* Max fan PWM if therm1 */ 315 #define ADT7462_BOOST2 0x02 /* Max fan PWM if therm2 */ 316 #define ADT7462_THERM1_TIMER 0x1c /* Therm1 timer window mask */ 317 #define ADT7462_THERM2_TIMER 0xe0 /* Therm2 timer window mask */ 318 319 /* 0x0e: Therm1 configuration register */ 320 #define ADT7462_THERM1_TIM_EN 0x01 /* Enable therm1 timer circuit */ 321 #define ADT7462_THERM1_LOCAL 0x02 /* Therm1 assert on local */ 322 #define ADT7462_THERM1_REM1 0x04 /* Therm1 assert on remote1 */ 323 #define ADT7462_THERM1_REM2 0x08 /* Therm1 assert on remote2 */ 324 #define ADT7462_THERM1_REM3 0x10 /* Therm1 assert on remote3 */ 325 326 /* 0x0f: Therm2 configuration register */ 327 #define ADT7462_THERM2_TIM_EN 0x01 /* Enable therm2 timer circuit */ 328 #define ADT7462_THERM2_LOCAL 0x02 /* Therm2 assert on local */ 329 #define ADT7462_THERM2_REM1 0x04 /* Therm2 assert on remote1 */ 330 #define ADT7462_THERM2_REM2 0x08 /* Therm2 assert on remote2 */ 331 #define ADT7462_THERM2_REM3 0x10 /* Therm2 assert on remote3 */ 332 333 /* 0x10: Pin configuration register 1 */ 334 #define ADT7462_PIN7_CONF 0x01 /* 0 = +12v1, 1 = Tach5 */ 335 #define ADT7462_PIN4_CONF 0x02 /* 0 = GPIO4, 1 = Tach4 */ 336 #define ADT7462_PIN3_CONF 0x04 /* 0 = GPIO3, 1 = Tach3 */ 337 #define ADT7462_PIN2_CONF 0x08 /* 0 = GPIO2, 1 = Tach2 */ 338 #define ADT7462_PIN1_CONF 0x10 /* 0 = GPIO1, 1 = Tach1 */ 339 #define ADT7462_DIODE3_CONF 0x20 /* 0 = volt/SCSI, 1 = D3+/D3- */ 340 #define ADT7462_DIODE1_CONF 0x40 /* 0 = volt/SCSI, 1 = D1+/D1- */ 341 #define ADT7462_VID_EN 0x80 /* 1 = En. VID's pins 1-4 28 31 32 */ 342 343 #define ADT7462_PCR1_TACH(val, x) (x > 4 || \ 344 (x == 4 && (val & ADT7462_PIN7_CONF)) || \ 345 (!(val & ADT7462_VID_EN) && (val & (1 << (4 - x))))) 346 #define ADT7462_PCR1_TEMP(val, x) (x== 0 || x == 2 || \ 347 (x == 3 && (val & ADT7462_DIODE3_CONF)) || \ 348 (x == 1 && (val & ADT7462_DIODE1_CONF))) 349 #define ADT7462_PCR1_PIN7_V(val) (!(val & ADT7462_PIN7_CONF)) 350 #define ADT7462_PCR1_PIN19_V(val) (!(val & ADT7462_DIODE3_CONF)) 351 #define ADT7462_PCR1_PIN15_V(val) (!(val & ADT7462_DIODE1_CONF)) 352 #define ADT7462_PCR1_VIDS(val) ((val & ADT7462_VID_EN) != 0) 353 #define ADT7462_PCR1_GPIO(val, x) (x > 3 || \ 354 (!(val & ADT7462_VID_EN) && !(val & (1 << (4 - x))))) 355 356 /* 0x11: Pin configuration register 2 */ 357 #define ADT7462_PIN23_CONF 0x03 /* 00 = Vcc, 2.5v, 1.8v, 11 = 1.5v */ 358 #define ADT7462_PIN22_CONF 0x04 /* 0 = 12v3, 1 = Tach8 */ 359 #define ADT7462_PIN21_CONF 0x08 /* 0 = 5v, 1 = Tach7 */ 360 #define ADT7462_PIN19_CONF 0x10 /* 0 = 1.25v, 1 = 0.9v */ 361 #define ADT7462_PIN15_CONF 0x20 /* 0 = 2.5v, 1 = 1.8v */ 362 #define ADT7462_PIN13_CONF 0x40 /* 0 = 3.3v, 1 = PWM4 */ 363 #define ADT7462_PIN8_CONF 0x80 /* 0 = 12v2, 1 = Tach6 */ 364 365 #define ADT7462_PCR2_P23_25V(val) ((val & ADT7462_PIN23_CONF) == 0x01) 366 #define ADT7462_PCR2_P23_18V(val) ((val & ADT7462_PIN23_CONF) == 0x02) 367 #define ADT7462_PCR2_P23_15V(val) ((val & ADT7462_PIN23_CONF) == 0x03) 368 #define ADT7462_PCR2_P22_TACH8(val) ((val & ADT7462_PIN22_CONF) == 0x04) 369 #define ADT7462_PCR2_P21_TACH7(val) ((val & ADT7462_PIN21_CONF) == 0x08) 370 #define ADT7462_PCR2_P19_09V(val) ((val & ADT7462_PIN19_CONF) == 0x10) 371 #define ADT7462_PCR2_P15_18V(val) ((val & ADT7462_PIN15_CONF) == 0x20) 372 #define ADT7462_PCR2_P13_PWM4(val) ((val & ADT7462_PIN13_CONF) == 0x40) 373 #define ADT7462_PCR2_P8_TACH6(val) ((val & ADT7462_PIN8_CONF) == 0x80) 374 #define ADT7462_PCR2_TACH(val, x) (x < 5 || \ 375 (x == 5 && ADT7462_PCR2_P8_TACH6(val)) || \ 376 (x == 6 && ADT7462_PCR2_P21_TACH7(val)) || \ 377 (x == 7 && ADT7462_PCR2_P22_TACH8(val))) 378 379 /* 0x12: Pin configuration register 3 */ 380 #define ADT7462_PIN27_CONF 0x02 /* 0 = fan2max, 1 = chassis intrus */ 381 #define ADT7462_PIN26_CONF 0x0c /* 00 = Vbatt, 1.2v2, 10/11=vr_hot2 */ 382 #define ADT7462_PIN25_CONF 0x30 /* 00 = 3.3v, 1.2v1, 10/11=vr_hot1 */ 383 #define ADT7462_PIN24_CONF 0xc0 /* 00 = Vccp, 2.5v, 1.8v, 11 = 1.5v */ 384 385 #define ADT7462_PCR3_P24_25V(val) ((val & ADT7462_PIN24_CONF) == 0x40) 386 #define ADT7462_PCR3_P24_18V(val) ((val & ADT7462_PIN24_CONF) == 0x80) 387 #define ADT7462_PCR3_P24_15V(val) ((val & ADT7462_PIN24_CONF) == 0xc0) 388 #define ADT7462_PCR3_P25_33V(val) ((val & ADT7462_PIN25_CONF) == 0x00) 389 #define ADT7462_PCR3_P25_12V(val) ((val & ADT7462_PIN25_CONF) == 0x10) 390 #define ADT7462_PCR3_P26_VBAT(val) ((val & ADT7462_PIN26_CONF) == 0x00) 391 #define ADT7462_PCR3_P26_12V(val) ((val & ADT7462_PIN26_CONF) == 0x04) 392 393 /* 0x13: Pin configuration register 4 */ 394 #define ADT7462_PIN32_CONF 0x04 /* 0 = GPIO6, 1 = PWM2 */ 395 #define ADT7462_PIN31_CONF 0x08 /* 0 = GPIO5, 1 = PWM1 */ 396 #define ADT7462_PIN29_CONF 0x30 /* 00 = GPIO8, 1.5v, 10/11 = therm2 */ 397 #define ADT7462_PIN28_CONF 0xc0 /* 00 = GPIO7, 1.5v, 10/11 = therm1 */ 398 399 #define ADT7462_PCR4_P29_15V(val) ((val & ADT7462_PIN29_CONF) == 0x10) 400 #define ADT7462_PCR4_P28_15V(val) ((val & ADT7462_PIN28_CONF) == 0x10) 401 #define ADT7462_PCR4_GPIO(val, x) (x < 4 || \ 402 (x == 4 && !(val & ADT7462_PIN31_CONF)) || \ 403 (x == 5 && !(val & ADT7462_PIN32_CONF)) || \ 404 (x == 6 && !(val & ADT7462_PIN28_CONF)) || \ 405 (x == 7 && !(val & ADT7462_PIN28_CONF))) 406 407 /* 0x14: Easy configuration options */ 408 #define ADT7462_EASY1 0x01 /* Enable easy option 1 */ 409 #define ADT7462_EASY2 0x02 /* Enable easy option 2 */ 410 #define ADT7462_EASY3 0x04 /* Enable easy option 3 */ 411 #define ADT7462_EASY4 0x08 /* Enable easy option 4 */ 412 413 /* 0x16: EDO/Single channel enable */ 414 #define ADT7462_EDO_EN1 0x01 /* Enable EDO on GPIO5 */ 415 #define ADT7462_EDO_EN2 0x02 /* Enable EDO on GPIO6 */ 416 #define ADT7462_1CHAN_MODE 0x04 /* Select single-channel mode */ 417 #define ADT7462_CHAN_SEL 0xf8 /* Select channel mask */ 418 419 /* 0x18: Voltage attenuator configuration 1 */ 420 #define ADT7462_ATT_PIN7 0x02 /* Enable attenuator on pin7 */ 421 #define ADT7462_ATT_PIN8 0x04 /* Enable attenuator on pin8 */ 422 #define ADT7462_ATT_PIN13 0x08 /* Enable attenuator on pin13 */ 423 #define ADT7462_ATT_PIN15 0x10 /* Enable attenuator on pin15 */ 424 #define ADT7462_ATT_PIN19 0x20 /* Enable attenuator on pin19 */ 425 #define ADT7462_ATT_PIN21 0x40 /* Enable attenuator on pin21 */ 426 #define ADT7462_ATT_PIN22 0x80 /* Enable attenuator on pin22 */ 427 428 /* 0x19: Voltage attenuator configuration 2 */ 429 #define ADT7462_ATT_PIN23 0x01 /* Enable attenuator on pin23 */ 430 #define ADT7462_ATT_PIN24 0x02 /* Enable attenuator on pin24 */ 431 #define ADT7462_ATT_PIN25 0x04 /* Enable attenuator on pin25 */ 432 #define ADT7462_ATT_PIN28 0x10 /* Enable attenuator on pin28 */ 433 #define ADT7462_ATT_PIN29 0x20 /* Enable attenuator on pin29 */ 434 435 /* 0x1a: Enhanced acoustics register 1 */ 436 #define ADT7462_AC_EN1 0x01 /* En. enhanced acoustics for PWM1 */ 437 #define ADT7462_AC_EN2 0x02 /* En. enhanced acoustics for PWM2 */ 438 #define ADT7462_AC_RATE1 0x1c /* Ramp rate for PWM1 */ 439 #define ADT7462_AC_RATE2 0xe0 /* Ramp rate for PWM2 */ 440 441 /* 0x1b: Enhanced acoustics register 2 */ 442 #define ADT7462_AC_EN3 0x01 /* En. enhanced acoustics for PWM3 */ 443 #define ADT7462_AC_EN4 0x02 /* En. enhanced acoustics for PWM4 */ 444 #define ADT7462_AC_RATE3 0x1c /* Ramp rate for PWM3 */ 445 #define ADT7462_AC_RATE4 0xe0 /* Ramp rate for PWM4 */ 446 447 /* 0x1c: Fan freewheeling test */ 448 #define ADT7462_FAN_FREE1_END 0x01 /* Freewheeling for fan1 complete */ 449 #define ADT7462_FAN_FREE2_END 0x02 /* Freewheeling for fan2 complete */ 450 #define ADT7462_FAN_FREE3_END 0x04 /* Freewheeling for fan3 complete */ 451 #define ADT7462_FAN_FREE4_END 0x08 /* Freewheeling for fan4 complete */ 452 #define ADT7462_FAN_FREE5_END 0x10 /* Freewheeling for fan5 complete */ 453 #define ADT7462_FAN_FREE6_END 0x20 /* Freewheeling for fan6 complete */ 454 #define ADT7462_FAN_FREE7_END 0x40 /* Freewheeling for fan7 complete */ 455 #define ADT7462_FAN_FREE8_END 0x80 /* Freewheeling for fan8 complete */ 456 457 /* 0x1d: Fans present */ 458 #define ADT7462_FAN1_PRESENT 0x01 /* Fan1 present */ 459 #define ADT7462_FAN2_PRESENT 0x02 /* Fan2 present */ 460 #define ADT7462_FAN3_PRESENT 0x04 /* Fan3 present */ 461 #define ADT7462_FAN4_PRESENT 0x08 /* Fan4 present */ 462 #define ADT7462_FAN5_PRESENT 0x10 /* Fan5 present */ 463 #define ADT7462_FAN6_PRESENT 0x20 /* Fan6 present */ 464 #define ADT7462_FAN7_PRESENT 0x40 /* Fan7 present */ 465 #define ADT7462_FAN8_PRESENT 0x80 /* Fan8 present */ 466 467 /* 0x1e: Fan freewheeling test */ 468 #define ADT7462_FAN_FREE1 0x01 /* Start freewheeling test for fan1 */ 469 #define ADT7462_FAN_FREE2 0x02 /* Start freewheeling test for fan2 */ 470 #define ADT7462_FAN_FREE3 0x04 /* Start freewheeling test for fan3 */ 471 #define ADT7462_FAN_FREE4 0x08 /* Start freewheeling test for fan4 */ 472 #define ADT7462_FAN_FREE5 0x10 /* Start freewheeling test for fan5 */ 473 #define ADT7462_FAN_FREE6 0x20 /* Start freewheeling test for fan6 */ 474 #define ADT7462_FAN_FREE7 0x40 /* Start freewheeling test for fan7 */ 475 #define ADT7462_FAN_FREE8 0x80 /* Start freewheeling test for fan8 */ 476 477 /* 0x21 - 0x24 : PWM configuration registers */ 478 #define ADT7462_PWM_CFG(x) (0x21 + x) 479 #define ADT7462_PWM_SPIN_TIMEO 0x07 /* Fan startup and test timeout */ 480 #define ADT7462_PWM_SLOW 0x08 /* Slow en. acoustics mode start*/ 481 #define ADT7462_PWM_INV 0x10 /* PWM output 0 = low, 1 = high */ 482 #define ADT7462_PWM_BHVR_MASK 0xe0 /* PWM control channel mask */ 483 #define ADT7462_PWM_BHVR_SHFT 5 /* PWM control channel shift */ 484 #define ADT7462_PWM_BHVR_LOCAL 0x00 /* PWM control = local */ 485 #define ADT7462_PWM_BHVR_REM1 0x20 /* PWM control = remote 1 */ 486 #define ADT7462_PWM_BHVR_REM2 0x40 /* PWM control = remote 2 */ 487 #define ADT7462_PWM_BHVR_REM3 0x60 /* PWM control = remote 3 */ 488 #define ADT7462_PWM_BHVR_OFF 0x80 /* PWM control = off */ 489 #define ADT7462_PWM_BHVR_LR3 0xa0 /* PWM control = local + rem 3 */ 490 #define ADT7462_PWM_BHVR_ALL 0xc0 /* PWM control = local + rem 1/2/3 */ 491 #define ADT7462_PWM_BHVR_MAN 0xe0 /* PWM control = manual */ 492 493 /* 0x25: PWM1, PWM2 frequency */ 494 #define ADT7462_PWM1_TMIN 0x01 /* PWM1 is off or min at Tmin */ 495 #define ADT7462_PWM2_TMIN 0x02 /* PWM2 is off or min at Tmin */ 496 #define ADT7462_PWM1_LFREQ 0x1c /* PWM1 low frequency mask */ 497 #define ADT7462_PWM2_LFREQ 0xe0 /* PWM2 low frequency mask */ 498 499 /* 0x26: PWM3, PWM4 frequency */ 500 #define ADT7462_PWM3_TMIN 0x01 /* PWM3 is off or min at Tmin */ 501 #define ADT7462_PWM4_TMIN 0x02 /* PWM4 is off or min at Tmin */ 502 #define ADT7462_PWM3_LFREQ 0x1c /* PWM3 low frequency mask */ 503 #define ADT7462_PWM4_LFREQ 0xe0 /* PWM4 low frequency mask */ 504 505 /* 0x30: Thermal mask register 1 */ 506 #define ADT7462_MASK_LOCAL 0x02 /* Mask local temp. out of limit */ 507 #define ADT7462_MASK_REMOTE1 0x04 /* Mask remote1 temp. out of limit */ 508 #define ADT7462_MASK_REMOTE2 0x08 /* Mask remote2 temp. out of limit */ 509 #define ADT7462_MASK_REMOTE3 0x10 /* Mask remote3 temp. out of limit */ 510 #define ADT7462_MASK_DIODE1 0x20 /* Mask remote1 temp. error */ 511 #define ADT7462_MASK_DIODE2 0x40 /* Mask remote2 temp. error */ 512 #define ADT7462_MASK_DIODE3 0x80 /* Mask remote3 temp. error */ 513 514 /* 0x31: Thermal mask register 2 */ 515 #define ADT7462_MASK_TH1_PCT 0x01 /* Mask therm1 percent alert */ 516 #define ADT7462_MASK_TH1_ASRT 0x02 /* Mask therm1 assert */ 517 #define ADT7462_MASK_TH1_STAT 0x04 /* Mask therm1 state alert */ 518 #define ADT7462_MASK_TH2_PCT 0x08 /* Mask therm2 percent alert */ 519 #define ADT7462_MASK_TH2_ASRT 0x10 /* Mask therm2 assert */ 520 #define ADT7462_MASK_TH2_STAT 0x20 /* Mask therm2 state alert */ 521 #define ADT7462_MASK_VRD1 0x40 /* Mask VRD1 assert */ 522 #define ADT7462_MASK_VRD2 0x80 /* Mask VRD2 assert */ 523 524 /* 0x32: Voltage mask register 1 */ 525 #define ADT7462_MASK_12V1 0x01 /* Mask 12V1 alert */ 526 #define ADT7462_MASK_12V2 0x02 /* Mask 12V2 alert */ 527 #define ADT7462_MASK_12V3 0x04 /* Mask 12V3 alert */ 528 #define ADT7462_MASK_33V 0x08 /* Mask 3.3V alert */ 529 #define ADT7462_MASK_PIN15V 0x10 /* Mask pin15v alert */ 530 #define ADT7462_MASK_PIN19V 0x20 /* Mask pin19v alert */ 531 #define ADT7462_MASK_5V 0x40 /* Mask 5V alert */ 532 #define ADT7462_MASK_PIN23V 0x80 /* Mask pin23v alert */ 533 534 /* 0x33: Voltage mask register 2 */ 535 #define ADT7462_MASK_PIN24V 0x08 /* Mask pin24v alert */ 536 #define ADT7462_MASK_PIN25V 0x10 /* Mask pin25v alert */ 537 #define ADT7462_MASK_PIN26V 0x20 /* Mask pin26v alert */ 538 #define ADT7462_MASK_15V2 0x40 /* Mask 1.5V2 alert */ 539 #define ADT7462_MASK_15V1 0x80 /* Mask 1.5V1 alert */ 540 541 /* 0x34: Fan mask register */ 542 #define ADT7462_MASK_FAN1_FAULT 0x01 /* Mask fan1 fault */ 543 #define ADT7462_MASK_FAN2_FAULT 0x02 /* Mask fan2 fault */ 544 #define ADT7462_MASK_FAN3_FAULT 0x04 /* Mask fan3 fault */ 545 #define ADT7462_MASK_FAN4_FAULT 0x08 /* Mask fan4 fault */ 546 #define ADT7462_MASK_FAN5_FAULT 0x10 /* Mask fan5 fault */ 547 #define ADT7462_MASK_FAN6_FAULT 0x20 /* Mask fan6 fault */ 548 #define ADT7462_MASK_FAN7_FAULT 0x40 /* Mask fan7 fault */ 549 #define ADT7462_MASK_FAN8_FAULT 0x80 /* Mask fan8 fault */ 550 551 /* 0x35: Digital mask register */ 552 #define ADT7462_MASK_FAN2MAX 0x08 /* Mask fan2max alert */ 553 #define ADT7462_MASK_SCSI1 0x10 /* Mask SCSI1 alert */ 554 #define ADT7462_MASK_SCSI2 0x20 /* Mask SCSI2 alert */ 555 #define ADT7462_MASK_VID 0x40 /* Mask VID comparison alert */ 556 #define ADT7462_MASK_CHASSIS 0x80 /* Mask chassis intrusion alert */ 557 558 /* 0x36: GPIO mask register */ 559 #define ADT7462_MASK_GPIO1_FLT 0x01 /* Mask GPIO1 fault */ 560 #define ADT7462_MASK_GPIO2_FLT 0x02 /* Mask GPIO2 fault */ 561 #define ADT7462_MASK_GPIO3_FLT 0x04 /* Mask GPIO3 fault */ 562 #define ADT7462_MASK_GPIO4_FLT 0x08 /* Mask GPIO4 fault */ 563 #define ADT7462_MASK_GPIO5_FLT 0x10 /* Mask GPIO5 fault */ 564 #define ADT7462_MASK_GPIO6_FLT 0x20 /* Mask GPIO6 fault */ 565 #define ADT7462_MASK_GPIO7_FLT 0x40 /* Mask GPIO7 fault */ 566 #define ADT7462_MASK_GPIO8_FLT 0x80 /* Mask GPIO8 fault */ 567 568 /* 0x36: EDO mask register 1 */ 569 #define ADT7462_EDO1_GPIO1 0x01 /* Mask GPIO1 for EDO1 */ 570 #define ADT7462_EDO1_GPIO2 0x02 /* Mask GPIO2 for EDO1 */ 571 #define ADT7462_EDO1_GPIO3 0x04 /* Mask GPIO3 for EDO1 */ 572 #define ADT7462_EDO1_GPIO4 0x08 /* Mask GPIO4 for EDO1 */ 573 #define ADT7462_EDO1_FAN 0x20 /* Mask fan fault for EDO1 */ 574 #define ADT7462_EDO1_TEMP 0x40 /* Mask therm for EDO1 */ 575 #define ADT7462_EDO2_VOLT 0x80 /* Mask volt limit for EDO1 */ 576 577 /* 0x36: EDO mask register 2 */ 578 #define ADT7462_EDO2_GPIO1 0x01 /* Mask GPIO1 for EDO2 */ 579 #define ADT7462_EDO2_GPIO2 0x02 /* Mask GPIO2 for EDO2 */ 580 #define ADT7462_EDO2_GPIO3 0x04 /* Mask GPIO3 for EDO2 */ 581 #define ADT7462_EDO2_GPIO4 0x08 /* Mask GPIO4 for EDO2 */ 582 #define ADT7462_EDO2_FAN 0x20 /* Mask fan fault for EDO2 */ 583 #define ADT7462_EDO2_TEMP 0x40 /* Mask therm for EDO2 */ 584 #define ADT7462_EDO2_VOLT 0x80 /* Mask volt limit for EDO2 */ 585 586 /* 0x3d: Device ID register */ 587 #define ADT7462_DEV_ID_VAL 0x62 /* ADT7462 device ID */ 588 589 /* 0x3e: Company ID register */ 590 #define ADT7462_COMP_ID_VAL 0x41 /* ADT7462 company ID */ 591 592 /* 0x3f: Revision ID register */ 593 #define ADT7462_REV_ID_VAL 0x04 /* ADT7462 revision ID */ 594 595 /* 0x44 - 0x53: Temperature limit registers: -64'C + value */ 596 #define ADT7462_TEMP_BASE 209150000 597 #define ADT7462_TEMP_OFFSET 64 598 #define ADT7462_TEMP_LOW(x) (0x44 + x) 599 #define ADT7462_TEMP_HIGH(x) (0x48 + x) 600 #define ADT7462_TEMP_THERM1(x) (0x4c + x) 601 #define ADT7462_TEMP_THERM2(x) (0x50 + x) 602 603 /* 0x54 - Local/remote 1 temperature hysteresis */ 604 #define ADT7462_REMOTE1_TH_HYST 0x0f /* Remote 1 therm hyst. (0 - 15) */ 605 #define ADT7462_LOCAL_TH_HYST 0xf0 /* Local therm hyst. (0 - 15) */ 606 607 /* 0x55 - Remote 2/remote 3 temperature hysteresis */ 608 #define ADT7462_REMOTE3_TH_HYST 0x0f /* Remote 3 therm hyst. (0 - 15) */ 609 #define ADT7462_REMOTE2_TH_HYST 0xf0 /* Remote 2 therm hyst. (0 - 15) */ 610 611 /* 0x56 - 0x59: Offset registers: resolution = 0.5'C */ 612 613 /* 0x5a - 0x5b: Operating point registers */ 614 #define ADT7462_OP_POINT(x) (0x59 + x) /* Only remote 1 and 2 */ 615 616 /* 0x5c - 0x5f: Tmin registers */ 617 #define ADT7462_TMIN(x) (0x5c + x) 618 619 /* 0x60 - 0x63: Trange/Hysteresis registers */ 620 #define ADT7462_HYST_TRANGE(x) (0x60 + x) 621 #define ADT7462_HTR_HYST_MASK 0x0f /* Auto fan loop hyst. (0-15) */ 622 #define ADT7462_HTR_RNGE_MASK 0xf0 /* Trange value (2 - 80) */ 623 #define ADT7462_HTR_RNGE_SHFT 4 /* Trange shift */ 624 625 /* 0x64: Operating point hysteresis */ 626 #define ADT7462_OPT_HYST 0xf0 /* Tmin loop hyst. (0 - 15) */ 627 628 /* 0x68 - 0x77: Voltage limit registers */ 629 630 /* 0x78 - 0x7f: Tach limit registers */ 631 #define ADT7462_TACH_LIMIT(x) (0x78 + x) 632 633 /* 0x80 - 0x81: Therm timer limit registers */ 634 635 /* 0x88 - 0x8f: Temperature value registers */ 636 #define ADT7462_TEMP_LSB(x) (0x88 + 2 * x) 637 638 /* 0x90 - 0x96: Voltage value registers */ 639 640 /* 0x97: VID value register */ 641 642 /* 0x98 - 0x9f, 0xa2 - 0xa9: Tach value registers */ 643 #define ADT7462_TACH_VAL_LSB(x) (x < 4 ? 0x98 + 2 * x : 0x9a + 2 * x) 644 #define ADT7462_TACH_PERIOD (90000 * 60) 645 646 /* 0xaa - 0xad: PWM current duty cycle registers */ 647 #define ADT7462_PWM_DUTY(x) (0xaa + x) 648 649 /* 0xae - 0xaf: Therm time value registers */ 650 651 /* 0xb8, 0xc0: Host/BMC thermal status register 1 */ 652 #define ADT7462_LOCAL_TRIP 0x02 653 #define ADT7462_REMOTE1_TRIP 0x04 654 #define ADT7462_REMOTE2_TRIP 0x08 655 #define ADT7462_REMOTE3_TRIP 0x10 656 #define ADT7462_DIODE1_ERR 0x20 657 #define ADT7462_DIODE2_ERR 0x40 658 #define ADT7462_DIODE3_ERR 0x80 659 660 /* 0xb9, 0xc1: Host/BMC thermal status register 2 */ 661 #define ADT7462_THERM1_PCT 0x01 662 #define ADT7462_THERM1_ASSERT 0x02 663 #define ADT7462_THERM1_STATE 0x04 664 #define ADT7462_THERM2_PCT 0x08 665 #define ADT7462_THERM2_ASSERT 0x10 666 #define ADT7462_THERM2_STATE 0x20 667 #define ADT7462_VRD1_ASSERT 0x40 668 #define ADT7462_VRD2_ASSERT 0x80 669 670 /* 0xba: Host thermal status register 3 */ 671 #define ADT7462_THERM1_L_EXCD 0x01 672 #define ADT7462_THERM1_R1_EXCD 0x02 673 #define ADT7462_THERM1_R2_EXCD 0x04 674 #define ADT7462_THERM1_R3_EXCD 0x08 675 #define ADT7462_THERM2_L_EXCD 0x10 676 #define ADT7462_THERM2_R1_EXCD 0x20 677 #define ADT7462_THERM2_R2_EXCD 0x40 678 #define ADT7462_THERM2_R3_EXCD 0x80 679 680 /* 0xbb, 0xc3: Host/BMC voltage status register 1 */ 681 #define ADT7462_12V1_TRIP 0x01 682 #define ADT7462_12V2_TRIP 0x02 683 #define ADT7462_12V3_TRIP 0x04 684 #define ADT7462_33V_TRIP 0x08 685 #define ADT7462_PIN15V_TRIP 0x10 686 #define ADT7462_PIN19V_TRIP 0x20 687 #define ADT7462_5V_TRIP 0x40 688 #define ADT7462_PIN23V_TRIP 0x80 689 690 /* 0xbc, 0xc4: Host/BMC voltage status register 2 */ 691 #define ADT7462_PIN24V_TRIP 0x04 692 #define ADT7462_PIN25V_TRIP 0x10 693 #define ADT7462_PIN26V_TRIP 0x20 694 #define ADT7462_15V2_TRIP 0x40 695 #define ADT7462_15V1_TRIP 0x80 696 697 /* 0xbd, 0xc5: Host/BMC fan status register */ 698 #define ADT7462_FAN_FAULT(val, x) (val & (1 << x)) 699 700 /* 0xbe, 0xc6: Host/BMC digital status register */ 701 #define ADT7462_FAN2MAX_ASSERT 0x08 702 #define ADT7462_SCSI1_ASSERT 0x10 703 #define ADT7462_SCSI2_ASSERT 0x20 704 #define ADT7462_VID_COMP_FLT 0x40 705 #define ADT7462_CHASSIS_ASSERT 0x80 706 707 /* 0xbf: Host/BMC GPIO status register */ 708 #define ADT7462_GPIO_ASSERT(val, x) (val & (1 << x)) 709 710 #endif /* _DEV_I2C_ADT7462REG_H_ */ 711
Indexes created Fri Sep 18 00:27:12 UTC 2026