Home | History | Annotate | Line # | Download | only in i2c
      1 /*	$NetBSD: ds2482owreg.h,v 1.1 2024/11/04 20:43:38 brad Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2024 Brad Spencer <brad (at) anduin.eldar.org>
      5  *
      6  * Permission to use, copy, modify, and distribute this software for any
      7  * purpose with or without fee is hereby granted, provided that the above
      8  * copyright notice and this permission notice appear in all copies.
      9  *
     10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     17  */
     18 
     19 #ifndef _DEV_I2C_DS2482REG_H_
     20 #define _DEV_I2C_DS2482REG_H_
     21 
     22 #define DS2482_LOWEST_ADDR		0x18
     23 #define DS2482_HIGHEST_ADDR		0x1F
     24 
     25 #define DS2482_DEVICE_RESET		0xF0
     26 #define DS2482_SET_READ_POINTER		0xE1
     27 #define 	DS2482_REGISTER_STATUS	0xF0
     28 #define			DS2482_STATUS_1WB	0x01
     29 #define			DS2482_STATUS_PPD	0x02
     30 #define			DS2482_STATUS_SD	0x04
     31 #define			DS2482_STATUS_LL	0x08
     32 #define			DS2482_STATUS_RST	0x10
     33 #define			DS2482_STATUS_SBR	0x20
     34 #define				DS2482_STATUS_SBR_SHIFT	5
     35 #define			DS2482_STATUS_TSB	0x40
     36 #define			DS2482_STATUS_DIR	0x80
     37 #define		DS2482_REGISTER_DATA	0xE1
     38 #define		DS2482_REGISTER_CONFIG	0xC3
     39 #define		DS2482_REGISTER_CHANNEL	0xD2 /* DS2482-800 only */
     40 #define DS2482_WRITE_CONFIG		0xD2
     41 #define		DS2482_CONFIG_1WS	0x08
     42 #define		DS2482_CONFIG_SPU	0x04
     43 #define		DS2482_CONFIG_APU	0x01
     44 #define DS2482_SELECT_CHANNEL		0xC3 /* DS2482-800 only */
     45 #define 	DS2482_CHANNEL_IO0	0xF0
     46 #define 	DS2482_CHANNEL_IO1	0xE1
     47 #define 	DS2482_CHANNEL_IO2	0xD2
     48 #define 	DS2482_CHANNEL_IO3	0xC3
     49 #define 	DS2482_CHANNEL_IO4	0xB4
     50 #define 	DS2482_CHANNEL_IO5	0xA5
     51 #define 	DS2482_CHANNEL_IO6	0x96
     52 #define 	DS2482_CHANNEL_IO7	0x87
     53 #define DS2482_ONEWIRE_RESET		0xB4
     54 #define DS2482_ONEWIRE_SINGLE_BIT	0x87
     55 #define		DS2482_ONEWIRE_BIT_ZERO		0x00
     56 #define		DS2482_ONEWIRE_BIT_ONE		0x80
     57 #define DS2482_ONEWIRE_WRITE_BYTE	0xA5
     58 #define DS2482_ONEWIRE_READ_BYTE	0x96
     59 #define DS2482_ONEWIRE_TRIPLET		0x78
     60 #define		DS2482_TRIPLET_DIR_ZERO 0x00
     61 #define		DS2482_TRIPLET_DIR_ONE	0x80
     62 
     63 #endif
     64