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      1 /* $NetBSD: motoi2creg.h,v 1.3 2014/10/07 21:32:10 matt Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2007, 2010 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Matt Thomas.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _DEV_I2C_MOTOI2CREG_H_
     33 #define _DEV_I2C_MOTOI2CREG_H_
     34 
     35 /*
     36  * This I2C controller is a common design used on many Motorola/Freescale
     37  * chip like the i.MX/MC9328, MPC8548, etc.  Different names in bit field
     38  * definition and not suffered from document error.
     39  */
     40 #define I2CADR	0x0000	/* my own I2C addr to respond for an external master */
     41 #define I2CFDR	0x0004	/* frequency devider */
     42 #define I2CCR	0x0008	/* control */
     43 #define	 CR_MEN   0x80	/* enable this HW */
     44 #define	 CR_MIEN  0x40	/* enable interrupt */
     45 #define	 CR_MSTA  0x20	/* 0->1 activates START, 1->0 makes STOP condition */
     46 #define	 CR_MTX   0x10	/* 1 for Tx, 0 for Rx */
     47 #define	 CR_TXAK  0x08	/* 1 makes no acknowledge when Rx */
     48 #define	 CR_RSTA  0x04	/* generate repeated START condition */
     49 #define I2CSR	0x000c	/* status */
     50 #define	 SR_MCF   0x80	/* 0 means transfer in progress, 1 when completed */
     51 #define	 SR_MAAS  0x40	/* 1 means addressed as slave */
     52 #define	 SR_MBB   0x20	/* 1 before STOP condition is detected */
     53 #define	 SR_MAL   0x10	/* arbitration was lost */
     54 #define	 SR_MIF   0x02	/* indicates data transter completion */
     55 #define	 SR_RXAK  0x01	/* 1 to indicate receive has completed */
     56 #define I2CDR	0x0010	/* data */
     57 #define	I2CDFSRR 0x0014	/* digital filter sampling rate register */
     58 
     59 /*
     60  * The equation to calculate the divider frequency (from AN2919) is:
     61  *
     62  * Frequency divider = B * (A + (floor(3 * C / B) * 2))
     63  *
     64  * where (in little endian bit order, msb to lsb) FDR is split into 2 3-bit
     65  * fields: fA contains bits 5,1,0 and fB contains bits 4,3,2.
     66  *
     67  * A is used as an index into { 9, 10, 12, 15, 5, 6, 7, 8 } though
     68  * on faster machines these are doubled to { 18, 20, 24, 50, 10, 12, 14, 16 }.
     69  * B is either 2**(b + 1) or 2**(b + 4).
     70  *
     71  * C is the sampling rate, which may be settable via I2CDFSRR register though
     72  * not all implementations have it.  Regardless, we just leave it at its
     73  * default setting (16).  So floor(3 * C / B) * 2 becomes a precomputable
     74  * quantity.  Once we know its value for fB=0, we can simply shift it right
     75  * as fB increases since B is a power-of-2.
     76  */
     77 
     78 #define FDR_A(n)		(((n) & 0x20) >> 3) | ((n) & 3))
     79 #define FDR_B(n)		(((n) & 0x1c) >> 2)
     80 
     81 #define	MOTOI2C_GROUP_A_VALUES	0x8765fca9U
     82 #define	MOTOI2C_A(a)		((MOTOI2C_GROUP_A_VALUE >> (4*(a))) & 0xf)
     83 #define	MOTOI2C_B(b)		(1 + (b))
     84 #define	MOTOI2C_DIV(name, fdr)	\
     85 	((name##_A(FDR_A(fdr)) + named##_C(FDR_B(fdr))) << name##_B(FDR_B(fdr)))
     86 
     87 #define	IMX31_A(fdr_a)		MOTOI2C_A(fdr_a)
     88 #define	IMX31_B(fdr_b)		MOTOI2C_B(fdr_b)
     89 #define IMX31_C(fdr_b)		(6 >> (fdr_b))
     90 #define	IMX31_DIV(fdr)		MOTOI2C_DIV(IMX31, fdr)
     91 
     92 #define	MCF52259_A(fdr_a)	MOTOI2C_A(fdr_a)
     93 #define	MCF52259_B(fdr_b)	MOTOI2C_B(fdr_b)
     94 #define MCF52259_C(fdr_b)	(5 >> (fdr_b))
     95 #define	MCF52259_DIV(fdr)	MOTOI2C_DIV(MCF52259, fdr)
     96 
     97 #define	MPC85xx_A(fdr_a)	(MOTOI2C_A(fdr_a) << 1)
     98 #define	MPC85xx_B(fdr_b)	(4 + (fdr_b))
     99 #define	MPC85xx_C(fdr_b)	((6 >> (fdr_b)) & ~1)
    100 #define	MPC85xx_DIV(fdr)	MOTOI2C_DIV(MPC85xx, fdr)
    101 
    102 #endif /* !_DEV_I2C_MOTOI2CREG_H_ */
    103