1 /* $NetBSD: r2025reg.h,v 1.1 2006/03/06 19:55:08 shige Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer in the documentation and/or other materials provided 17 * with the distribution. 18 * 3. The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _DEV_I2C_R2025REG_H_ 36 #define _DEV_I2C_R2025REG_H_ 37 38 /* 39 * R2025S/D Real-Time Clock 40 */ 41 42 /* I2C Slave Address */ 43 #define R2025_ADDR 0x32 44 45 /* Register size */ 46 #define R2025_REG_SIZE 16 47 48 #define R2025_CLK_SIZE 7 /* 7bytes: 0x0-0x6 */ 49 50 /* Registers */ 51 #define R2025_REG_SEC 0x0 52 #define R2025_REG_MIN 0x1 53 #define R2025_REG_HOUR 0x2 54 #define R2025_REG_WDAY 0x3 55 #define R2025_REG_DAY 0x4 56 #define R2025_REG_MON 0x5 57 #define R2025_REG_YEAR 0x6 58 #define R2025_REG_CORRECTCLOCK 0x7 59 #define R2025_REG_ALARMW_MIN 0x8 60 #define R2025_REG_ALARMW_HOUR 0x9 61 #define R2025_REG_ALARMW_WDAY 0xa 62 #define R2025_REG_ALARMD_MIN 0xb 63 #define R2025_REG_ALARMD_HOUR 0xc 64 #define R2025_REG_RESERVED 0xd 65 #define R2025_REG_CTRL1 0xe 66 #define R2025_REG_CTRL2 0xf 67 68 69 /* Register mask */ 70 #define R2025_REG_SEC_MASK 0x7f 71 #define R2025_REG_MIN_MASK 0x7f 72 #define R2025_REG_HOUR_MASK 0x3f 73 #define R2025_REG_WDAY_MASK 0x07 74 #define R2025_REG_DAY_MASK 0x3f 75 #define R2025_REG_MON_MASK 0x1f 76 #define R2025_REG_YEAR_MASK 0xff 77 #define R2025_REG_CORRECTCLOCK_MASK 0x7f 78 #define R2025_REG_ALARMW_MIN_MASK 0x7f 79 #define R2025_REG_ALARMW_HOUR_MASK 0x3f 80 #define R2025_REG_ALARMW_WDAY_MASK 0x7f 81 #define R2025_REG_ALARMD_MIN_MASK 0x7f 82 #define R2025_REG_ALARMD_HOUR_MASK 0x3f 83 #define R2025_REG_CTRL1_MASK 0xff 84 #define R2025_REG_CTRL2_MASK 0xff 85 86 /* Register flag: R2025_MON */ 87 #define R2025_REG_MON_Y1920 (1u << 7) 88 89 /* Register flag: R2025_CTRL1 */ 90 #define R2025_REG_CTRL1_WALE (1u << 7) 91 #define R2025_REG_CTRL1_DALE (1u << 6) 92 #define R2025_REG_CTRL1_H1224 (1u << 5) 93 #define R2025_REG_CTRL1_CLEN2 (1u << 4) 94 #define R2025_REG_CTRL1_TEST (1u << 3) 95 #define R2025_REG_CTRL1_CT2 (1u << 2) 96 #define R2025_REG_CTRL1_CT1 (1u << 1) 97 #define R2025_REG_CTRL1_CT0 (1u << 0) 98 99 /* Register flag: R2025_CTRL2 */ 100 #define R2025_REG_CTRL2_VDSL (1u << 7) 101 #define R2025_REG_CTRL2_VDET (1u << 6) 102 #define R2025_REG_CTRL2_XST (1u << 5) 103 #define R2025_REG_CTRL2_PON (1u << 4) 104 #define R2025_REG_CTRL2_CLEN1 (1u << 3) 105 #define R2025_REG_CTRL2_CTFG (1u << 2) 106 #define R2025_REG_CTRL2_WAFG (1u << 1) 107 #define R2025_REG_CTRL2_DAFG (1u << 0) 108 109 #endif /* _DEV_I2C_R2025REG_H_ */ 110
Indexes created Sat Sep 20 22:09:52 GMT 2025