1 /* $NetBSD: w83795greg.h,v 1.1 2013/08/06 15:58:25 soren Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Soren S. Jorvang. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Nuvoton_W83795G_W83795ADG_Datasheet_V1.43.pdf 30 */ 31 32 #define W83795G_BANKSEL 0x00 /* Bank Selection */ 33 #define BANKSEL_HBACS 0x80 34 #define BANKSEL_BANK 0x07 35 36 /* 37 * Bank 0 registers 38 */ 39 #define W83795G_CONFIG 0x01 /* Configuration */ 40 #define CONFIG_START 0x01 41 #define CONFIG_INT_CLEAR 0x02 42 #define CONFIG_CONFIG48 0x04 43 #define CONFIG_CLKSEL 0x18 44 #define CONFIG_RST_VDD_MD 0x20 45 #define CONFIG_SYS_RST_MD 0x40 46 #define CONFIG_INIT 0x80 47 48 #define W83795G_V_CTRL1 0x02 /* Voltage monitoring control */ 49 #define W83795G_V_CTRL2 0x03 /* Voltage monitoring control */ 50 #define W83795G_T_CTRL1 0x04 /* Temp monitoring control */ 51 #define W83795G_T_CTRL2 0x05 /* Temp monitoring control */ 52 #define W83795G_F_CTRL1 0x06 /* FANIN monitoring control */ 53 #define W83795G_F_CTRL2 0x07 /* FANIN monitoring control */ 54 #define W83795G_VMIGB_C 0x08 /* 8x voltage input gain control */ 55 #define VMIGB_C_GAIN_VDSEN14 0x01 56 #define VMIGB_C_GAIN_VDSEN15 0x02 57 #define VMIGB_C_GAIN_VDSEN16 0x04 58 #define VMIGB_C_GAIN_VDSEN17 0x08 59 #define W83795G_GPIO_M 0x09 /* GPIO I/O mode control */ 60 #define W83795G_GPIO_I 0x0a /* GPIO input data */ 61 #define W83795G_GPIO_O 0x0b /* GPIO output data */ 62 63 #define W83795G_WDTLOCK 0x0c /* Lock Watch Dog */ 64 #define WDTLOCK_ENABLE_SOFT 0x55 65 #define WDTLOCK_DISABLE_SOFT 0xaa 66 #define WDTLOCK_ENABLE_HARD 0x33 67 #define WDTLOCK_DISABLE_HARD 0xcc 68 69 #define W83795G_WDT_ENA 0x0d /* Watch Dog Enable */ 70 #define WDT_ENA_SOFT 0x01 71 #define WDT_ENA_HARD 0x02 72 #define WDT_ENA_ENWDT 0x04 73 74 #define W83795G_WDT_STS 0x0e /* Watch Dog Status */ 75 #define WDT_STS_SOFT_TO 0x01 76 #define WDT_STS_HARD_TO 0x02 77 #define WDT_STS_WDT_ST 0x0c 78 79 #define W83795G_WDT_CNT 0x0f /* Watch Dog Timeout Counter */ 80 81 #define W83795G_VSEN1 0x10 82 #define W83795G_VSEN2 0x11 83 #define W83795G_VSEN3 0x12 84 #define W83795G_VSEN4 0x13 85 #define W83795G_VSEN5 0x14 86 #define W83795G_VSEN6 0x15 87 #define W83795G_VSEN7 0x16 88 #define W83795G_VSEN8 0x17 89 #define W83795G_VSEN9 0x18 90 #define W83795G_VSEN10 0x19 91 #define W83795G_VSEN11 0x1a 92 #define W83795G_VTT 0x1b 93 #define W83795G_3VDD 0x1c 94 #define W83795G_3VSB 0x1d 95 #define W83795G_VBAT 0x1e 96 #define W83795G_TR5 0x1f 97 #define W83795G_VSEN12 W83795G_TR5 98 #define W83795G_TR6 0x20 99 #define W83795G_VSEN13 W83795G_TR6 100 #define W83795G_TD1 0x21 101 #define W83795G_TR1 W83795G_TD1 102 #define W83795G_VDSEN14 W83795G_TD1 103 #define W83795G_TD2 0x22 104 #define W83795G_TR2 W83795G_TD2 105 #define W83795G_VDSEN15 W83795G_TD2 106 #define W83795G_TD3 0x23 107 #define W83795G_TR3 W83795G_TD3 108 #define W83795G_VDSEN16 W83795G_TD3 109 #define W83795G_TD4 0x24 110 #define W83795G_TR4 W83795G_TD4 111 #define W83795G_VDSEN17 W83795G_TD4 112 #define W83795G_DTS1 0x26 113 #define W83795G_DTS2 0x27 114 #define W83795G_DTS3 0x28 115 #define W83795G_DTS4 0x29 116 #define W83795G_DTS5 0x2a 117 #define W83795G_DTS6 0x2b 118 #define W83795G_DTS7 0x2c 119 #define W83795G_DTS8 0x2d 120 #define W83795G_FANIN1 0x2e 121 #define W83795G_FANIN2 0x2f 122 #define W83795G_FANIN3 0x30 123 #define W83795G_FANIN4 0x31 124 #define W83795G_FANIN5 0x32 125 #define W83795G_FANIN6 0x33 126 #define W83795G_FANIN7 0x34 127 #define W83795G_FANIN8 0x35 128 #define W83795G_FANIN9 0x36 129 #define W83795G_FANIN10 0x37 130 #define W83795G_FANIN11 0x38 131 #define W83795G_FANIN12 0x39 132 #define W83795G_FANIN13 0x3a 133 #define W83795G_FANIN14 0x3b 134 #define W83795G_VR_LSB 0x3c /* Monitored Channel Readout Low Byte */ 135 136 #define W83795G_SMICTRL 0x40 /* SMI Control */ 137 #define W83795G_SMISTS1 0x41 /* SMI Status 1 */ 138 #define W83795G_SMISTS2 0x42 /* SMI Status 2 */ 139 #define W83795G_SMISTS3 0x43 /* SMI Status 3 */ 140 #define W83795G_SMISTS4 0x44 /* SMI Status 4 */ 141 #define W83795G_SMISTS5 0x45 /* SMI Status 5 */ 142 #define W83795G_SMISTS6 0x46 /* SMI Status 6 */ 143 #define W83795G_SMISTS7 0x47 /* SMI Status 7 */ 144 #define W83795G_SMIMSK1 0x48 /* SMI Mask 1 */ 145 #define W83795G_SMIMSK2 0x49 /* SMI Mask 2 */ 146 #define W83795G_SMIMSK3 0x4a /* SMI Mask 3 */ 147 #define W83795G_SMIMSK4 0x4b /* SMI Mask 4 */ 148 #define W83795G_SMIMSK5 0x4c /* SMI Mask 5 */ 149 #define W83795G_SMIMSK6 0x4d /* SMI Mask 6 */ 150 #define W83795G_SMIMSK7 0x4e /* SMI Mask 7 */ 151 #define W83795G_BEEP1 0x50 /* BEEP Control 1 */ 152 #define W83795G_BEEP2 0x51 /* BEEP Control 1 */ 153 #define W83795G_BEEP3 0x52 /* BEEP Control 2 */ 154 #define W83795G_BEEP4 0x53 /* BEEP Control 3 */ 155 #define W83795G_BEEP5 0x54 /* BEEP Control 4 */ 156 #define W83795G_BEEP6 0x55 /* BEEP Control 5 */ 157 #define W83795G_OVT_GLB 0x58 /* OVT Global Enable */ 158 #define W83795G_OVT1_C1 0x59 /* OVT1 Control 1 */ 159 #define W83795G_OVT1_C2 0x5a /* OVT1 Control 1 */ 160 #define W83795G_OVT2_C1 0x5b /* OVT2 Control 1 */ 161 #define W83795G_OVT2_C2 0x5c /* OVT2 Control 1 */ 162 #define W83795G_OVT3_C1 0x5d /* OVT3 Control 1 */ 163 #define W83795G_OVT3_C2 0x5e /* OVT3 Control 1 */ 164 #define W83795G_THERM 0x5f /* THERMTRIP Control/Status */ 165 #define W83795G_PROCSTS 0x60 /* PROCHOT Processor Hot Status */ 166 #define W83795G_PROC1 0x61 /* PROCHOT1# Processor Hot Control */ 167 #define W83795G_PROC2 0x62 /* PROCHOT2# Processor Hot Control */ 168 #define W83795G_PROC3 0x63 /* PROCHOT3# Processor Hot Control */ 169 #define W83795G_PROC4 0x64 /* PROCHOT4# Processor Hot Control */ 170 #define W83795G_VFAULT1 0x65 /* VOLT_FAULT# Control 1 */ 171 #define W83795G_VFAULT2 0x66 /* VOLT_FAULT# Control 2 */ 172 #define W83795G_VFAULT3 0x67 /* VOLT_FAULT# Control 3 */ 173 #define W83795G_FFAULT1 0x68 /* FAN_FAULT# Control 1 */ 174 #define W83795G_FFAULT2 0x69 /* FAN_FAULT# Control 2 */ 175 #define W83795G_VIDCTRL 0x6a /* VID Control */ 176 #define W83795G_DVID_HI 0x6b /* Dynamic VID High Tolerance */ 177 #define W83795G_DVID_LO 0x6c /* Dynamic VID Low Tolerance */ 178 #define W83795G_V1VIDIN 0x6d /* VSEN1 VID Input Value */ 179 #define W83795G_V2VIDIN 0x6e /* VSEN2 VID Input Value */ 180 #define W83795G_V3VIDIN 0x6f /* VSEN3 VID Input Value */ 181 182 #define W83795G_VSEN1HL 0x70 183 #define W83795G_VSEN1LL 0x71 184 #define W83795G_VSEN2HL 0x72 185 #define W83795G_VSEN2LL 0x73 186 #define W83795G_VSEN3HL 0x74 187 #define W83795G_VSEN3LL 0x75 188 #define W83795G_VSEN4HL 0x76 189 #define W83795G_VSEN4LL 0x77 190 #define W83795G_VSEN5HL 0x78 191 #define W83795G_VSEN5LL 0x79 192 #define W83795G_VSEN6HL 0x7a 193 #define W83795G_VSEN6LL 0x7b 194 #define W83795G_VSEN7HL 0x7c 195 #define W83795G_VSEN7LL 0x7d 196 #define W83795G_VSEN8HL 0x7e 197 #define W83795G_VSEN8LL 0x7f 198 #define W83795G_VSEN9HL 0x80 199 #define W83795G_VSEN9LL 0x81 200 #define W83795G_VSEN10H 0x82 201 #define W83795G_VSEN10L 0x83 202 #define W83795G_VSEN11H 0x84 203 #define W83795G_VSEN11L 0x85 204 #define W83795G_VTT_HL 0x86 205 #define W83795G_VTT_LL 0x87 206 #define W83795G_3VDD_HL 0x88 207 #define W83795G_3VDD_LL 0x89 208 #define W83795G_3VSB_HL 0x8a 209 #define W83795G_3VSB_LL 0x8b 210 #define W83795G_VBAT_HL 0x8c 211 #define W83795G_VBAT_LL 0x8d 212 #define W83795G_V1H_LSB 0x8e 213 #define W83795G_V1L_LSB 0x8f 214 #define W83795G_V2H_LSB 0x90 215 #define W83795G_V2L_LSB 0x91 216 #define W83795G_V3H_LSB 0x92 217 #define W83795G_V3L_LSB 0x93 218 #define W83795G_V4H_LSB 0x94 219 #define W83795G_V4L_LSB 0x95 220 #define W83795G_TD1CRIT 0x96 221 #define W83795G_VD14_HL W83795G_TD1CRIT 222 #define W83795G_TD1CRTH 0x97 223 #define W83795G_VD14_LL W83795G_TD1CRTH 224 #define W83795G_TD1WARN 0x98 225 #define W83795G_VD14HLL W83795G_TD1WARN 226 #define W83795G_TD1WRNH 0x99 227 #define W83795G_VD14LLL W83795G_TD1WRNH 228 #define W83795G_TD2CRIT 0x9a 229 #define W83795G_VD15_HL W83795G_TD2CRIT 230 #define W83795G_TD2CRTH 0x9b 231 #define W83795G_VD15_LL W83795G_TD2CRTH 232 #define W83795G_TD2WARN 0x9c 233 #define W83795G_VD15HLL W83795G_TD2WARN 234 #define W83795G_TD2WRNH 0x9d 235 #define W83795G_VD15LLL W83795G_TD2WRNH 236 #define W83795G_TD3CRIT 0x9e 237 #define W83795G_VD16_HL W83795G_TD3CRIT 238 #define W83795G_TD3CRTH 0x9f 239 #define W83795G_VD16_LL W83795G_TD3CRTH 240 #define W83795G_TD3WARN 0xa0 241 #define W83795G_VD16HLL W83795G_TD3WARN 242 #define W83795G_TD3WRNH 0xa1 243 #define W83795G_VD16LLL W83795G_TD3WRNH 244 #define W83795G_TD4CRIT 0xa2 245 #define W83795G_VD17_HL W83795G_TD4CRIT 246 #define W83795G_TD4CRTH 0xa3 247 #define W83795G_VD17_LL W83795G_TD4CRTH 248 #define W83795G_TD4WARN 0xa4 249 #define W83795G_VD17HLL W83795G_TD4WARN 250 #define W83795G_TD4WRNH 0xa5 251 #define W83795G_VD17LLL W83795G_TD4WRNH 252 #define W83795G_TR5CRIT 0xa6 253 #define W83795G_VS12_HL W83795G_TR5CRIT 254 #define W83795G_TR5CRTH 0xa7 255 #define W83795G_VS12_LL W83795G_TR5CRIH 256 #define W83795G_TR5WARN 0xa8 257 #define W83795G_VS12HLL W83795G_TR5WARN 258 #define W83795G_TR5WRNH 0xa9 259 #define W83795G_VS12LLL W83795G_TR5WRNH 260 #define W83795G_TR6CRIT 0xaa 261 #define W83795G_VS13_HL W83795G_TR6CRIT 262 #define W83795G_TR6CRTH 0xab 263 #define W83795G_VS13_LL W83795G_TR6CRIH 264 #define W83795G_TR6WARN 0xac 265 #define W83795G_VS13HLL W83795G_TR6WARN 266 #define W83795G_TR6WRNH 0xad 267 #define W83795G_VS13LLL W83795G_TR6WRNH 268 #define W83795G_DTSCRIT 0xb2 269 #define W83795G_DTSCRTH 0xb3 270 #define W83795G_DTSWARN 0xb4 271 #define W83795G_DTSWRNH 0xb5 272 #define W83795G_FAN1HL 0xb6 273 #define W83795G_FAN2HL 0xb7 274 #define W83795G_FAN3HL 0xb8 275 #define W83795G_FAN4HL 0xb9 276 #define W83795G_FAN5HL 0xba 277 #define W83795G_FAN6HL 0xbb 278 #define W83795G_FAN7HL 0xbc 279 #define W83795G_FAN8HL 0xbd 280 #define W83795G_FAN9HL 0xbe 281 #define W83795G_FAN10HL 0xbf 282 #define W83795G_FAN11HL 0xc0 283 #define W83795G_FAN12HL 0xc1 284 #define W83795G_FAN13HL 0xc2 285 #define W83795G_FAN14HL 0xc3 286 #define W83795G_FHL1LSB 0xc4 287 #define W83795G_FHL2LSB 0xc5 288 #define W83795G_FHL3LSB 0xc6 289 #define W83795G_FHL4LSB 0xc7 290 #define W83795G_FHL5LSB 0xc8 291 #define W83795G_FHL6LSB 0xc9 292 #define W83795G_FHL7LSB 0xca 293 294 #define W83795G_TD1_OFF 0xd0 295 #define W83795G_TD2_OFF 0xd1 296 #define W83795G_TD3_OFF 0xd2 297 #define W83795G_TD4_OFF 0xd3 298 #define W83795G_TD56OFF 0xd4 299 300 #define W83795G_DEVICE 0xfb /* Nuvoton Device ID */ 301 #define DEVICE_B 0x51 302 #define DEVICE_C 0x52 303 304 #define W83795G_I2CADDR 0xfc /* I2C Address */ 305 #define I2CADDR_MINADDR 0x2c /* Datasheet says 0x58 ! */ 306 #define I2CADDR_MAXADDR 0x2f /* Datasheet says 0x5e ! */ 307 308 #define W83795G_VENDOR 0xfd /* Nuvoton Vendor ID */ 309 #define VENDOR_NUVOTON 0x5c 310 #define VENDOR_NUVOTON_ID_HI 0x5c 311 #define VENDOR_NUVOTON_ID_LO 0xa3 312 313 #define W83795G_CHIP 0xfe /* Nuvoton Chip ID */ 314 #define CHIP_W83795G 0x79 315 316 #define W83795G_DEVICEA 0xff 317 #define DEVICEA_A 0x50 318 319 /* 320 * Bank 1 registers 321 * 322 * UDID/ASF 323 */ 324 325 /* 326 * Bank 2 registers 327 */ 328 #define W83795G_FCMS1 0x01 /* Fan Control Mode Selection */ 329 #define W83795G_T1FMR 0x02 /* Temperature to Fan Mapping */ 330 #define W83795G_T2FMR 0x03 /* Temperature to Fan Mapping */ 331 #define W83795G_T3FMR 0x04 /* Temperature to Fan Mapping */ 332 #define W83795G_T4FMR 0x05 /* Temperature to Fan Mapping */ 333 #define W83795G_T5FMR 0x06 /* Temperature to Fan Mapping */ 334 #define W83795G_T6FMR 0x07 /* Temperature to Fan Mapping */ 335 #define W83795G_FCMS2 0x08 /* Fan Control Mode Selection */ 336 #define W83795G_T12TSS 0x09 /* Temperature Source Selection */ 337 #define W83795G_T34TSS 0x0a /* Temperature Source Selection */ 338 #define W83795G_T56TSS 0x0b /* Temperature Source Selection */ 339 #define W83795G_DFSP 0x0c /* Default Fan Speed at Power-on */ 340 #define W83795G_SFOSUT 0x0d /* SmartFan Output Step Up Time */ 341 #define W83795G_SFOSDT 0x0e /* SmartFan Output Step Down Time */ 342 #define W83795G_FOMC 0x0f /* Fan Output Mode Control */ 343 #define W83795G_F1OV 0x10 /* Fan Output Value */ 344 #define W83795G_F2OV 0x11 /* Fan Output Value */ 345 #define W83795G_F3OV 0x12 /* Fan Output Value */ 346 #define W83795G_F4OV 0x13 /* Fan Output Value */ 347 #define W83795G_F5OV 0x14 /* Fan Output Value */ 348 #define W83795G_F6OV 0x15 /* Fan Output Value */ 349 #define W83795G_F7OV 0x16 /* Fan Output Value */ 350 #define W83795G_F8OV 0x17 /* Fan Output Value */ 351 #define W83795G_F1PFP 0x18 /* Fan Output PWM Frequency Prescalar */ 352 #define W83795G_F2PFP 0x19 /* Fan Output PWM Frequency Prescalar */ 353 #define W83795G_F3PFP 0x1a /* Fan Output PWM Frequency Prescalar */ 354 #define W83795G_FdPFP 0x1b /* Fan Output PWM Frequency Prescalar */ 355 #define W83795G_F5PFP 0x1c /* Fan Output PWM Frequency Prescalar */ 356 #define W83795G_F6PFP 0x1d /* Fan Output PWM Frequency Prescalar */ 357 #define W83795G_F7PFP 0x1e /* Fan Output PWM Frequency Prescalar */ 358 #define W83795G_F8PFP 0x1f /* Fan Output PWM Frequency Prescalar */ 359 #define W83795G_F1OSV 0x20 /* Fan Output Start-up Value */ 360 #define W83795G_F2OSV 0x21 /* Fan Output Start-up Value */ 361 #define W83795G_F3OSV 0x22 /* Fan Output Start-up Value */ 362 #define W83795G_F4OSV 0x23 /* Fan Output Start-up Value */ 363 #define W83795G_F5OSV 0x24 /* Fan Output Start-up Value */ 364 #define W83795G_F6OSV 0x25 /* Fan Output Start-up Value */ 365 #define W83795G_F7OSV 0x26 /* Fan Output Start-up Value */ 366 #define W83795G_F8OSV 0x27 /* Fan Output Start-up Value */ 367 #define W83795G_F1ONV 0x28 /* Fan Output Nonstop Value */ 368 #define W83795G_F2ONV 0x29 /* Fan Output Nonstop Value */ 369 #define W83795G_F3ONV 0x2a /* Fan Output Nonstop Value */ 370 #define W83795G_F4ONV 0x2b /* Fan Output Nonstop Value */ 371 #define W83795G_F5ONV 0x2c /* Fan Output Nonstop Value */ 372 #define W83795G_F6ONV 0x2d /* Fan Output Nonstop Value */ 373 #define W83795G_F7ONV 0x2e /* Fan Output Nonstop Value */ 374 #define W83795G_F8ONV 0x2f /* Fan Output Nonstop Value */ 375 #define W83795G_F1OST 0x30 /* Fan Output Stop Time */ 376 #define W83795G_F2OST 0x31 /* Fan Output Stop Time */ 377 #define W83795G_F3OST 0x32 /* Fan Output Stop Time */ 378 #define W83795G_F4OST 0x33 /* Fan Output Stop Time */ 379 #define W83795G_F5OST 0x34 /* Fan Output Stop Time */ 380 #define W83795G_F6OST 0x35 /* Fan Output Stop Time */ 381 #define W83795G_F7OST 0x36 /* Fan Output Stop Time */ 382 #define W83795G_F8OST 0x37 /* Fan Output Stop Time */ 383 #define W83795G_FOPPC 0x38 /* Fan Output PWM Polarity Control */ 384 #define W83795G_F1TSH 0x40 /* FANIN Target Speed */ 385 #define W83795G_F1TSL 0x41 /* FANIN Target Speed */ 386 #define W83795G_F2TSH 0x42 /* FANIN Target Speed */ 387 #define W83795G_F2TSL 0x43 /* FANIN Target Speed */ 388 #define W83795G_F3TSH 0x44 /* FANIN Target Speed */ 389 #define W83795G_F3TSL 0x45 /* FANIN Target Speed */ 390 #define W83795G_F4TSH 0x46 /* FANIN Target Speed */ 391 #define W83795G_F4TSL 0x47 /* FANIN Target Speed */ 392 #define W83795G_F5TSH 0x48 /* FANIN Target Speed */ 393 #define W83795G_F5TSL 0x49 /* FANIN Target Speed */ 394 #define W83795G_F6TSH 0x4a /* FANIN Target Speed */ 395 #define W83795G_F6TSL 0x4b /* FANIN Target Speed */ 396 #define W83795G_F7TSH 0x4c /* FANIN Target Speed */ 397 #define W83795G_F7TSL 0x4d /* FANIN Target Speed */ 398 #define W83795G_F8TSH 0x4e /* FANIN Target Speed */ 399 #define W83795G_F8TSL 0x4f /* FANIN Target Speed */ 400 #define W83795G_TFTS 0x50 /* Tolerance of FANIN Target Speed */ 401 #define W83795G_T1TTI 0x60 /* Target Temperature of Inputs */ 402 #define W83795G_T2TTI 0x61 /* Target Temperature of Inputs */ 403 #define W83795G_T3TTI 0x62 /* Target Temperature of Inputs */ 404 #define W83795G_T4TTI 0x63 /* Target Temperature of Inputs */ 405 #define W83795G_T5TTI 0x64 /* Target Temperature of Inputs */ 406 #define W83795G_T6TTI 0x65 /* Target Temperature of Inputs */ 407 #define W83795G_T1CTFS 0x68 /* Critical Temperature to Full Speed */ 408 #define W83795G_T2CTFS 0x69 /* Critical Temperature to Full Speed */ 409 #define W83795G_T3CTFS 0x6a /* Critical Temperature to Full Speed */ 410 #define W83795G_T4CTFS 0x6b /* Critical Temperature to Full Speed */ 411 #define W83795G_T5CTFS 0x6c /* Critical Temperature to Full Speed */ 412 #define W83795G_HT1 0x70 /* Hysteresis of Temperature */ 413 #define W83795G_HT2 0x71 /* Hysteresis of Temperature */ 414 #define W83795G_HT3 0x72 /* Hysteresis of Temperature */ 415 #define W83795G_HT4 0x73 /* Hysteresis of Temperature */ 416 #define W83795G_HT5 0x74 /* Hysteresis of Temperature */ 417 #define W83795G_HT6 0x75 /* Hysteresis of Temperature */ 418 #define W83795G_SFIV 0x80 /* SMART FAN IV Temperature Maps */ 419 #define W83795G_CRPE1 0xe0 /* Configuration of PECI Error */ 420 #define W83795G_CRPE2 0xe1 /* Configuration of PECI Error */ 421 #define W83795G_F1OMV 0xe2 /* Fan Output Min Value on PECI Error */ 422 #define W83795G_F2OMV 0xe3 /* Fan Output Min Value on PECI Error */ 423 #define W83795G_F3OMV 0xe4 /* Fan Output Min Value on PECI Error */ 424 #define W83795G_F4OMV 0xe5 /* Fan Output Min Value on PECI Error */ 425 #define W83795G_F5OMV 0xe6 /* Fan Output Min Value on PECI Error */ 426 #define W83795G_F6OMV 0xe7 /* Fan Output Min Value on PECI Error */ 427 #define W83795G_F7OMV 0xe8 /* Fan Output Min Value on PECI Error */ 428 #define W83795G_F8OMV 0xe9 /* Fan Output Min Value on PECI Error */ 429 430 /* 431 * Bank 3 registers 432 * 433 * PECI/SB-TSI 434 */ 435
Indexes created Sun Sep 21 20:09:37 GMT 2025