1 /* $NetBSD: x1226.c,v 1.25 2025/09/07 21:45:16 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima for the NetBSD Project. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Shigeyuki Fukushima. 21 * 4. The name of Shigeyuki Fukushima may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY SHIGEYUKI FUKUSHIMA ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SHIGEYUKI FUKUSHIMA 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: x1226.c,v 1.25 2025/09/07 21:45:16 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/x1226reg.h> 54 55 #include "ioconf.h" 56 57 struct xrtc_softc { 58 device_t sc_dev; 59 i2c_tag_t sc_tag; 60 int sc_address; 61 int sc_open; 62 struct todr_chip_handle sc_todr; 63 }; 64 65 static void xrtc_attach(device_t, device_t, void *); 66 static int xrtc_match(device_t, cfdata_t, void *); 67 68 CFATTACH_DECL_NEW(xrtc, sizeof(struct xrtc_softc), 69 xrtc_match, xrtc_attach, NULL, NULL); 70 71 dev_type_open(xrtc_open); 72 dev_type_close(xrtc_close); 73 dev_type_read(xrtc_read); 74 dev_type_write(xrtc_write); 75 76 const struct cdevsw xrtc_cdevsw = { 77 .d_open = xrtc_open, 78 .d_close = xrtc_close, 79 .d_read = xrtc_read, 80 .d_write = xrtc_write, 81 .d_ioctl = noioctl, 82 .d_stop = nostop, 83 .d_tty = notty, 84 .d_poll = nopoll, 85 .d_mmap = nommap, 86 .d_kqfilter = nokqfilter, 87 .d_discard = nodiscard, 88 .d_flag = D_OTHER 89 }; 90 91 static int xrtc_clock_read(struct xrtc_softc *, struct clock_ymdhms *); 92 static int xrtc_gettime_ymdhms(struct todr_chip_handle *, 93 struct clock_ymdhms *); 94 static int xrtc_settime_ymdhms(struct todr_chip_handle *, 95 struct clock_ymdhms *); 96 97 /* 98 * xrtc_match() 99 */ 100 static int 101 xrtc_match(device_t parent, cfdata_t cf, void *arg) 102 { 103 struct i2c_attach_args *ia = arg; 104 105 /* match only this RTC devices */ 106 if (ia->ia_addr == X1226_ADDR) 107 return (I2C_MATCH_ADDRESS_ONLY); 108 109 return (0); 110 } 111 112 /* 113 * xrtc_attach() 114 */ 115 static void 116 xrtc_attach(device_t parent, device_t self, void *arg) 117 { 118 struct xrtc_softc *sc = device_private(self); 119 struct i2c_attach_args *ia = arg; 120 121 aprint_naive(": Real-time Clock/NVRAM\n"); 122 aprint_normal(": Xicor X1226 Real-time Clock/NVRAM\n"); 123 124 sc->sc_tag = ia->ia_tag; 125 sc->sc_address = ia->ia_addr; 126 sc->sc_dev = self; 127 sc->sc_open = 0; 128 sc->sc_todr.todr_dev = self; 129 sc->sc_todr.todr_gettime_ymdhms = xrtc_gettime_ymdhms; 130 sc->sc_todr.todr_settime_ymdhms = xrtc_settime_ymdhms; 131 132 todr_attach(&sc->sc_todr); 133 } 134 135 136 /*ARGSUSED*/ 137 int 138 xrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 139 { 140 struct xrtc_softc *sc; 141 142 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 143 return (ENXIO); 144 145 /* XXX: Locking */ 146 147 if (sc->sc_open) 148 return (EBUSY); 149 150 sc->sc_open = 1; 151 return (0); 152 } 153 154 /*ARGSUSED*/ 155 int 156 xrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 157 { 158 struct xrtc_softc *sc; 159 160 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 161 return (ENXIO); 162 163 sc->sc_open = 0; 164 return (0); 165 } 166 167 /*ARGSUSED*/ 168 int 169 xrtc_read(dev_t dev, struct uio *uio, int flags) 170 { 171 struct xrtc_softc *sc; 172 u_int8_t ch, cmdbuf[2]; 173 int addr, error; 174 175 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 176 return (ENXIO); 177 178 if (uio->uio_offset >= X1226_NVRAM_SIZE) 179 return (EINVAL); 180 181 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 182 return (error); 183 184 while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) { 185 addr = (int)uio->uio_offset + X1226_NVRAM_START; 186 cmdbuf[0] = (addr >> 8) & 0xff; 187 cmdbuf[1] = addr & 0xff; 188 if ((error = iic_exec(sc->sc_tag, 189 I2C_OP_READ_WITH_STOP, 190 sc->sc_address, cmdbuf, 2, &ch, 1, 0)) != 0) { 191 iic_release_bus(sc->sc_tag, 0); 192 aprint_error_dev(sc->sc_dev, 193 "xrtc_read: read failed at 0x%x\n", 194 (int)uio->uio_offset); 195 return (error); 196 } 197 if ((error = uiomove(&ch, 1, uio)) != 0) { 198 iic_release_bus(sc->sc_tag, 0); 199 return (error); 200 } 201 } 202 203 iic_release_bus(sc->sc_tag, 0); 204 205 return (0); 206 } 207 208 /*ARGSUSED*/ 209 int 210 xrtc_write(dev_t dev, struct uio *uio, int flags) 211 { 212 struct xrtc_softc *sc; 213 u_int8_t cmdbuf[3]; 214 int addr, error; 215 216 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 217 return (ENXIO); 218 219 if (uio->uio_offset >= X1226_NVRAM_SIZE) 220 return (EINVAL); 221 222 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 223 return (error); 224 225 while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) { 226 addr = (int)uio->uio_offset + X1226_NVRAM_START; 227 cmdbuf[0] = (addr >> 8) & 0xff; 228 cmdbuf[1] = addr & 0xff; 229 if ((error = uiomove(&cmdbuf[2], 1, uio)) != 0) { 230 break; 231 } 232 if ((error = iic_exec(sc->sc_tag, 233 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 234 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 235 iic_release_bus(sc->sc_tag, 0); 236 aprint_error_dev(sc->sc_dev, 237 "xrtc_write: write failed at 0x%x\n", 238 (int)uio->uio_offset); 239 return (error); 240 } 241 } 242 243 iic_release_bus(sc->sc_tag, 0); 244 245 return (0); 246 } 247 248 249 static int 250 xrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 251 { 252 struct xrtc_softc *sc = device_private(ch->todr_dev); 253 struct clock_ymdhms check; 254 int retries; 255 int error; 256 257 memset(dt, 0, sizeof(*dt)); 258 memset(&check, 0, sizeof(check)); 259 260 retries = 5; 261 do { 262 if ((error = xrtc_clock_read(sc, dt)) == 0) 263 error = xrtc_clock_read(sc, &check); 264 if (error) 265 return error; 266 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 267 268 return (0); 269 } 270 271 static int 272 xrtc_clock_read(struct xrtc_softc *sc, struct clock_ymdhms *dt) 273 { 274 int i = 0; 275 u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[2]; 276 int error; 277 278 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 279 aprint_error_dev(sc->sc_dev, 280 "xrtc_clock_read: failed to acquire I2C bus\n"); 281 return (error); 282 } 283 284 /* Read each RTC register in order */ 285 for (i = 0 ; i < X1226_REG_RTC_SIZE ; i++) { 286 int addr = i + X1226_REG_RTC_BASE; 287 cmdbuf[0] = (addr >> 8) & 0xff; 288 cmdbuf[1] = addr & 0xff; 289 290 if ((error = iic_exec(sc->sc_tag, 291 I2C_OP_READ_WITH_STOP, 292 sc->sc_address, cmdbuf, 2, 293 &bcd[i], 1, 0)) != 0) { 294 iic_release_bus(sc->sc_tag, 0); 295 aprint_error_dev(sc->sc_dev, 296 "xrtc_clock_read: failed to read rtc " 297 "at 0x%x\n", i); 298 return (error); 299 } 300 } 301 302 /* Done with I2C */ 303 iic_release_bus(sc->sc_tag, 0); 304 305 /* 306 * Convert the X1226's register bcd values 307 */ 308 dt->dt_sec = bcdtobin(bcd[X1226_REG_SC - X1226_REG_RTC_BASE] 309 & X1226_REG_SC_MASK); 310 dt->dt_min = bcdtobin(bcd[X1226_REG_MN - X1226_REG_RTC_BASE] 311 & X1226_REG_MN_MASK); 312 if (!(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_24H)) { 313 dt->dt_hour = bcdtobin(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] 314 & X1226_REG_HR12_MASK); 315 if (bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_12HPM) { 316 dt->dt_hour += 12; 317 } 318 } else { 319 dt->dt_hour = bcdtobin(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] 320 & X1226_REG_HR24_MASK); 321 } 322 dt->dt_wday = bcdtobin(bcd[X1226_REG_DW - X1226_REG_RTC_BASE] 323 & X1226_REG_DT_MASK); 324 dt->dt_day = bcdtobin(bcd[X1226_REG_DT - X1226_REG_RTC_BASE] 325 & X1226_REG_DT_MASK); 326 dt->dt_mon = bcdtobin(bcd[X1226_REG_MO - X1226_REG_RTC_BASE] 327 & X1226_REG_MO_MASK); 328 dt->dt_year = bcdtobin(bcd[X1226_REG_YR - X1226_REG_RTC_BASE] 329 & X1226_REG_YR_MASK); 330 dt->dt_year += bcdtobin(bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] 331 & X1226_REG_Y2K_MASK) * 100; 332 333 return (0); 334 } 335 336 static int 337 xrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 338 { 339 struct xrtc_softc *sc = device_private(ch->todr_dev); 340 int i = 0, addr; 341 u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[3]; 342 int error, error2; 343 344 /* 345 * Convert our time to bcd values 346 */ 347 bcd[X1226_REG_SC - X1226_REG_RTC_BASE] = bintobcd(dt->dt_sec); 348 bcd[X1226_REG_MN - X1226_REG_RTC_BASE] = bintobcd(dt->dt_min); 349 bcd[X1226_REG_HR - X1226_REG_RTC_BASE] = bintobcd(dt->dt_hour) 350 | X1226_FLAG_HR_24H; 351 bcd[X1226_REG_DW - X1226_REG_RTC_BASE] = bintobcd(dt->dt_wday); 352 bcd[X1226_REG_DT - X1226_REG_RTC_BASE] = bintobcd(dt->dt_day); 353 bcd[X1226_REG_MO - X1226_REG_RTC_BASE] = bintobcd(dt->dt_mon); 354 bcd[X1226_REG_YR - X1226_REG_RTC_BASE] = bintobcd(dt->dt_year % 100); 355 bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] = bintobcd(dt->dt_year / 100); 356 357 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 358 aprint_error_dev(sc->sc_dev, 359 "xrtc_clock_write: failed to acquire I2C bus\n"); 360 return (error); 361 } 362 363 /* Unlock register: Write Enable Latch */ 364 addr = X1226_REG_SR; 365 cmdbuf[0] = ((addr >> 8) & 0xff); 366 cmdbuf[1] = (addr & 0xff); 367 cmdbuf[2] = X1226_FLAG_SR_WEL; 368 if ((error = iic_exec(sc->sc_tag, 369 I2C_OP_WRITE_WITH_STOP, 370 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 371 iic_release_bus(sc->sc_tag, 0); 372 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 373 "failed to write-unlock status register(WEL=1)\n"); 374 return (error); 375 } 376 377 /* Unlock register: Register Write Enable Latch */ 378 addr = X1226_REG_SR; 379 cmdbuf[0] = ((addr >> 8) & 0xff); 380 cmdbuf[1] = (addr & 0xff); 381 cmdbuf[2] = X1226_FLAG_SR_WEL | X1226_FLAG_SR_RWEL; 382 if ((error = iic_exec(sc->sc_tag, 383 I2C_OP_WRITE_WITH_STOP, 384 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 385 iic_release_bus(sc->sc_tag, 0); 386 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 387 "failed to write-unlock status register(RWEL=1)\n"); 388 return (error); 389 } 390 391 /* Write each RTC register in reverse order */ 392 for (i = (X1226_REG_RTC_SIZE - 1) ; i >= 0; i--) { 393 addr = i + X1226_REG_RTC_BASE; 394 cmdbuf[0] = ((addr >> 8) & 0xff); 395 cmdbuf[1] = (addr & 0xff); 396 if ((error = iic_exec(sc->sc_tag, 397 I2C_OP_WRITE_WITH_STOP, 398 sc->sc_address, cmdbuf, 2, 399 &bcd[i], 1, 0)) != 0) { 400 401 aprint_error_dev(sc->sc_dev, 402 "xrtc_clock_write: failed to write rtc at 0x%x\n", 403 i); 404 405 goto write_lock_rtc; 406 } 407 } 408 409 write_lock_rtc: 410 /* Lock register: WEL/RWEL off */ 411 addr = X1226_REG_SR; 412 cmdbuf[0] = ((addr >> 8) & 0xff); 413 cmdbuf[1] = (addr & 0xff); 414 cmdbuf[2] = 0; 415 if ((error2 = iic_exec(sc->sc_tag, 416 I2C_OP_WRITE_WITH_STOP, 417 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 418 iic_release_bus(sc->sc_tag, 0); 419 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 420 "failed to write-lock status register\n"); 421 return (error ? error : error2); 422 } 423 424 iic_release_bus(sc->sc_tag, 0); 425 return (error); 426 } 427
Indexes created Mon Sep 22 10:09:38 GMT 2025