x1226.c revision 1.5 1 1.5 scw /* $NetBSD: x1226.c,v 1.5 2005/06/03 12:18:46 scw Exp $ */
2 1.1 shige
3 1.1 shige /*
4 1.1 shige * Copyright (c) 2003 Shigeyuki Fukushima.
5 1.1 shige * All rights reserved.
6 1.1 shige *
7 1.1 shige * Written by Shigeyuki Fukushima for the NetBSD Project.
8 1.1 shige *
9 1.1 shige * Redistribution and use in source and binary forms, with or without
10 1.1 shige * modification, are permitted provided that the following conditions
11 1.1 shige * are met:
12 1.1 shige * 1. Redistributions of source code must retain the above copyright
13 1.1 shige * notice, this list of conditions and the following disclaimer.
14 1.1 shige * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 shige * notice, this list of conditions and the following disclaimer in the
16 1.1 shige * documentation and/or other materials provided with the distribution.
17 1.1 shige * 3. All advertising materials mentioning features or use of this software
18 1.1 shige * must display the following acknowledgement:
19 1.1 shige * This product includes software developed for the NetBSD Project by
20 1.1 shige * Shigeyuki Fukushima.
21 1.1 shige * 4. The name of Shigeyuki Fukushima may not be used to endorse
22 1.1 shige * or promote products derived from this software without specific prior
23 1.1 shige * written permission.
24 1.1 shige *
25 1.1 shige * THIS SOFTWARE IS PROVIDED BY SHIGEYUKI FUKUSHIMA ``AS IS'' AND
26 1.1 shige * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 shige * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 shige * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SHIGEYUKI FUKUSHIMA
29 1.1 shige * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 shige * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 shige * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 shige * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 shige * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 shige * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 shige * POSSIBILITY OF SUCH DAMAGE.
36 1.1 shige */
37 1.1 shige
38 1.1 shige #include <sys/cdefs.h>
39 1.5 scw __KERNEL_RCSID(0, "$NetBSD: x1226.c,v 1.5 2005/06/03 12:18:46 scw Exp $");
40 1.1 shige
41 1.1 shige #include <sys/param.h>
42 1.1 shige #include <sys/systm.h>
43 1.1 shige #include <sys/device.h>
44 1.1 shige #include <sys/kernel.h>
45 1.1 shige #include <sys/fcntl.h>
46 1.1 shige #include <sys/uio.h>
47 1.1 shige #include <sys/conf.h>
48 1.1 shige #include <sys/event.h>
49 1.1 shige
50 1.1 shige #include <dev/clock_subr.h>
51 1.1 shige
52 1.1 shige #include <dev/i2c/i2cvar.h>
53 1.1 shige #include <dev/i2c/x1226reg.h>
54 1.1 shige
55 1.1 shige struct xrtc_softc {
56 1.1 shige struct device sc_dev;
57 1.1 shige i2c_tag_t sc_tag;
58 1.1 shige int sc_address;
59 1.1 shige int sc_open;
60 1.1 shige struct todr_chip_handle sc_todr;
61 1.1 shige };
62 1.1 shige
63 1.1 shige static void xrtc_attach(struct device *, struct device *, void *);
64 1.1 shige static int xrtc_match(struct device *, struct cfdata *, void *);
65 1.1 shige
66 1.1 shige CFATTACH_DECL(xrtc, sizeof(struct xrtc_softc),
67 1.1 shige xrtc_match, xrtc_attach, NULL, NULL);
68 1.1 shige extern struct cfdriver xrtc_cd;
69 1.1 shige
70 1.1 shige dev_type_open(xrtc_open);
71 1.1 shige dev_type_close(xrtc_close);
72 1.1 shige dev_type_read(xrtc_read);
73 1.1 shige dev_type_write(xrtc_write);
74 1.1 shige
75 1.1 shige const struct cdevsw xrtc_cdevsw = {
76 1.1 shige xrtc_open, xrtc_close, xrtc_read, xrtc_write,
77 1.1 shige noioctl, nostop, notty, nopoll, nommap, nokqfilter
78 1.1 shige };
79 1.1 shige
80 1.1 shige static int xrtc_clock_read(struct xrtc_softc *, struct clock_ymdhms *);
81 1.1 shige static int xrtc_clock_write(struct xrtc_softc *, struct clock_ymdhms *);
82 1.1 shige static int xrtc_gettime(struct todr_chip_handle *, struct timeval *);
83 1.1 shige static int xrtc_settime(struct todr_chip_handle *, struct timeval *);
84 1.1 shige static int xrtc_getcal(struct todr_chip_handle *, int *);
85 1.1 shige static int xrtc_setcal(struct todr_chip_handle *, int);
86 1.1 shige
87 1.1 shige
88 1.1 shige /*
89 1.1 shige * xrtc_match()
90 1.1 shige */
91 1.1 shige static int
92 1.1 shige xrtc_match(struct device *parent, struct cfdata *cf, void *arg)
93 1.1 shige {
94 1.1 shige struct i2c_attach_args *ia = arg;
95 1.1 shige
96 1.1 shige /* match only this RTC devices */
97 1.1 shige if (ia->ia_addr == X1226_ADDR)
98 1.1 shige return (1);
99 1.1 shige
100 1.1 shige return (0);
101 1.1 shige }
102 1.1 shige
103 1.1 shige /*
104 1.1 shige * xrtc_attach()
105 1.1 shige */
106 1.1 shige static void
107 1.1 shige xrtc_attach(struct device *parent, struct device *self, void *arg)
108 1.1 shige {
109 1.1 shige struct xrtc_softc *sc = (struct xrtc_softc *)self;
110 1.1 shige struct i2c_attach_args *ia = arg;
111 1.1 shige
112 1.1 shige aprint_naive(": Real-time Clock/NVRAM\n");
113 1.1 shige aprint_normal(": Xicor X1226 Real-time Clock/NVRAM\n");
114 1.1 shige
115 1.1 shige sc->sc_tag = ia->ia_tag;
116 1.1 shige sc->sc_address = ia->ia_addr;
117 1.1 shige sc->sc_open = 0;
118 1.1 shige sc->sc_todr.cookie = sc;
119 1.1 shige sc->sc_todr.todr_gettime = xrtc_gettime;
120 1.1 shige sc->sc_todr.todr_settime = xrtc_settime;
121 1.1 shige sc->sc_todr.todr_getcal = xrtc_getcal;
122 1.1 shige sc->sc_todr.todr_setcal = xrtc_setcal;
123 1.1 shige sc->sc_todr.todr_setwen = NULL;
124 1.1 shige
125 1.1 shige todr_attach(&sc->sc_todr);
126 1.1 shige }
127 1.1 shige
128 1.1 shige
129 1.1 shige /*ARGSUSED*/
130 1.1 shige int
131 1.1 shige xrtc_open(dev_t dev, int flag, int fmt, struct proc *p)
132 1.1 shige {
133 1.1 shige struct xrtc_softc *sc;
134 1.1 shige
135 1.1 shige if ((sc = device_lookup(&xrtc_cd, minor(dev))) == NULL)
136 1.1 shige return (ENXIO);
137 1.1 shige
138 1.1 shige /* XXX: Locking */
139 1.1 shige
140 1.1 shige if (sc->sc_open)
141 1.1 shige return (EBUSY);
142 1.1 shige
143 1.1 shige sc->sc_open = 1;
144 1.1 shige return (0);
145 1.1 shige }
146 1.1 shige
147 1.1 shige /*ARGSUSED*/
148 1.1 shige int
149 1.1 shige xrtc_close(dev_t dev, int flag, int fmt, struct proc *p)
150 1.1 shige {
151 1.1 shige struct xrtc_softc *sc;
152 1.1 shige
153 1.1 shige if ((sc = device_lookup(&xrtc_cd, minor(dev))) == NULL)
154 1.1 shige return (ENXIO);
155 1.1 shige
156 1.1 shige sc->sc_open = 0;
157 1.1 shige return (0);
158 1.1 shige }
159 1.1 shige
160 1.1 shige /*ARGSUSED*/
161 1.1 shige int
162 1.1 shige xrtc_read(dev_t dev, struct uio *uio, int flags)
163 1.1 shige {
164 1.1 shige struct xrtc_softc *sc;
165 1.1 shige u_int8_t ch, cmdbuf[2];
166 1.1 shige int addr, error;
167 1.1 shige
168 1.1 shige if ((sc = device_lookup(&xrtc_cd, minor(dev))) == NULL)
169 1.1 shige return (ENXIO);
170 1.1 shige
171 1.1 shige if (uio->uio_offset >= X1226_NVRAM_SIZE)
172 1.1 shige return (EINVAL);
173 1.1 shige
174 1.1 shige if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
175 1.1 shige return (error);
176 1.1 shige
177 1.1 shige while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) {
178 1.1 shige addr = (int)uio->uio_offset + X1226_NVRAM_START;
179 1.2 shige cmdbuf[0] = (addr >> 8) && 0xff;
180 1.2 shige cmdbuf[1] = addr && 0xff;
181 1.1 shige if ((error = iic_exec(sc->sc_tag,
182 1.1 shige I2C_OP_READ_WITH_STOP,
183 1.1 shige sc->sc_address, cmdbuf, 2, &ch, 1, 0)) != 0) {
184 1.1 shige iic_release_bus(sc->sc_tag, 0);
185 1.1 shige printf("%s: xrtc_read: read failed at 0x%x\n",
186 1.1 shige sc->sc_dev.dv_xname, (int)uio->uio_offset);
187 1.1 shige return (error);
188 1.1 shige }
189 1.1 shige if ((error = uiomove(&ch, 1, uio)) != 0) {
190 1.1 shige iic_release_bus(sc->sc_tag, 0);
191 1.1 shige return (error);
192 1.1 shige }
193 1.1 shige }
194 1.1 shige
195 1.1 shige iic_release_bus(sc->sc_tag, 0);
196 1.1 shige
197 1.1 shige return (0);
198 1.1 shige }
199 1.1 shige
200 1.1 shige /*ARGSUSED*/
201 1.1 shige int
202 1.1 shige xrtc_write(dev_t dev, struct uio *uio, int flags)
203 1.1 shige {
204 1.1 shige struct xrtc_softc *sc;
205 1.1 shige u_int8_t cmdbuf[3];
206 1.1 shige int addr, error;
207 1.1 shige
208 1.1 shige if ((sc = device_lookup(&xrtc_cd, minor(dev))) == NULL)
209 1.1 shige return (ENXIO);
210 1.1 shige
211 1.1 shige if (uio->uio_offset >= X1226_NVRAM_SIZE)
212 1.1 shige return (EINVAL);
213 1.1 shige
214 1.1 shige if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
215 1.1 shige return (error);
216 1.1 shige
217 1.1 shige while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) {
218 1.1 shige addr = (int)uio->uio_offset + X1226_NVRAM_START;
219 1.2 shige cmdbuf[0] = (addr >> 8) && 0xff;
220 1.2 shige cmdbuf[1] = addr && 0xff;
221 1.1 shige if ((error = uiomove(&cmdbuf[2], 1, uio)) != 0) {
222 1.1 shige break;
223 1.1 shige }
224 1.1 shige if ((error = iic_exec(sc->sc_tag,
225 1.1 shige uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP,
226 1.1 shige sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) {
227 1.1 shige iic_release_bus(sc->sc_tag, 0);
228 1.1 shige printf("%s: xrtc_write: write failed at 0x%x\n",
229 1.1 shige sc->sc_dev.dv_xname, (int)uio->uio_offset);
230 1.1 shige return (error);
231 1.1 shige }
232 1.1 shige }
233 1.1 shige
234 1.1 shige iic_release_bus(sc->sc_tag, 0);
235 1.1 shige
236 1.1 shige return (0);
237 1.1 shige }
238 1.1 shige
239 1.1 shige
240 1.1 shige static int
241 1.1 shige xrtc_gettime(struct todr_chip_handle *ch, struct timeval *tv)
242 1.1 shige {
243 1.1 shige struct xrtc_softc *sc = ch->cookie;
244 1.1 shige struct clock_ymdhms dt, check;
245 1.1 shige int retries;
246 1.1 shige
247 1.1 shige memset(&dt, 0, sizeof(dt));
248 1.1 shige memset(&check, 0, sizeof(check));
249 1.1 shige
250 1.1 shige retries = 5;
251 1.1 shige do {
252 1.1 shige xrtc_clock_read(sc, &dt);
253 1.1 shige xrtc_clock_read(sc, &check);
254 1.1 shige } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries);
255 1.1 shige
256 1.1 shige tv->tv_sec = clock_ymdhms_to_secs(&dt);
257 1.1 shige tv->tv_usec = 0;
258 1.1 shige
259 1.1 shige return (0);
260 1.1 shige }
261 1.1 shige
262 1.1 shige static int
263 1.1 shige xrtc_settime(struct todr_chip_handle *ch, struct timeval *tv)
264 1.1 shige {
265 1.1 shige struct xrtc_softc *sc = ch->cookie;
266 1.1 shige struct clock_ymdhms dt;
267 1.1 shige
268 1.1 shige clock_secs_to_ymdhms(tv->tv_sec, &dt);
269 1.1 shige
270 1.1 shige if (xrtc_clock_write(sc, &dt) == 0)
271 1.1 shige return (-1);
272 1.1 shige
273 1.1 shige return (0);
274 1.1 shige }
275 1.1 shige
276 1.1 shige static int
277 1.1 shige xrtc_setcal(struct todr_chip_handle *ch, int cal)
278 1.1 shige {
279 1.1 shige return (EOPNOTSUPP);
280 1.1 shige }
281 1.1 shige
282 1.1 shige static int
283 1.1 shige xrtc_getcal(struct todr_chip_handle *ch, int *cal)
284 1.1 shige {
285 1.1 shige return (EOPNOTSUPP);
286 1.1 shige }
287 1.1 shige
288 1.1 shige static int
289 1.1 shige xrtc_clock_read(struct xrtc_softc *sc, struct clock_ymdhms *dt)
290 1.1 shige {
291 1.1 shige int i = 0;
292 1.1 shige u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[2];
293 1.1 shige
294 1.1 shige if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) {
295 1.1 shige printf("%s: xrtc_clock_read: failed to acquire I2C bus\n",
296 1.1 shige sc->sc_dev.dv_xname);
297 1.1 shige return (0);
298 1.1 shige }
299 1.1 shige
300 1.1 shige /* Read each RTC register in order */
301 1.1 shige for (i = 0 ; i < X1226_REG_RTC_SIZE ; i++) {
302 1.1 shige int addr = i + X1226_REG_RTC_BASE;
303 1.2 shige cmdbuf[0] = (addr >> 8) & 0xff;
304 1.2 shige cmdbuf[1] = addr & 0xff;
305 1.1 shige
306 1.1 shige if (iic_exec(sc->sc_tag,
307 1.1 shige I2C_OP_READ_WITH_STOP,
308 1.1 shige sc->sc_address, cmdbuf, 2,
309 1.1 shige &bcd[i], 1, I2C_F_POLL)) {
310 1.1 shige iic_release_bus(sc->sc_tag, I2C_F_POLL);
311 1.1 shige printf("%s: xrtc_clock_read: failed to read rtc "
312 1.1 shige "at 0x%x\n", sc->sc_dev.dv_xname, i);
313 1.1 shige return (0);
314 1.1 shige }
315 1.1 shige }
316 1.1 shige
317 1.1 shige /* Done with I2C */
318 1.1 shige iic_release_bus(sc->sc_tag, I2C_F_POLL);
319 1.1 shige
320 1.1 shige /*
321 1.1 shige * Convert the X1226's register bcd values
322 1.1 shige */
323 1.1 shige dt->dt_sec = FROMBCD(bcd[X1226_REG_SC - X1226_REG_RTC_BASE]
324 1.1 shige & X1226_REG_SC_MASK);
325 1.1 shige dt->dt_min = FROMBCD(bcd[X1226_REG_MN - X1226_REG_RTC_BASE]
326 1.1 shige & X1226_REG_MN_MASK);
327 1.3 shige if (!(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_24H)) {
328 1.1 shige dt->dt_hour = FROMBCD(bcd[X1226_REG_HR - X1226_REG_RTC_BASE]
329 1.1 shige & X1226_REG_HR12_MASK);
330 1.1 shige if (bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_12HPM) {
331 1.1 shige dt->dt_hour += 12;
332 1.1 shige }
333 1.1 shige } else {
334 1.1 shige dt->dt_hour = FROMBCD(bcd[X1226_REG_HR - X1226_REG_RTC_BASE]
335 1.1 shige & X1226_REG_HR24_MASK);
336 1.1 shige }
337 1.2 shige dt->dt_wday = FROMBCD(bcd[X1226_REG_DW - X1226_REG_RTC_BASE]
338 1.2 shige & X1226_REG_DT_MASK);
339 1.1 shige dt->dt_day = FROMBCD(bcd[X1226_REG_DT - X1226_REG_RTC_BASE]
340 1.1 shige & X1226_REG_DT_MASK);
341 1.1 shige dt->dt_mon = FROMBCD(bcd[X1226_REG_MO - X1226_REG_RTC_BASE]
342 1.1 shige & X1226_REG_MO_MASK);
343 1.1 shige dt->dt_year = FROMBCD(bcd[X1226_REG_YR - X1226_REG_RTC_BASE]
344 1.1 shige & X1226_REG_YR_MASK);
345 1.1 shige dt->dt_year += FROMBCD(bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE]
346 1.1 shige & X1226_REG_Y2K_MASK) * 100;
347 1.1 shige
348 1.1 shige return (1);
349 1.1 shige }
350 1.1 shige
351 1.1 shige static int
352 1.1 shige xrtc_clock_write(struct xrtc_softc *sc, struct clock_ymdhms *dt)
353 1.1 shige {
354 1.1 shige int i = 0, addr;
355 1.1 shige u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[3];
356 1.1 shige
357 1.1 shige /*
358 1.1 shige * Convert our time to bcd values
359 1.1 shige */
360 1.1 shige bcd[X1226_REG_SC - X1226_REG_RTC_BASE] = TOBCD(dt->dt_sec);
361 1.1 shige bcd[X1226_REG_MN - X1226_REG_RTC_BASE] = TOBCD(dt->dt_min);
362 1.1 shige bcd[X1226_REG_HR - X1226_REG_RTC_BASE] = TOBCD(dt->dt_hour)
363 1.1 shige | X1226_FLAG_HR_24H;
364 1.1 shige bcd[X1226_REG_DW - X1226_REG_RTC_BASE] = TOBCD(dt->dt_wday);
365 1.1 shige bcd[X1226_REG_DT - X1226_REG_RTC_BASE] = TOBCD(dt->dt_day);
366 1.1 shige bcd[X1226_REG_MO - X1226_REG_RTC_BASE] = TOBCD(dt->dt_mon);
367 1.1 shige bcd[X1226_REG_YR - X1226_REG_RTC_BASE] = TOBCD(dt->dt_year % 100);
368 1.1 shige bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] = TOBCD(dt->dt_year / 100);
369 1.1 shige
370 1.1 shige if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) {
371 1.1 shige printf("%s: xrtc_clock_write: failed to acquire I2C bus\n",
372 1.1 shige sc->sc_dev.dv_xname);
373 1.1 shige return (0);
374 1.1 shige }
375 1.1 shige
376 1.1 shige /* Unlock register: Write Enable Latch */
377 1.1 shige addr = X1226_REG_SR;
378 1.2 shige cmdbuf[0] = ((addr >> 8) & 0xff);
379 1.2 shige cmdbuf[1] = (addr & 0xff);
380 1.1 shige cmdbuf[2] = X1226_FLAG_SR_WEL;
381 1.1 shige if (iic_exec(sc->sc_tag,
382 1.1 shige I2C_OP_WRITE_WITH_STOP,
383 1.1 shige sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) {
384 1.1 shige iic_release_bus(sc->sc_tag, I2C_F_POLL);
385 1.1 shige printf("%s: xrtc_clock_write: "
386 1.1 shige "failed to write-unlock status register(WEL=1)\n",
387 1.1 shige sc->sc_dev.dv_xname);
388 1.1 shige return (0);
389 1.1 shige }
390 1.1 shige
391 1.1 shige /* Unlock register: Register Write Enable Latch */
392 1.1 shige addr = X1226_REG_SR;
393 1.2 shige cmdbuf[0] = ((addr >> 8) & 0xff);
394 1.2 shige cmdbuf[1] = (addr & 0xff);
395 1.4 shige cmdbuf[2] = X1226_FLAG_SR_WEL | X1226_FLAG_SR_RWEL;
396 1.1 shige if (iic_exec(sc->sc_tag,
397 1.1 shige I2C_OP_WRITE_WITH_STOP,
398 1.1 shige sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) {
399 1.1 shige iic_release_bus(sc->sc_tag, I2C_F_POLL);
400 1.1 shige printf("%s: xrtc_clock_write: "
401 1.1 shige "failed to write-unlock status register(RWEL=1)\n",
402 1.1 shige sc->sc_dev.dv_xname);
403 1.1 shige return (0);
404 1.1 shige }
405 1.1 shige
406 1.1 shige /* Write each RTC register in reverse order */
407 1.1 shige for (i = (X1226_REG_RTC_SIZE - 1) ; i >= 0; i--) {
408 1.5 scw addr = i + X1226_REG_RTC_BASE;
409 1.2 shige cmdbuf[0] = ((addr >> 8) & 0xff);
410 1.2 shige cmdbuf[1] = (addr & 0xff);
411 1.1 shige if (iic_exec(sc->sc_tag,
412 1.1 shige I2C_OP_WRITE_WITH_STOP,
413 1.1 shige sc->sc_address, cmdbuf, 2,
414 1.1 shige &bcd[i], 1, I2C_F_POLL)) {
415 1.1 shige
416 1.1 shige /* Lock register: WEL/RWEL off */
417 1.1 shige addr = X1226_REG_SR;
418 1.2 shige cmdbuf[0] = ((addr >> 8) & 0xff);
419 1.2 shige cmdbuf[1] = (addr & 0xff);
420 1.1 shige cmdbuf[2] = 0;
421 1.1 shige iic_exec(sc->sc_tag,
422 1.1 shige I2C_OP_WRITE_WITH_STOP,
423 1.1 shige sc->sc_address, cmdbuf, 2,
424 1.1 shige &cmdbuf[2], 1, 0);
425 1.1 shige
426 1.1 shige iic_release_bus(sc->sc_tag, I2C_F_POLL);
427 1.1 shige printf("%s: xrtc_clock_write: failed to write rtc "
428 1.1 shige "at 0x%x\n", sc->sc_dev.dv_xname, i);
429 1.1 shige return (0);
430 1.1 shige }
431 1.1 shige }
432 1.1 shige
433 1.1 shige /* Lock register: WEL/RWEL off */
434 1.1 shige addr = X1226_REG_SR;
435 1.2 shige cmdbuf[0] = ((addr >> 8) & 0xff);
436 1.2 shige cmdbuf[1] = (addr & 0xff);
437 1.2 shige cmdbuf[2] = 0;
438 1.1 shige if (iic_exec(sc->sc_tag,
439 1.1 shige I2C_OP_WRITE_WITH_STOP,
440 1.1 shige sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) {
441 1.1 shige iic_release_bus(sc->sc_tag, I2C_F_POLL);
442 1.1 shige printf("%s: xrtc_clock_write: "
443 1.1 shige "failed to write-lock status register\n",
444 1.1 shige sc->sc_dev.dv_xname);
445 1.1 shige return (0);
446 1.1 shige }
447 1.1 shige
448 1.1 shige iic_release_bus(sc->sc_tag, I2C_F_POLL);
449 1.1 shige return (1);
450 1.1 shige }
451