x1226.c revision 1.11
1 /* $NetBSD: x1226.c,v 1.11 2008/04/06 20:25:59 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima for the NetBSD Project. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Shigeyuki Fukushima. 21 * 4. The name of Shigeyuki Fukushima may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY SHIGEYUKI FUKUSHIMA ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SHIGEYUKI FUKUSHIMA 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: x1226.c,v 1.11 2008/04/06 20:25:59 cegger Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/x1226reg.h> 54 55 struct xrtc_softc { 56 struct device sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static void xrtc_attach(struct device *, struct device *, void *); 64 static int xrtc_match(struct device *, struct cfdata *, void *); 65 66 CFATTACH_DECL(xrtc, sizeof(struct xrtc_softc), 67 xrtc_match, xrtc_attach, NULL, NULL); 68 extern struct cfdriver xrtc_cd; 69 70 dev_type_open(xrtc_open); 71 dev_type_close(xrtc_close); 72 dev_type_read(xrtc_read); 73 dev_type_write(xrtc_write); 74 75 const struct cdevsw xrtc_cdevsw = { 76 xrtc_open, xrtc_close, xrtc_read, xrtc_write, 77 noioctl, nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 78 }; 79 80 static int xrtc_clock_read(struct xrtc_softc *, struct clock_ymdhms *); 81 static int xrtc_clock_write(struct xrtc_softc *, struct clock_ymdhms *); 82 static int xrtc_gettime(struct todr_chip_handle *, volatile struct timeval *); 83 static int xrtc_settime(struct todr_chip_handle *, volatile struct timeval *); 84 85 /* 86 * xrtc_match() 87 */ 88 static int 89 xrtc_match(struct device *parent, struct cfdata *cf, void *arg) 90 { 91 struct i2c_attach_args *ia = arg; 92 93 /* match only this RTC devices */ 94 if (ia->ia_addr == X1226_ADDR) 95 return (1); 96 97 return (0); 98 } 99 100 /* 101 * xrtc_attach() 102 */ 103 static void 104 xrtc_attach(struct device *parent, struct device *self, void *arg) 105 { 106 struct xrtc_softc *sc = device_private(self); 107 struct i2c_attach_args *ia = arg; 108 109 aprint_naive(": Real-time Clock/NVRAM\n"); 110 aprint_normal(": Xicor X1226 Real-time Clock/NVRAM\n"); 111 112 sc->sc_tag = ia->ia_tag; 113 sc->sc_address = ia->ia_addr; 114 sc->sc_open = 0; 115 sc->sc_todr.cookie = sc; 116 sc->sc_todr.todr_gettime = xrtc_gettime; 117 sc->sc_todr.todr_settime = xrtc_settime; 118 sc->sc_todr.todr_setwen = NULL; 119 120 todr_attach(&sc->sc_todr); 121 } 122 123 124 /*ARGSUSED*/ 125 int 126 xrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 127 { 128 struct xrtc_softc *sc; 129 130 if ((sc = device_lookup(&xrtc_cd, minor(dev))) == NULL) 131 return (ENXIO); 132 133 /* XXX: Locking */ 134 135 if (sc->sc_open) 136 return (EBUSY); 137 138 sc->sc_open = 1; 139 return (0); 140 } 141 142 /*ARGSUSED*/ 143 int 144 xrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 145 { 146 struct xrtc_softc *sc; 147 148 if ((sc = device_lookup(&xrtc_cd, minor(dev))) == NULL) 149 return (ENXIO); 150 151 sc->sc_open = 0; 152 return (0); 153 } 154 155 /*ARGSUSED*/ 156 int 157 xrtc_read(dev_t dev, struct uio *uio, int flags) 158 { 159 struct xrtc_softc *sc; 160 u_int8_t ch, cmdbuf[2]; 161 int addr, error; 162 163 if ((sc = device_lookup(&xrtc_cd, minor(dev))) == NULL) 164 return (ENXIO); 165 166 if (uio->uio_offset >= X1226_NVRAM_SIZE) 167 return (EINVAL); 168 169 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 170 return (error); 171 172 while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) { 173 addr = (int)uio->uio_offset + X1226_NVRAM_START; 174 cmdbuf[0] = (addr >> 8) && 0xff; 175 cmdbuf[1] = addr && 0xff; 176 if ((error = iic_exec(sc->sc_tag, 177 I2C_OP_READ_WITH_STOP, 178 sc->sc_address, cmdbuf, 2, &ch, 1, 0)) != 0) { 179 iic_release_bus(sc->sc_tag, 0); 180 aprint_error_dev(&sc->sc_dev, "xrtc_read: read failed at 0x%x\n", 181 (int)uio->uio_offset); 182 return (error); 183 } 184 if ((error = uiomove(&ch, 1, uio)) != 0) { 185 iic_release_bus(sc->sc_tag, 0); 186 return (error); 187 } 188 } 189 190 iic_release_bus(sc->sc_tag, 0); 191 192 return (0); 193 } 194 195 /*ARGSUSED*/ 196 int 197 xrtc_write(dev_t dev, struct uio *uio, int flags) 198 { 199 struct xrtc_softc *sc; 200 u_int8_t cmdbuf[3]; 201 int addr, error; 202 203 if ((sc = device_lookup(&xrtc_cd, minor(dev))) == NULL) 204 return (ENXIO); 205 206 if (uio->uio_offset >= X1226_NVRAM_SIZE) 207 return (EINVAL); 208 209 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 210 return (error); 211 212 while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) { 213 addr = (int)uio->uio_offset + X1226_NVRAM_START; 214 cmdbuf[0] = (addr >> 8) && 0xff; 215 cmdbuf[1] = addr && 0xff; 216 if ((error = uiomove(&cmdbuf[2], 1, uio)) != 0) { 217 break; 218 } 219 if ((error = iic_exec(sc->sc_tag, 220 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 221 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 222 iic_release_bus(sc->sc_tag, 0); 223 aprint_error_dev(&sc->sc_dev, "xrtc_write: write failed at 0x%x\n", 224 (int)uio->uio_offset); 225 return (error); 226 } 227 } 228 229 iic_release_bus(sc->sc_tag, 0); 230 231 return (0); 232 } 233 234 235 static int 236 xrtc_gettime(struct todr_chip_handle *ch, volatile struct timeval *tv) 237 { 238 struct xrtc_softc *sc = ch->cookie; 239 struct clock_ymdhms dt, check; 240 int retries; 241 242 memset(&dt, 0, sizeof(dt)); 243 memset(&check, 0, sizeof(check)); 244 245 retries = 5; 246 do { 247 xrtc_clock_read(sc, &dt); 248 xrtc_clock_read(sc, &check); 249 } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries); 250 251 tv->tv_sec = clock_ymdhms_to_secs(&dt); 252 tv->tv_usec = 0; 253 254 return (0); 255 } 256 257 static int 258 xrtc_settime(struct todr_chip_handle *ch, volatile struct timeval *tv) 259 { 260 struct xrtc_softc *sc = ch->cookie; 261 struct clock_ymdhms dt; 262 263 clock_secs_to_ymdhms(tv->tv_sec, &dt); 264 265 if (xrtc_clock_write(sc, &dt) == 0) 266 return (-1); 267 268 return (0); 269 } 270 271 static int 272 xrtc_clock_read(struct xrtc_softc *sc, struct clock_ymdhms *dt) 273 { 274 int i = 0; 275 u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[2]; 276 277 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 278 aprint_error_dev(&sc->sc_dev, "xrtc_clock_read: failed to acquire I2C bus\n"); 279 return (0); 280 } 281 282 /* Read each RTC register in order */ 283 for (i = 0 ; i < X1226_REG_RTC_SIZE ; i++) { 284 int addr = i + X1226_REG_RTC_BASE; 285 cmdbuf[0] = (addr >> 8) & 0xff; 286 cmdbuf[1] = addr & 0xff; 287 288 if (iic_exec(sc->sc_tag, 289 I2C_OP_READ_WITH_STOP, 290 sc->sc_address, cmdbuf, 2, 291 &bcd[i], 1, I2C_F_POLL)) { 292 iic_release_bus(sc->sc_tag, I2C_F_POLL); 293 aprint_error_dev(&sc->sc_dev, "xrtc_clock_read: failed to read rtc " 294 "at 0x%x\n", i); 295 return (0); 296 } 297 } 298 299 /* Done with I2C */ 300 iic_release_bus(sc->sc_tag, I2C_F_POLL); 301 302 /* 303 * Convert the X1226's register bcd values 304 */ 305 dt->dt_sec = FROMBCD(bcd[X1226_REG_SC - X1226_REG_RTC_BASE] 306 & X1226_REG_SC_MASK); 307 dt->dt_min = FROMBCD(bcd[X1226_REG_MN - X1226_REG_RTC_BASE] 308 & X1226_REG_MN_MASK); 309 if (!(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_24H)) { 310 dt->dt_hour = FROMBCD(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] 311 & X1226_REG_HR12_MASK); 312 if (bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_12HPM) { 313 dt->dt_hour += 12; 314 } 315 } else { 316 dt->dt_hour = FROMBCD(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] 317 & X1226_REG_HR24_MASK); 318 } 319 dt->dt_wday = FROMBCD(bcd[X1226_REG_DW - X1226_REG_RTC_BASE] 320 & X1226_REG_DT_MASK); 321 dt->dt_day = FROMBCD(bcd[X1226_REG_DT - X1226_REG_RTC_BASE] 322 & X1226_REG_DT_MASK); 323 dt->dt_mon = FROMBCD(bcd[X1226_REG_MO - X1226_REG_RTC_BASE] 324 & X1226_REG_MO_MASK); 325 dt->dt_year = FROMBCD(bcd[X1226_REG_YR - X1226_REG_RTC_BASE] 326 & X1226_REG_YR_MASK); 327 dt->dt_year += FROMBCD(bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] 328 & X1226_REG_Y2K_MASK) * 100; 329 330 return (1); 331 } 332 333 static int 334 xrtc_clock_write(struct xrtc_softc *sc, struct clock_ymdhms *dt) 335 { 336 int i = 0, addr; 337 u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[3]; 338 339 /* 340 * Convert our time to bcd values 341 */ 342 bcd[X1226_REG_SC - X1226_REG_RTC_BASE] = TOBCD(dt->dt_sec); 343 bcd[X1226_REG_MN - X1226_REG_RTC_BASE] = TOBCD(dt->dt_min); 344 bcd[X1226_REG_HR - X1226_REG_RTC_BASE] = TOBCD(dt->dt_hour) 345 | X1226_FLAG_HR_24H; 346 bcd[X1226_REG_DW - X1226_REG_RTC_BASE] = TOBCD(dt->dt_wday); 347 bcd[X1226_REG_DT - X1226_REG_RTC_BASE] = TOBCD(dt->dt_day); 348 bcd[X1226_REG_MO - X1226_REG_RTC_BASE] = TOBCD(dt->dt_mon); 349 bcd[X1226_REG_YR - X1226_REG_RTC_BASE] = TOBCD(dt->dt_year % 100); 350 bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] = TOBCD(dt->dt_year / 100); 351 352 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 353 aprint_error_dev(&sc->sc_dev, "xrtc_clock_write: failed to acquire I2C bus\n"); 354 return (0); 355 } 356 357 /* Unlock register: Write Enable Latch */ 358 addr = X1226_REG_SR; 359 cmdbuf[0] = ((addr >> 8) & 0xff); 360 cmdbuf[1] = (addr & 0xff); 361 cmdbuf[2] = X1226_FLAG_SR_WEL; 362 if (iic_exec(sc->sc_tag, 363 I2C_OP_WRITE_WITH_STOP, 364 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) { 365 iic_release_bus(sc->sc_tag, I2C_F_POLL); 366 aprint_error_dev(&sc->sc_dev, "xrtc_clock_write: " 367 "failed to write-unlock status register(WEL=1)\n"); 368 return (0); 369 } 370 371 /* Unlock register: Register Write Enable Latch */ 372 addr = X1226_REG_SR; 373 cmdbuf[0] = ((addr >> 8) & 0xff); 374 cmdbuf[1] = (addr & 0xff); 375 cmdbuf[2] = X1226_FLAG_SR_WEL | X1226_FLAG_SR_RWEL; 376 if (iic_exec(sc->sc_tag, 377 I2C_OP_WRITE_WITH_STOP, 378 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) { 379 iic_release_bus(sc->sc_tag, I2C_F_POLL); 380 aprint_error_dev(&sc->sc_dev, "xrtc_clock_write: " 381 "failed to write-unlock status register(RWEL=1)\n"); 382 return (0); 383 } 384 385 /* Write each RTC register in reverse order */ 386 for (i = (X1226_REG_RTC_SIZE - 1) ; i >= 0; i--) { 387 addr = i + X1226_REG_RTC_BASE; 388 cmdbuf[0] = ((addr >> 8) & 0xff); 389 cmdbuf[1] = (addr & 0xff); 390 if (iic_exec(sc->sc_tag, 391 I2C_OP_WRITE_WITH_STOP, 392 sc->sc_address, cmdbuf, 2, 393 &bcd[i], 1, I2C_F_POLL)) { 394 395 /* Lock register: WEL/RWEL off */ 396 addr = X1226_REG_SR; 397 cmdbuf[0] = ((addr >> 8) & 0xff); 398 cmdbuf[1] = (addr & 0xff); 399 cmdbuf[2] = 0; 400 iic_exec(sc->sc_tag, 401 I2C_OP_WRITE_WITH_STOP, 402 sc->sc_address, cmdbuf, 2, 403 &cmdbuf[2], 1, 0); 404 405 iic_release_bus(sc->sc_tag, I2C_F_POLL); 406 aprint_error_dev(&sc->sc_dev, "xrtc_clock_write: failed to write rtc " 407 "at 0x%x\n", i); 408 return (0); 409 } 410 } 411 412 /* Lock register: WEL/RWEL off */ 413 addr = X1226_REG_SR; 414 cmdbuf[0] = ((addr >> 8) & 0xff); 415 cmdbuf[1] = (addr & 0xff); 416 cmdbuf[2] = 0; 417 if (iic_exec(sc->sc_tag, 418 I2C_OP_WRITE_WITH_STOP, 419 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) { 420 iic_release_bus(sc->sc_tag, I2C_F_POLL); 421 aprint_error_dev(&sc->sc_dev, "xrtc_clock_write: " 422 "failed to write-lock status register\n"); 423 return (0); 424 } 425 426 iic_release_bus(sc->sc_tag, I2C_F_POLL); 427 return (1); 428 } 429
Indexes created Sat Sep 27 14:09:57 GMT 2025