x1226.c revision 1.19
1 /* $NetBSD: x1226.c,v 1.19 2014/11/20 16:34:26 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima for the NetBSD Project. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Shigeyuki Fukushima. 21 * 4. The name of Shigeyuki Fukushima may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY SHIGEYUKI FUKUSHIMA ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SHIGEYUKI FUKUSHIMA 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: x1226.c,v 1.19 2014/11/20 16:34:26 christos Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/x1226reg.h> 54 55 struct xrtc_softc { 56 device_t sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static void xrtc_attach(device_t, device_t, void *); 64 static int xrtc_match(device_t, cfdata_t, void *); 65 66 CFATTACH_DECL_NEW(xrtc, sizeof(struct xrtc_softc), 67 xrtc_match, xrtc_attach, NULL, NULL); 68 extern struct cfdriver xrtc_cd; 69 70 dev_type_open(xrtc_open); 71 dev_type_close(xrtc_close); 72 dev_type_read(xrtc_read); 73 dev_type_write(xrtc_write); 74 75 const struct cdevsw xrtc_cdevsw = { 76 .d_open = xrtc_open, 77 .d_close = xrtc_close, 78 .d_read = xrtc_read, 79 .d_write = xrtc_write, 80 .d_ioctl = noioctl, 81 .d_stop = nostop, 82 .d_tty = notty, 83 .d_poll = nopoll, 84 .d_mmap = nommap, 85 .d_kqfilter = nokqfilter, 86 .d_discard = nodiscard, 87 .d_flag = D_OTHER 88 }; 89 90 static int xrtc_clock_read(struct xrtc_softc *, struct clock_ymdhms *); 91 static int xrtc_clock_write(struct xrtc_softc *, struct clock_ymdhms *); 92 static int xrtc_gettime(struct todr_chip_handle *, struct timeval *); 93 static int xrtc_settime(struct todr_chip_handle *, struct timeval *); 94 95 /* 96 * xrtc_match() 97 */ 98 static int 99 xrtc_match(device_t parent, cfdata_t cf, void *arg) 100 { 101 struct i2c_attach_args *ia = arg; 102 103 /* match only this RTC devices */ 104 if (ia->ia_addr == X1226_ADDR) 105 return (1); 106 107 return (0); 108 } 109 110 /* 111 * xrtc_attach() 112 */ 113 static void 114 xrtc_attach(device_t parent, device_t self, void *arg) 115 { 116 struct xrtc_softc *sc = device_private(self); 117 struct i2c_attach_args *ia = arg; 118 119 aprint_naive(": Real-time Clock/NVRAM\n"); 120 aprint_normal(": Xicor X1226 Real-time Clock/NVRAM\n"); 121 122 sc->sc_tag = ia->ia_tag; 123 sc->sc_address = ia->ia_addr; 124 sc->sc_dev = self; 125 sc->sc_open = 0; 126 sc->sc_todr.cookie = sc; 127 sc->sc_todr.todr_gettime = xrtc_gettime; 128 sc->sc_todr.todr_settime = xrtc_settime; 129 sc->sc_todr.todr_setwen = NULL; 130 131 todr_attach(&sc->sc_todr); 132 } 133 134 135 /*ARGSUSED*/ 136 int 137 xrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 138 { 139 struct xrtc_softc *sc; 140 141 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 142 return (ENXIO); 143 144 /* XXX: Locking */ 145 146 if (sc->sc_open) 147 return (EBUSY); 148 149 sc->sc_open = 1; 150 return (0); 151 } 152 153 /*ARGSUSED*/ 154 int 155 xrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 156 { 157 struct xrtc_softc *sc; 158 159 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 160 return (ENXIO); 161 162 sc->sc_open = 0; 163 return (0); 164 } 165 166 /*ARGSUSED*/ 167 int 168 xrtc_read(dev_t dev, struct uio *uio, int flags) 169 { 170 struct xrtc_softc *sc; 171 u_int8_t ch, cmdbuf[2]; 172 int addr, error; 173 174 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 175 return (ENXIO); 176 177 if (uio->uio_offset >= X1226_NVRAM_SIZE) 178 return (EINVAL); 179 180 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 181 return (error); 182 183 while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) { 184 addr = (int)uio->uio_offset + X1226_NVRAM_START; 185 cmdbuf[0] = (addr >> 8) & 0xff; 186 cmdbuf[1] = addr & 0xff; 187 if ((error = iic_exec(sc->sc_tag, 188 I2C_OP_READ_WITH_STOP, 189 sc->sc_address, cmdbuf, 2, &ch, 1, 0)) != 0) { 190 iic_release_bus(sc->sc_tag, 0); 191 aprint_error_dev(sc->sc_dev, 192 "xrtc_read: read failed at 0x%x\n", 193 (int)uio->uio_offset); 194 return (error); 195 } 196 if ((error = uiomove(&ch, 1, uio)) != 0) { 197 iic_release_bus(sc->sc_tag, 0); 198 return (error); 199 } 200 } 201 202 iic_release_bus(sc->sc_tag, 0); 203 204 return (0); 205 } 206 207 /*ARGSUSED*/ 208 int 209 xrtc_write(dev_t dev, struct uio *uio, int flags) 210 { 211 struct xrtc_softc *sc; 212 u_int8_t cmdbuf[3]; 213 int addr, error; 214 215 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 216 return (ENXIO); 217 218 if (uio->uio_offset >= X1226_NVRAM_SIZE) 219 return (EINVAL); 220 221 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 222 return (error); 223 224 while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) { 225 addr = (int)uio->uio_offset + X1226_NVRAM_START; 226 cmdbuf[0] = (addr >> 8) & 0xff; 227 cmdbuf[1] = addr & 0xff; 228 if ((error = uiomove(&cmdbuf[2], 1, uio)) != 0) { 229 break; 230 } 231 if ((error = iic_exec(sc->sc_tag, 232 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 233 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 234 iic_release_bus(sc->sc_tag, 0); 235 aprint_error_dev(sc->sc_dev, 236 "xrtc_write: write failed at 0x%x\n", 237 (int)uio->uio_offset); 238 return (error); 239 } 240 } 241 242 iic_release_bus(sc->sc_tag, 0); 243 244 return (0); 245 } 246 247 248 static int 249 xrtc_gettime(struct todr_chip_handle *ch, struct timeval *tv) 250 { 251 struct xrtc_softc *sc = ch->cookie; 252 struct clock_ymdhms dt, check; 253 int retries; 254 255 memset(&dt, 0, sizeof(dt)); 256 memset(&check, 0, sizeof(check)); 257 258 retries = 5; 259 do { 260 xrtc_clock_read(sc, &dt); 261 xrtc_clock_read(sc, &check); 262 } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries); 263 264 tv->tv_sec = clock_ymdhms_to_secs(&dt); 265 tv->tv_usec = 0; 266 267 return (0); 268 } 269 270 static int 271 xrtc_settime(struct todr_chip_handle *ch, struct timeval *tv) 272 { 273 struct xrtc_softc *sc = ch->cookie; 274 struct clock_ymdhms dt; 275 276 clock_secs_to_ymdhms(tv->tv_sec, &dt); 277 278 if (xrtc_clock_write(sc, &dt) == 0) 279 return (-1); 280 281 return (0); 282 } 283 284 static int 285 xrtc_clock_read(struct xrtc_softc *sc, struct clock_ymdhms *dt) 286 { 287 int i = 0; 288 u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[2]; 289 290 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 291 aprint_error_dev(sc->sc_dev, 292 "xrtc_clock_read: failed to acquire I2C bus\n"); 293 return (0); 294 } 295 296 /* Read each RTC register in order */ 297 for (i = 0 ; i < X1226_REG_RTC_SIZE ; i++) { 298 int addr = i + X1226_REG_RTC_BASE; 299 cmdbuf[0] = (addr >> 8) & 0xff; 300 cmdbuf[1] = addr & 0xff; 301 302 if (iic_exec(sc->sc_tag, 303 I2C_OP_READ_WITH_STOP, 304 sc->sc_address, cmdbuf, 2, 305 &bcd[i], 1, I2C_F_POLL)) { 306 iic_release_bus(sc->sc_tag, I2C_F_POLL); 307 aprint_error_dev(sc->sc_dev, 308 "xrtc_clock_read: failed to read rtc " 309 "at 0x%x\n", i); 310 return (0); 311 } 312 } 313 314 /* Done with I2C */ 315 iic_release_bus(sc->sc_tag, I2C_F_POLL); 316 317 /* 318 * Convert the X1226's register bcd values 319 */ 320 dt->dt_sec = bcdtobin(bcd[X1226_REG_SC - X1226_REG_RTC_BASE] 321 & X1226_REG_SC_MASK); 322 dt->dt_min = bcdtobin(bcd[X1226_REG_MN - X1226_REG_RTC_BASE] 323 & X1226_REG_MN_MASK); 324 if (!(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_24H)) { 325 dt->dt_hour = bcdtobin(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] 326 & X1226_REG_HR12_MASK); 327 if (bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_12HPM) { 328 dt->dt_hour += 12; 329 } 330 } else { 331 dt->dt_hour = bcdtobin(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] 332 & X1226_REG_HR24_MASK); 333 } 334 dt->dt_wday = bcdtobin(bcd[X1226_REG_DW - X1226_REG_RTC_BASE] 335 & X1226_REG_DT_MASK); 336 dt->dt_day = bcdtobin(bcd[X1226_REG_DT - X1226_REG_RTC_BASE] 337 & X1226_REG_DT_MASK); 338 dt->dt_mon = bcdtobin(bcd[X1226_REG_MO - X1226_REG_RTC_BASE] 339 & X1226_REG_MO_MASK); 340 dt->dt_year = bcdtobin(bcd[X1226_REG_YR - X1226_REG_RTC_BASE] 341 & X1226_REG_YR_MASK); 342 dt->dt_year += bcdtobin(bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] 343 & X1226_REG_Y2K_MASK) * 100; 344 345 return (1); 346 } 347 348 static int 349 xrtc_clock_write(struct xrtc_softc *sc, struct clock_ymdhms *dt) 350 { 351 int i = 0, addr; 352 u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[3]; 353 354 /* 355 * Convert our time to bcd values 356 */ 357 bcd[X1226_REG_SC - X1226_REG_RTC_BASE] = bintobcd(dt->dt_sec); 358 bcd[X1226_REG_MN - X1226_REG_RTC_BASE] = bintobcd(dt->dt_min); 359 bcd[X1226_REG_HR - X1226_REG_RTC_BASE] = bintobcd(dt->dt_hour) 360 | X1226_FLAG_HR_24H; 361 bcd[X1226_REG_DW - X1226_REG_RTC_BASE] = bintobcd(dt->dt_wday); 362 bcd[X1226_REG_DT - X1226_REG_RTC_BASE] = bintobcd(dt->dt_day); 363 bcd[X1226_REG_MO - X1226_REG_RTC_BASE] = bintobcd(dt->dt_mon); 364 bcd[X1226_REG_YR - X1226_REG_RTC_BASE] = bintobcd(dt->dt_year % 100); 365 bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] = bintobcd(dt->dt_year / 100); 366 367 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 368 aprint_error_dev(sc->sc_dev, 369 "xrtc_clock_write: failed to acquire I2C bus\n"); 370 return (0); 371 } 372 373 /* Unlock register: Write Enable Latch */ 374 addr = X1226_REG_SR; 375 cmdbuf[0] = ((addr >> 8) & 0xff); 376 cmdbuf[1] = (addr & 0xff); 377 cmdbuf[2] = X1226_FLAG_SR_WEL; 378 if (iic_exec(sc->sc_tag, 379 I2C_OP_WRITE_WITH_STOP, 380 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) { 381 iic_release_bus(sc->sc_tag, I2C_F_POLL); 382 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 383 "failed to write-unlock status register(WEL=1)\n"); 384 return (0); 385 } 386 387 /* Unlock register: Register Write Enable Latch */ 388 addr = X1226_REG_SR; 389 cmdbuf[0] = ((addr >> 8) & 0xff); 390 cmdbuf[1] = (addr & 0xff); 391 cmdbuf[2] = X1226_FLAG_SR_WEL | X1226_FLAG_SR_RWEL; 392 if (iic_exec(sc->sc_tag, 393 I2C_OP_WRITE_WITH_STOP, 394 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) { 395 iic_release_bus(sc->sc_tag, I2C_F_POLL); 396 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 397 "failed to write-unlock status register(RWEL=1)\n"); 398 return (0); 399 } 400 401 /* Write each RTC register in reverse order */ 402 for (i = (X1226_REG_RTC_SIZE - 1) ; i >= 0; i--) { 403 addr = i + X1226_REG_RTC_BASE; 404 cmdbuf[0] = ((addr >> 8) & 0xff); 405 cmdbuf[1] = (addr & 0xff); 406 if (iic_exec(sc->sc_tag, 407 I2C_OP_WRITE_WITH_STOP, 408 sc->sc_address, cmdbuf, 2, 409 &bcd[i], 1, I2C_F_POLL)) { 410 411 /* Lock register: WEL/RWEL off */ 412 addr = X1226_REG_SR; 413 cmdbuf[0] = ((addr >> 8) & 0xff); 414 cmdbuf[1] = (addr & 0xff); 415 cmdbuf[2] = 0; 416 iic_exec(sc->sc_tag, 417 I2C_OP_WRITE_WITH_STOP, 418 sc->sc_address, cmdbuf, 2, 419 &cmdbuf[2], 1, 0); 420 421 iic_release_bus(sc->sc_tag, I2C_F_POLL); 422 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: failed to write rtc " 423 "at 0x%x\n", i); 424 return (0); 425 } 426 } 427 428 /* Lock register: WEL/RWEL off */ 429 addr = X1226_REG_SR; 430 cmdbuf[0] = ((addr >> 8) & 0xff); 431 cmdbuf[1] = (addr & 0xff); 432 cmdbuf[2] = 0; 433 if (iic_exec(sc->sc_tag, 434 I2C_OP_WRITE_WITH_STOP, 435 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) { 436 iic_release_bus(sc->sc_tag, I2C_F_POLL); 437 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 438 "failed to write-lock status register\n"); 439 return (0); 440 } 441 442 iic_release_bus(sc->sc_tag, I2C_F_POLL); 443 return (1); 444 } 445
Indexes created Wed Sep 24 14:09:57 GMT 2025