x1226.c revision 1.21
1 /* $NetBSD: x1226.c,v 1.21 2018/06/16 21:22:13 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima for the NetBSD Project. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Shigeyuki Fukushima. 21 * 4. The name of Shigeyuki Fukushima may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY SHIGEYUKI FUKUSHIMA ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SHIGEYUKI FUKUSHIMA 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: x1226.c,v 1.21 2018/06/16 21:22:13 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/x1226reg.h> 54 55 #include "ioconf.h" 56 57 struct xrtc_softc { 58 device_t sc_dev; 59 i2c_tag_t sc_tag; 60 int sc_address; 61 int sc_open; 62 struct todr_chip_handle sc_todr; 63 }; 64 65 static void xrtc_attach(device_t, device_t, void *); 66 static int xrtc_match(device_t, cfdata_t, void *); 67 68 CFATTACH_DECL_NEW(xrtc, sizeof(struct xrtc_softc), 69 xrtc_match, xrtc_attach, NULL, NULL); 70 71 dev_type_open(xrtc_open); 72 dev_type_close(xrtc_close); 73 dev_type_read(xrtc_read); 74 dev_type_write(xrtc_write); 75 76 const struct cdevsw xrtc_cdevsw = { 77 .d_open = xrtc_open, 78 .d_close = xrtc_close, 79 .d_read = xrtc_read, 80 .d_write = xrtc_write, 81 .d_ioctl = noioctl, 82 .d_stop = nostop, 83 .d_tty = notty, 84 .d_poll = nopoll, 85 .d_mmap = nommap, 86 .d_kqfilter = nokqfilter, 87 .d_discard = nodiscard, 88 .d_flag = D_OTHER 89 }; 90 91 static int xrtc_clock_read(struct xrtc_softc *, struct clock_ymdhms *); 92 static int xrtc_clock_write(struct xrtc_softc *, struct clock_ymdhms *); 93 static int xrtc_gettime(struct todr_chip_handle *, struct timeval *); 94 static int xrtc_settime(struct todr_chip_handle *, struct timeval *); 95 96 /* 97 * xrtc_match() 98 */ 99 static int 100 xrtc_match(device_t parent, cfdata_t cf, void *arg) 101 { 102 struct i2c_attach_args *ia = arg; 103 104 /* match only this RTC devices */ 105 if (ia->ia_addr == X1226_ADDR) 106 return (I2C_MATCH_ADDRESS_ONLY); 107 108 return (0); 109 } 110 111 /* 112 * xrtc_attach() 113 */ 114 static void 115 xrtc_attach(device_t parent, device_t self, void *arg) 116 { 117 struct xrtc_softc *sc = device_private(self); 118 struct i2c_attach_args *ia = arg; 119 120 aprint_naive(": Real-time Clock/NVRAM\n"); 121 aprint_normal(": Xicor X1226 Real-time Clock/NVRAM\n"); 122 123 sc->sc_tag = ia->ia_tag; 124 sc->sc_address = ia->ia_addr; 125 sc->sc_dev = self; 126 sc->sc_open = 0; 127 sc->sc_todr.cookie = sc; 128 sc->sc_todr.todr_gettime = xrtc_gettime; 129 sc->sc_todr.todr_settime = xrtc_settime; 130 sc->sc_todr.todr_setwen = NULL; 131 132 todr_attach(&sc->sc_todr); 133 } 134 135 136 /*ARGSUSED*/ 137 int 138 xrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 139 { 140 struct xrtc_softc *sc; 141 142 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 143 return (ENXIO); 144 145 /* XXX: Locking */ 146 147 if (sc->sc_open) 148 return (EBUSY); 149 150 sc->sc_open = 1; 151 return (0); 152 } 153 154 /*ARGSUSED*/ 155 int 156 xrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 157 { 158 struct xrtc_softc *sc; 159 160 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 161 return (ENXIO); 162 163 sc->sc_open = 0; 164 return (0); 165 } 166 167 /*ARGSUSED*/ 168 int 169 xrtc_read(dev_t dev, struct uio *uio, int flags) 170 { 171 struct xrtc_softc *sc; 172 u_int8_t ch, cmdbuf[2]; 173 int addr, error; 174 175 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 176 return (ENXIO); 177 178 if (uio->uio_offset >= X1226_NVRAM_SIZE) 179 return (EINVAL); 180 181 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 182 return (error); 183 184 while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) { 185 addr = (int)uio->uio_offset + X1226_NVRAM_START; 186 cmdbuf[0] = (addr >> 8) & 0xff; 187 cmdbuf[1] = addr & 0xff; 188 if ((error = iic_exec(sc->sc_tag, 189 I2C_OP_READ_WITH_STOP, 190 sc->sc_address, cmdbuf, 2, &ch, 1, 0)) != 0) { 191 iic_release_bus(sc->sc_tag, 0); 192 aprint_error_dev(sc->sc_dev, 193 "xrtc_read: read failed at 0x%x\n", 194 (int)uio->uio_offset); 195 return (error); 196 } 197 if ((error = uiomove(&ch, 1, uio)) != 0) { 198 iic_release_bus(sc->sc_tag, 0); 199 return (error); 200 } 201 } 202 203 iic_release_bus(sc->sc_tag, 0); 204 205 return (0); 206 } 207 208 /*ARGSUSED*/ 209 int 210 xrtc_write(dev_t dev, struct uio *uio, int flags) 211 { 212 struct xrtc_softc *sc; 213 u_int8_t cmdbuf[3]; 214 int addr, error; 215 216 if ((sc = device_lookup_private(&xrtc_cd, minor(dev))) == NULL) 217 return (ENXIO); 218 219 if (uio->uio_offset >= X1226_NVRAM_SIZE) 220 return (EINVAL); 221 222 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 223 return (error); 224 225 while (uio->uio_resid && uio->uio_offset < X1226_NVRAM_SIZE) { 226 addr = (int)uio->uio_offset + X1226_NVRAM_START; 227 cmdbuf[0] = (addr >> 8) & 0xff; 228 cmdbuf[1] = addr & 0xff; 229 if ((error = uiomove(&cmdbuf[2], 1, uio)) != 0) { 230 break; 231 } 232 if ((error = iic_exec(sc->sc_tag, 233 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 234 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0)) != 0) { 235 iic_release_bus(sc->sc_tag, 0); 236 aprint_error_dev(sc->sc_dev, 237 "xrtc_write: write failed at 0x%x\n", 238 (int)uio->uio_offset); 239 return (error); 240 } 241 } 242 243 iic_release_bus(sc->sc_tag, 0); 244 245 return (0); 246 } 247 248 249 static int 250 xrtc_gettime(struct todr_chip_handle *ch, struct timeval *tv) 251 { 252 struct xrtc_softc *sc = ch->cookie; 253 struct clock_ymdhms dt, check; 254 int retries; 255 256 memset(&dt, 0, sizeof(dt)); 257 memset(&check, 0, sizeof(check)); 258 259 retries = 5; 260 do { 261 xrtc_clock_read(sc, &dt); 262 xrtc_clock_read(sc, &check); 263 } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries); 264 265 tv->tv_sec = clock_ymdhms_to_secs(&dt); 266 tv->tv_usec = 0; 267 268 return (0); 269 } 270 271 static int 272 xrtc_settime(struct todr_chip_handle *ch, struct timeval *tv) 273 { 274 struct xrtc_softc *sc = ch->cookie; 275 struct clock_ymdhms dt; 276 277 clock_secs_to_ymdhms(tv->tv_sec, &dt); 278 279 if (xrtc_clock_write(sc, &dt) == 0) 280 return (-1); 281 282 return (0); 283 } 284 285 static int 286 xrtc_clock_read(struct xrtc_softc *sc, struct clock_ymdhms *dt) 287 { 288 int i = 0; 289 u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[2]; 290 291 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 292 aprint_error_dev(sc->sc_dev, 293 "xrtc_clock_read: failed to acquire I2C bus\n"); 294 return (0); 295 } 296 297 /* Read each RTC register in order */ 298 for (i = 0 ; i < X1226_REG_RTC_SIZE ; i++) { 299 int addr = i + X1226_REG_RTC_BASE; 300 cmdbuf[0] = (addr >> 8) & 0xff; 301 cmdbuf[1] = addr & 0xff; 302 303 if (iic_exec(sc->sc_tag, 304 I2C_OP_READ_WITH_STOP, 305 sc->sc_address, cmdbuf, 2, 306 &bcd[i], 1, I2C_F_POLL)) { 307 iic_release_bus(sc->sc_tag, I2C_F_POLL); 308 aprint_error_dev(sc->sc_dev, 309 "xrtc_clock_read: failed to read rtc " 310 "at 0x%x\n", i); 311 return (0); 312 } 313 } 314 315 /* Done with I2C */ 316 iic_release_bus(sc->sc_tag, I2C_F_POLL); 317 318 /* 319 * Convert the X1226's register bcd values 320 */ 321 dt->dt_sec = bcdtobin(bcd[X1226_REG_SC - X1226_REG_RTC_BASE] 322 & X1226_REG_SC_MASK); 323 dt->dt_min = bcdtobin(bcd[X1226_REG_MN - X1226_REG_RTC_BASE] 324 & X1226_REG_MN_MASK); 325 if (!(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_24H)) { 326 dt->dt_hour = bcdtobin(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] 327 & X1226_REG_HR12_MASK); 328 if (bcd[X1226_REG_HR - X1226_REG_RTC_BASE] & X1226_FLAG_HR_12HPM) { 329 dt->dt_hour += 12; 330 } 331 } else { 332 dt->dt_hour = bcdtobin(bcd[X1226_REG_HR - X1226_REG_RTC_BASE] 333 & X1226_REG_HR24_MASK); 334 } 335 dt->dt_wday = bcdtobin(bcd[X1226_REG_DW - X1226_REG_RTC_BASE] 336 & X1226_REG_DT_MASK); 337 dt->dt_day = bcdtobin(bcd[X1226_REG_DT - X1226_REG_RTC_BASE] 338 & X1226_REG_DT_MASK); 339 dt->dt_mon = bcdtobin(bcd[X1226_REG_MO - X1226_REG_RTC_BASE] 340 & X1226_REG_MO_MASK); 341 dt->dt_year = bcdtobin(bcd[X1226_REG_YR - X1226_REG_RTC_BASE] 342 & X1226_REG_YR_MASK); 343 dt->dt_year += bcdtobin(bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] 344 & X1226_REG_Y2K_MASK) * 100; 345 346 return (1); 347 } 348 349 static int 350 xrtc_clock_write(struct xrtc_softc *sc, struct clock_ymdhms *dt) 351 { 352 int i = 0, addr; 353 u_int8_t bcd[X1226_REG_RTC_SIZE], cmdbuf[3]; 354 355 /* 356 * Convert our time to bcd values 357 */ 358 bcd[X1226_REG_SC - X1226_REG_RTC_BASE] = bintobcd(dt->dt_sec); 359 bcd[X1226_REG_MN - X1226_REG_RTC_BASE] = bintobcd(dt->dt_min); 360 bcd[X1226_REG_HR - X1226_REG_RTC_BASE] = bintobcd(dt->dt_hour) 361 | X1226_FLAG_HR_24H; 362 bcd[X1226_REG_DW - X1226_REG_RTC_BASE] = bintobcd(dt->dt_wday); 363 bcd[X1226_REG_DT - X1226_REG_RTC_BASE] = bintobcd(dt->dt_day); 364 bcd[X1226_REG_MO - X1226_REG_RTC_BASE] = bintobcd(dt->dt_mon); 365 bcd[X1226_REG_YR - X1226_REG_RTC_BASE] = bintobcd(dt->dt_year % 100); 366 bcd[X1226_REG_Y2K - X1226_REG_RTC_BASE] = bintobcd(dt->dt_year / 100); 367 368 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 369 aprint_error_dev(sc->sc_dev, 370 "xrtc_clock_write: failed to acquire I2C bus\n"); 371 return (0); 372 } 373 374 /* Unlock register: Write Enable Latch */ 375 addr = X1226_REG_SR; 376 cmdbuf[0] = ((addr >> 8) & 0xff); 377 cmdbuf[1] = (addr & 0xff); 378 cmdbuf[2] = X1226_FLAG_SR_WEL; 379 if (iic_exec(sc->sc_tag, 380 I2C_OP_WRITE_WITH_STOP, 381 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) { 382 iic_release_bus(sc->sc_tag, I2C_F_POLL); 383 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 384 "failed to write-unlock status register(WEL=1)\n"); 385 return (0); 386 } 387 388 /* Unlock register: Register Write Enable Latch */ 389 addr = X1226_REG_SR; 390 cmdbuf[0] = ((addr >> 8) & 0xff); 391 cmdbuf[1] = (addr & 0xff); 392 cmdbuf[2] = X1226_FLAG_SR_WEL | X1226_FLAG_SR_RWEL; 393 if (iic_exec(sc->sc_tag, 394 I2C_OP_WRITE_WITH_STOP, 395 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) { 396 iic_release_bus(sc->sc_tag, I2C_F_POLL); 397 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 398 "failed to write-unlock status register(RWEL=1)\n"); 399 return (0); 400 } 401 402 /* Write each RTC register in reverse order */ 403 for (i = (X1226_REG_RTC_SIZE - 1) ; i >= 0; i--) { 404 addr = i + X1226_REG_RTC_BASE; 405 cmdbuf[0] = ((addr >> 8) & 0xff); 406 cmdbuf[1] = (addr & 0xff); 407 if (iic_exec(sc->sc_tag, 408 I2C_OP_WRITE_WITH_STOP, 409 sc->sc_address, cmdbuf, 2, 410 &bcd[i], 1, I2C_F_POLL)) { 411 412 /* Lock register: WEL/RWEL off */ 413 addr = X1226_REG_SR; 414 cmdbuf[0] = ((addr >> 8) & 0xff); 415 cmdbuf[1] = (addr & 0xff); 416 cmdbuf[2] = 0; 417 iic_exec(sc->sc_tag, 418 I2C_OP_WRITE_WITH_STOP, 419 sc->sc_address, cmdbuf, 2, 420 &cmdbuf[2], 1, 0); 421 422 iic_release_bus(sc->sc_tag, I2C_F_POLL); 423 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: failed to write rtc " 424 "at 0x%x\n", i); 425 return (0); 426 } 427 } 428 429 /* Lock register: WEL/RWEL off */ 430 addr = X1226_REG_SR; 431 cmdbuf[0] = ((addr >> 8) & 0xff); 432 cmdbuf[1] = (addr & 0xff); 433 cmdbuf[2] = 0; 434 if (iic_exec(sc->sc_tag, 435 I2C_OP_WRITE_WITH_STOP, 436 sc->sc_address, cmdbuf, 2, &cmdbuf[2], 1, 0) != 0) { 437 iic_release_bus(sc->sc_tag, I2C_F_POLL); 438 aprint_error_dev(sc->sc_dev, "xrtc_clock_write: " 439 "failed to write-lock status register\n"); 440 return (0); 441 } 442 443 iic_release_bus(sc->sc_tag, I2C_F_POLL); 444 return (1); 445 } 446
Indexes created Wed Sep 24 15:09:51 GMT 2025