ahareg.h revision 1.1
1 /* $NetBSD: ahareg.h,v 1.1 1997/02/07 17:37:29 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Originally written by Julian Elischer (julian (at) tfs.com) 34 * for TRW Financial Systems for use under the MACH(2.5) operating system. 35 * 36 * TRW Financial Systems, in accordance with their agreement with Carnegie 37 * Mellon University, makes this software available to CMU to distribute 38 * or use in any manner that they see fit as long as this message is kept with 39 * the software. For this reason TFS also grants any other persons or 40 * organisations permission to use or modify this software. 41 * 42 * TFS supplies this software to be publicly redistributed 43 * on the understanding that TFS is not responsible for the correct 44 * functioning of this software in any circumstances. 45 */ 46 47 typedef u_int8_t physaddr[3]; 48 typedef u_int8_t physlen[3]; 49 #define ltophys _lto3b 50 #define phystol _3btol 51 52 /* 53 * I/O port offsets 54 */ 55 #define AHA_CTRL_PORT 0 /* control (wo) */ 56 #define AHA_STAT_PORT 0 /* status (ro) */ 57 #define AHA_CMD_PORT 1 /* command (wo) */ 58 #define AHA_DATA_PORT 1 /* data (ro) */ 59 #define AHA_INTR_PORT 2 /* interrupt status (ro) */ 60 61 /* 62 * AHA_CTRL bits 63 */ 64 #define AHA_CTRL_HRST 0x80 /* Hardware reset */ 65 #define AHA_CTRL_SRST 0x40 /* Software reset */ 66 #define AHA_CTRL_IRST 0x20 /* Interrupt reset */ 67 #define AHA_CTRL_SCRST 0x10 /* SCSI bus reset */ 68 69 /* 70 * AHA_STAT bits 71 */ 72 #define AHA_STAT_STST 0x80 /* Self test in Progress */ 73 #define AHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ 74 #define AHA_STAT_INIT 0x20 /* Mbx Init required */ 75 #define AHA_STAT_IDLE 0x10 /* Host Adapter Idle */ 76 #define AHA_STAT_CDF 0x08 /* cmd/data out port full */ 77 #define AHA_STAT_DF 0x04 /* Data in port full */ 78 #define AHA_STAT_INVDCMD 0x01 /* Invalid command */ 79 80 /* 81 * AHA_CMD opcodes 82 */ 83 #define AHA_NOP 0x00 /* No operation */ 84 #define AHA_MBX_INIT 0x01 /* Mbx initialization */ 85 #define AHA_START_SCSI 0x02 /* start scsi command */ 86 #define AHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ 87 #define AHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ 88 #if 0 89 #define AHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ 90 #define AHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ 91 #define AHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ 92 #define AHA_SPEED_SET 0x09 /* set transfer speed */ 93 #endif 94 #define AHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ 95 #define AHA_INQUIRE_CONFIG 0x0b /* return configuration data */ 96 #define AHA_TARGET_EN 0x0c /* enable target mode */ 97 #define AHA_INQUIRE_SETUP 0x0d /* return setup data */ 98 #define AHA_ECHO 0x1e /* Echo command data */ 99 #define AHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ 100 #define AHA_EXT_BIOS 0x28 /* return extended bios info */ 101 #define AHA_MBX_ENABLE 0x29 /* enable mail box interface */ 102 103 /* 104 * AHA_INTR bits 105 */ 106 #define AHA_INTR_ANYINTR 0x80 /* Any interrupt */ 107 #define AHA_INTR_SCRD 0x08 /* SCSI reset detected */ 108 #define AHA_INTR_HACC 0x04 /* Command complete */ 109 #define AHA_INTR_MBOA 0x02 /* MBX out empty */ 110 #define AHA_INTR_MBIF 0x01 /* MBX in full */ 111 112 struct aha_mbx_out { 113 u_char cmd; 114 physaddr ccb_addr; 115 }; 116 117 struct aha_mbx_in { 118 u_char stat; 119 physaddr ccb_addr; 120 }; 121 122 /* 123 * mbo.cmd values 124 */ 125 #define AHA_MBO_FREE 0x0 /* MBO entry is free */ 126 #define AHA_MBO_START 0x1 /* MBO activate entry */ 127 #define AHA_MBO_ABORT 0x2 /* MBO abort entry */ 128 129 /* 130 * mbi.stat values 131 */ 132 #define AHA_MBI_FREE 0x0 /* MBI entry is free */ 133 #define AHA_MBI_OK 0x1 /* completed without error */ 134 #define AHA_MBI_ABORT 0x2 /* aborted ccb */ 135 #define AHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ 136 #define AHA_MBI_ERROR 0x4 /* Completed with error */ 137 138 /* FOR OLD VERSIONS OF THE !%$@ this may have to be 16 (yuk) */ 139 #define AHA_NSEG 17 /* Number of scatter gather segments <= 16 */ 140 /* allow 64 K i/o (min) */ 141 142 struct aha_scat_gath { 143 physlen seg_len; 144 physaddr seg_addr; 145 }; 146 147 struct aha_ccb { 148 u_char opcode; 149 u_char lun:3; 150 u_char data_in:1; /* must be 0 */ 151 u_char data_out:1; /* must be 0 */ 152 u_char target:3; 153 u_char scsi_cmd_length; 154 u_char req_sense_length; 155 physlen data_length; 156 physaddr data_addr; 157 physaddr link_addr; 158 u_char link_id; 159 u_char host_stat; 160 u_char target_stat; 161 u_char reserved[2]; 162 struct scsi_generic scsi_cmd; 163 struct scsi_sense_data scsi_sense; 164 struct aha_scat_gath scat_gath[AHA_NSEG]; 165 /*----------------------------------------------------------------*/ 166 TAILQ_ENTRY(aha_ccb) chain; 167 struct aha_ccb *nexthash; 168 long hashkey; 169 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 170 int flags; 171 #define CCB_ALLOC 0x01 172 #define CCB_ABORT 0x02 173 #ifdef AHADIAG 174 #define CCB_SENDING 0x04 175 #endif 176 int timeout; 177 }; 178 179 /* 180 * opcode fields 181 */ 182 #define AHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ 183 #define AHA_TARGET_CCB 0x01 /* SCSI Target CCB */ 184 #define AHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scatter gather */ 185 #define AHA_RESET_CCB 0x81 /* SCSI Bus reset */ 186 187 /* 188 * aha_ccb.host_stat values 189 */ 190 #define AHA_OK 0x00 /* cmd ok */ 191 #define AHA_LINK_OK 0x0a /* Link cmd ok */ 192 #define AHA_LINK_IT 0x0b /* Link cmd ok + int */ 193 #define AHA_SEL_TIMEOUT 0x11 /* Selection time out */ 194 #define AHA_OVER_UNDER 0x12 /* Data over/under run */ 195 #define AHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ 196 #define AHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ 197 #define AHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ 198 #define AHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ 199 #define AHA_BAD_LINK 0x17 /* Not same values of LUN for links */ 200 #define AHA_INV_TARGET 0x18 /* Invalid target direction */ 201 #define AHA_CCB_DUP 0x19 /* Duplicate CCB received */ 202 #define AHA_INV_CCB 0x1a /* Invalid CCB or segment list */ 203 204 struct aha_revision { 205 struct { 206 u_char opcode; 207 } cmd; 208 struct { 209 u_char boardid; /* type of board */ 210 /* 0x31 = AHA-1540 */ 211 /* 0x41 = AHA-1540A/1542A/1542B */ 212 /* 0x42 = AHA-1640 */ 213 /* 0x43 = AHA-1542C */ 214 /* 0x44 = AHA-1542CF */ 215 /* 0x45 = AHA-1542CF, BIOS v2.01 */ 216 /* 0x46 = AHA-1542CP */ 217 u_char spec_opts; /* special options ID */ 218 /* 0x41 = Board is standard model */ 219 u_char revision_1; /* firmware revision [0-9A-Z] */ 220 u_char revision_2; /* firmware revision [0-9A-Z] */ 221 } reply; 222 }; 223 224 struct aha_extbios { 225 struct { 226 u_char opcode; 227 } cmd; 228 struct { 229 u_char flags; /* Bit 3 == 1 extended bios enabled */ 230 u_char mailboxlock; /* mail box lock code to unlock it */ 231 } reply; 232 }; 233 234 struct aha_toggle { 235 struct { 236 u_char opcode; 237 u_char enable; 238 } cmd; 239 }; 240 241 struct aha_config { 242 struct { 243 u_char opcode; 244 } cmd; 245 struct { 246 u_char chan; 247 u_char intr; 248 u_char scsi_dev:3; 249 u_char :5; 250 } reply; 251 }; 252 253 struct aha_mailbox { 254 struct { 255 u_char opcode; 256 u_char nmbx; 257 physaddr addr; 258 } cmd; 259 }; 260 261 struct aha_unlock { 262 struct { 263 u_char opcode; 264 u_char junk; 265 u_char magic; 266 } cmd; 267 }; 268 269 struct aha_devices { 270 struct { 271 u_char opcode; 272 } cmd; 273 struct { 274 u_char junk[8]; 275 } reply; 276 }; 277 278 struct aha_setup { 279 struct { 280 u_char opcode; 281 u_char len; 282 } cmd; 283 struct { 284 u_char sync_neg:1; 285 u_char parity:1; 286 u_char :6; 287 u_char speed; 288 u_char bus_on; 289 u_char bus_off; 290 u_char num_mbx; 291 u_char mbx[3]; 292 struct { 293 u_char offset:4; 294 u_char period:3; 295 u_char valid:1; 296 } sync[8]; 297 u_char disc_sts; 298 } reply; 299 }; 300 301 #define INT9 0x01 302 #define INT10 0x02 303 #define INT11 0x04 304 #define INT12 0x08 305 #define INT14 0x20 306 #define INT15 0x40 307 308 #define EISADMA 0x00 309 #define CHAN0 0x01 310 #define CHAN5 0x20 311 #define CHAN6 0x40 312 #define CHAN7 0x80 313
Indexes created Mon Sep 29 18:09:42 GMT 2025