ahareg.h revision 1.13
1 /* $NetBSD: ahareg.h,v 1.13 2008/03/29 17:27:50 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1997-99 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Originally written by Julian Elischer (julian (at) tfs.com) 42 * for TRW Financial Systems for use under the MACH(2.5) operating system. 43 * 44 * TRW Financial Systems, in accordance with their agreement with Carnegie 45 * Mellon University, makes this software available to CMU to distribute 46 * or use in any manner that they see fit as long as this message is kept with 47 * the software. For this reason TFS also grants any other persons or 48 * organisations permission to use or modify this software. 49 * 50 * TFS supplies this software to be publicly redistributed 51 * on the understanding that TFS is not responsible for the correct 52 * functioning of this software in any circumstances. 53 */ 54 55 typedef u_int8_t physaddr[3]; 56 typedef u_int8_t physlen[3]; 57 #define ltophys _lto3b 58 #define phystol _3btol 59 60 /* 61 * I/O port offsets 62 */ 63 #define AHA_CTRL_PORT 0 /* control (wo) */ 64 #define AHA_STAT_PORT 0 /* status (ro) */ 65 #define AHA_CMD_PORT 1 /* command (wo) */ 66 #define AHA_DATA_PORT 1 /* data (ro) */ 67 #define AHA_INTR_PORT 2 /* interrupt status (ro) */ 68 69 /* 70 * AHA_CTRL bits 71 */ 72 #define AHA_CTRL_HRST 0x80 /* Hardware reset */ 73 #define AHA_CTRL_SRST 0x40 /* Software reset */ 74 #define AHA_CTRL_IRST 0x20 /* Interrupt reset */ 75 #define AHA_CTRL_SCRST 0x10 /* SCSI bus reset */ 76 77 /* 78 * AHA_STAT bits 79 */ 80 #define AHA_STAT_STST 0x80 /* Self test in Progress */ 81 #define AHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ 82 #define AHA_STAT_INIT 0x20 /* Mbx Init required */ 83 #define AHA_STAT_IDLE 0x10 /* Host Adapter Idle */ 84 #define AHA_STAT_CDF 0x08 /* cmd/data out port full */ 85 #define AHA_STAT_DF 0x04 /* Data in port full */ 86 #define AHA_STAT_RSVD 0x02 /* Unused */ 87 #define AHA_STAT_INVDCMD 0x01 /* Invalid command */ 88 89 /* 90 * AHA_CMD opcodes 91 */ 92 #define AHA_NOP 0x00 /* No operation */ 93 #define AHA_MBX_INIT 0x01 /* Mbx initialization */ 94 #define AHA_START_SCSI 0x02 /* start scsi command */ 95 #define AHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ 96 #define AHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ 97 #if 0 98 #define AHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ 99 #define AHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ 100 #define AHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ 101 #define AHA_SPEED_SET 0x09 /* set transfer speed */ 102 #endif 103 #define AHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ 104 #define AHA_INQUIRE_CONFIG 0x0b /* return configuration data */ 105 #define AHA_TARGET_EN 0x0c /* enable target mode */ 106 #define AHA_INQUIRE_SETUP 0x0d /* return setup data */ 107 #define AHA_ECHO 0x1e /* Echo command data */ 108 #define AHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ 109 #define AHA_EXT_BIOS 0x28 /* return extended bios info */ 110 #define AHA_MBX_ENABLE 0x29 /* enable mail box interface */ 111 112 /* 113 * AHA_INTR bits 114 */ 115 #define AHA_INTR_ANYINTR 0x80 /* Any interrupt */ 116 #define AHA_INTR_RSVD 0x70 /* unused bits */ 117 #define AHA_INTR_SCRD 0x08 /* SCSI reset detected */ 118 #define AHA_INTR_HACC 0x04 /* Command complete */ 119 #define AHA_INTR_MBOA 0x02 /* MBX out empty */ 120 #define AHA_INTR_MBIF 0x01 /* MBX in full */ 121 122 /* 123 * AHA Board IDs 124 */ 125 #define BOARD_1540_16HEAD_BIOS 0x00 126 #define BOARD_1540_64HEAD_BIOS 0x30 127 #define BOARD_1540 0x31 128 #define BOARD_1542 0x41 /* aha-1540/1542 w/64-h bios */ 129 #define BOARD_1640 0x42 /* aha-1640 */ 130 #define BOARD_1740 0x43 /* aha-1740A/1742A/1744 */ 131 #define BOARD_1542C 0x44 /* aha-1542C */ 132 #define BOARD_1542CF 0x45 /* aha-1542CF */ 133 #define BOARD_1542CP 0x46 /* aha-1542CP, plug and play */ 134 135 struct aha_mbx_out { 136 u_char cmd; 137 physaddr ccb_addr; 138 }; 139 140 struct aha_mbx_in { 141 u_char stat; 142 physaddr ccb_addr; 143 }; 144 145 /* 146 * mbo.cmd values 147 */ 148 #define AHA_MBO_FREE 0x0 /* MBO entry is free */ 149 #define AHA_MBO_START 0x1 /* MBO activate entry */ 150 #define AHA_MBO_ABORT 0x2 /* MBO abort entry */ 151 152 /* 153 * mbi.stat values 154 */ 155 #define AHA_MBI_FREE 0x0 /* MBI entry is free */ 156 #define AHA_MBI_OK 0x1 /* completed without error */ 157 #define AHA_MBI_ABORT 0x2 /* aborted ccb */ 158 #define AHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ 159 #define AHA_MBI_ERROR 0x4 /* Completed with error */ 160 161 /* FOR OLD VERSIONS OF THE !%$@ this may have to be 16 (yuk) */ 162 #define AHA_NSEG 17 /* Number of scatter gather segments <= 16 */ 163 /* allow 64 K i/o (min) */ 164 165 struct aha_scat_gath { 166 physlen seg_len; 167 physaddr seg_addr; 168 }; 169 170 struct aha_ccb { 171 u_char opcode; 172 u_char lun:3; 173 u_char data_in:1; /* must be 0 */ 174 u_char data_out:1; /* must be 0 */ 175 u_char target:3; 176 u_char scsi_cmd_length; 177 u_char req_sense_length; 178 physlen data_length; 179 physaddr data_addr; 180 physaddr link_addr; 181 u_char link_id; 182 u_char host_stat; 183 u_char target_stat; 184 u_char reserved[2]; 185 u_char scsi_cmd[12]; 186 struct scsi_sense_data scsi_sense; 187 struct aha_scat_gath scat_gath[AHA_NSEG]; 188 /*----------------------------------------------------------------*/ 189 TAILQ_ENTRY(aha_ccb) chain; 190 struct aha_ccb *nexthash; 191 u_long hashkey; 192 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ 193 int flags; 194 #define CCB_ALLOC 0x01 195 #define CCB_ABORT 0x02 196 #ifdef AHADIAG 197 #define CCB_SENDING 0x04 198 #endif 199 int timeout; 200 201 /* 202 * This DMA map maps the buffer involved in the transfer. 203 * Its contents are loaded into "scat_gath" above. 204 */ 205 bus_dmamap_t dmamap_xfer; 206 }; 207 208 /* 209 * opcode fields 210 */ 211 #define AHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ 212 #define AHA_TARGET_CCB 0x01 /* SCSI Target CCB */ 213 #define AHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scatter gather */ 214 #define AHA_RESET_CCB 0x81 /* SCSI Bus reset */ 215 216 /* 217 * aha_ccb.host_stat values 218 */ 219 #define AHA_OK 0x00 /* cmd ok */ 220 #define AHA_LINK_OK 0x0a /* Link cmd ok */ 221 #define AHA_LINK_IT 0x0b /* Link cmd ok + int */ 222 #define AHA_SEL_TIMEOUT 0x11 /* Selection time out */ 223 #define AHA_OVER_UNDER 0x12 /* Data over/under run */ 224 #define AHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ 225 #define AHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ 226 #define AHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ 227 #define AHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ 228 #define AHA_BAD_LINK 0x17 /* Not same values of LUN for links */ 229 #define AHA_INV_TARGET 0x18 /* Invalid target direction */ 230 #define AHA_CCB_DUP 0x19 /* Duplicate CCB received */ 231 #define AHA_INV_CCB 0x1a /* Invalid CCB or segment list */ 232 233 struct aha_revision { 234 struct { 235 u_char opcode; 236 } cmd; 237 struct { 238 u_char boardid; /* type of board */ 239 /* 0x31 = AHA-1540 */ 240 /* 0x41 = AHA-1540A/1542A/1542B */ 241 /* 0x42 = AHA-1640 */ 242 /* 0x43 = AHA-1542C */ 243 /* 0x44 = AHA-1542CF */ 244 /* 0x45 = AHA-1542CF, BIOS v2.01 */ 245 /* 0x46 = AHA-1542CP */ 246 u_char spec_opts; /* special options ID */ 247 /* 0x41 = Board is standard model */ 248 u_char revision_1; /* firmware revision [0-9A-Z] */ 249 u_char revision_2; /* firmware revision [0-9A-Z] */ 250 } reply; 251 }; 252 253 struct aha_extbios { 254 struct { 255 u_char opcode; 256 } cmd; 257 struct { 258 u_char flags; /* Bit 3 == 1 extended bios enabled */ 259 u_char mailboxlock; /* mail box lock code to unlock it */ 260 } reply; 261 }; 262 263 struct aha_toggle { 264 struct { 265 u_char opcode; 266 u_char enable; 267 } cmd; 268 }; 269 270 struct aha_config { 271 struct { 272 u_char opcode; 273 } cmd; 274 struct { 275 u_char chan; 276 u_char intr; 277 u_char scsi_dev:3; 278 u_char :5; 279 } reply; 280 }; 281 282 struct aha_mailbox { 283 struct { 284 u_char opcode; 285 u_char nmbx; 286 physaddr addr; 287 } cmd; 288 }; 289 290 struct aha_unlock { 291 struct { 292 u_char opcode; 293 u_char junk; 294 u_char magic; 295 } cmd; 296 }; 297 298 struct aha_devices { 299 struct { 300 u_char opcode; 301 } cmd; 302 struct { 303 u_char lun_map[8]; 304 } reply; 305 }; 306 307 struct aha_setup { 308 struct { 309 u_char opcode; 310 u_char len; 311 } cmd; 312 struct { 313 u_char sync_neg:1; 314 u_char parity:1; 315 u_char :6; 316 u_char speed; 317 u_char bus_on; 318 u_char bus_off; 319 u_char num_mbx; 320 u_char mbx[3]; 321 struct { 322 u_char offset:4; 323 u_char period:3; 324 u_char valid:1; 325 } sync[8]; 326 u_char disc_sts; 327 } reply; 328 }; 329 330 #define INT9 0x01 331 #define INT10 0x02 332 #define INT11 0x04 333 #define INT12 0x08 334 #define INT14 0x20 335 #define INT15 0x40 336 337 #define EISADMA 0x00 338 #define CHAN0 0x01 339 #define CHAN5 0x20 340 #define CHAN6 0x40 341 #define CHAN7 0x80 342
Indexes created Sun Sep 28 16:09:52 GMT 2025