ahareg.h revision 1.6
1 /* $NetBSD: ahareg.h,v 1.6 1997/09/09 18:56:15 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Charles M. Hannum. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * Originally written by Julian Elischer (julian (at) tfs.com) 71 * for TRW Financial Systems for use under the MACH(2.5) operating system. 72 * 73 * TRW Financial Systems, in accordance with their agreement with Carnegie 74 * Mellon University, makes this software available to CMU to distribute 75 * or use in any manner that they see fit as long as this message is kept with 76 * the software. For this reason TFS also grants any other persons or 77 * organisations permission to use or modify this software. 78 * 79 * TFS supplies this software to be publicly redistributed 80 * on the understanding that TFS is not responsible for the correct 81 * functioning of this software in any circumstances. 82 */ 83 84 typedef u_int8_t physaddr[3]; 85 typedef u_int8_t physlen[3]; 86 #define ltophys _lto3b 87 #define phystol _3btol 88 89 /* 90 * I/O port offsets 91 */ 92 #define AHA_CTRL_PORT 0 /* control (wo) */ 93 #define AHA_STAT_PORT 0 /* status (ro) */ 94 #define AHA_CMD_PORT 1 /* command (wo) */ 95 #define AHA_DATA_PORT 1 /* data (ro) */ 96 #define AHA_INTR_PORT 2 /* interrupt status (ro) */ 97 98 /* 99 * AHA_CTRL bits 100 */ 101 #define AHA_CTRL_HRST 0x80 /* Hardware reset */ 102 #define AHA_CTRL_SRST 0x40 /* Software reset */ 103 #define AHA_CTRL_IRST 0x20 /* Interrupt reset */ 104 #define AHA_CTRL_SCRST 0x10 /* SCSI bus reset */ 105 106 /* 107 * AHA_STAT bits 108 */ 109 #define AHA_STAT_STST 0x80 /* Self test in Progress */ 110 #define AHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ 111 #define AHA_STAT_INIT 0x20 /* Mbx Init required */ 112 #define AHA_STAT_IDLE 0x10 /* Host Adapter Idle */ 113 #define AHA_STAT_CDF 0x08 /* cmd/data out port full */ 114 #define AHA_STAT_DF 0x04 /* Data in port full */ 115 #define AHA_STAT_INVDCMD 0x01 /* Invalid command */ 116 117 /* 118 * AHA_CMD opcodes 119 */ 120 #define AHA_NOP 0x00 /* No operation */ 121 #define AHA_MBX_INIT 0x01 /* Mbx initialization */ 122 #define AHA_START_SCSI 0x02 /* start scsi command */ 123 #define AHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ 124 #define AHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ 125 #if 0 126 #define AHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ 127 #define AHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ 128 #define AHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ 129 #define AHA_SPEED_SET 0x09 /* set transfer speed */ 130 #endif 131 #define AHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ 132 #define AHA_INQUIRE_CONFIG 0x0b /* return configuration data */ 133 #define AHA_TARGET_EN 0x0c /* enable target mode */ 134 #define AHA_INQUIRE_SETUP 0x0d /* return setup data */ 135 #define AHA_ECHO 0x1e /* Echo command data */ 136 #define AHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ 137 #define AHA_EXT_BIOS 0x28 /* return extended bios info */ 138 #define AHA_MBX_ENABLE 0x29 /* enable mail box interface */ 139 140 /* 141 * AHA_INTR bits 142 */ 143 #define AHA_INTR_ANYINTR 0x80 /* Any interrupt */ 144 #define AHA_INTR_SCRD 0x08 /* SCSI reset detected */ 145 #define AHA_INTR_HACC 0x04 /* Command complete */ 146 #define AHA_INTR_MBOA 0x02 /* MBX out empty */ 147 #define AHA_INTR_MBIF 0x01 /* MBX in full */ 148 149 struct aha_mbx_out { 150 u_char cmd; 151 physaddr ccb_addr; 152 }; 153 154 struct aha_mbx_in { 155 u_char stat; 156 physaddr ccb_addr; 157 }; 158 159 /* 160 * mbo.cmd values 161 */ 162 #define AHA_MBO_FREE 0x0 /* MBO entry is free */ 163 #define AHA_MBO_START 0x1 /* MBO activate entry */ 164 #define AHA_MBO_ABORT 0x2 /* MBO abort entry */ 165 166 /* 167 * mbi.stat values 168 */ 169 #define AHA_MBI_FREE 0x0 /* MBI entry is free */ 170 #define AHA_MBI_OK 0x1 /* completed without error */ 171 #define AHA_MBI_ABORT 0x2 /* aborted ccb */ 172 #define AHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ 173 #define AHA_MBI_ERROR 0x4 /* Completed with error */ 174 175 /* FOR OLD VERSIONS OF THE !%$@ this may have to be 16 (yuk) */ 176 #define AHA_NSEG 17 /* Number of scatter gather segments <= 16 */ 177 /* allow 64 K i/o (min) */ 178 179 struct aha_scat_gath { 180 physlen seg_len; 181 physaddr seg_addr; 182 }; 183 184 struct aha_ccb { 185 u_char opcode; 186 u_char lun:3; 187 u_char data_in:1; /* must be 0 */ 188 u_char data_out:1; /* must be 0 */ 189 u_char target:3; 190 u_char scsi_cmd_length; 191 u_char req_sense_length; 192 physlen data_length; 193 physaddr data_addr; 194 physaddr link_addr; 195 u_char link_id; 196 u_char host_stat; 197 u_char target_stat; 198 u_char reserved[2]; 199 struct scsi_generic scsi_cmd; 200 struct scsipi_sense_data scsi_sense; 201 struct aha_scat_gath scat_gath[AHA_NSEG]; 202 /*----------------------------------------------------------------*/ 203 TAILQ_ENTRY(aha_ccb) chain; 204 struct aha_ccb *nexthash; 205 u_long hashkey; 206 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ 207 int flags; 208 #define CCB_ALLOC 0x01 209 #define CCB_ABORT 0x02 210 #ifdef AHADIAG 211 #define CCB_SENDING 0x04 212 #endif 213 int timeout; 214 215 /* 216 * DMA maps used by the CCB. These maps are created 217 * in aha_init_ccb(). 218 */ 219 220 /* 221 * This DMA map maps an individual CCB. This map is permanently 222 * loaded in aha_init_ccb(). 223 */ 224 bus_dmamap_t dmamap_self; 225 226 /* 227 * This DMA map maps the buffer involved in the transfer. 228 * Its contents are loaded into "scat_gath" above. 229 */ 230 bus_dmamap_t dmamap_xfer; 231 }; 232 233 /* 234 * opcode fields 235 */ 236 #define AHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ 237 #define AHA_TARGET_CCB 0x01 /* SCSI Target CCB */ 238 #define AHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scatter gather */ 239 #define AHA_RESET_CCB 0x81 /* SCSI Bus reset */ 240 241 /* 242 * aha_ccb.host_stat values 243 */ 244 #define AHA_OK 0x00 /* cmd ok */ 245 #define AHA_LINK_OK 0x0a /* Link cmd ok */ 246 #define AHA_LINK_IT 0x0b /* Link cmd ok + int */ 247 #define AHA_SEL_TIMEOUT 0x11 /* Selection time out */ 248 #define AHA_OVER_UNDER 0x12 /* Data over/under run */ 249 #define AHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ 250 #define AHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ 251 #define AHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ 252 #define AHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ 253 #define AHA_BAD_LINK 0x17 /* Not same values of LUN for links */ 254 #define AHA_INV_TARGET 0x18 /* Invalid target direction */ 255 #define AHA_CCB_DUP 0x19 /* Duplicate CCB received */ 256 #define AHA_INV_CCB 0x1a /* Invalid CCB or segment list */ 257 258 struct aha_revision { 259 struct { 260 u_char opcode; 261 } cmd; 262 struct { 263 u_char boardid; /* type of board */ 264 /* 0x31 = AHA-1540 */ 265 /* 0x41 = AHA-1540A/1542A/1542B */ 266 /* 0x42 = AHA-1640 */ 267 /* 0x43 = AHA-1542C */ 268 /* 0x44 = AHA-1542CF */ 269 /* 0x45 = AHA-1542CF, BIOS v2.01 */ 270 /* 0x46 = AHA-1542CP */ 271 u_char spec_opts; /* special options ID */ 272 /* 0x41 = Board is standard model */ 273 u_char revision_1; /* firmware revision [0-9A-Z] */ 274 u_char revision_2; /* firmware revision [0-9A-Z] */ 275 } reply; 276 }; 277 278 struct aha_extbios { 279 struct { 280 u_char opcode; 281 } cmd; 282 struct { 283 u_char flags; /* Bit 3 == 1 extended bios enabled */ 284 u_char mailboxlock; /* mail box lock code to unlock it */ 285 } reply; 286 }; 287 288 struct aha_toggle { 289 struct { 290 u_char opcode; 291 u_char enable; 292 } cmd; 293 }; 294 295 struct aha_config { 296 struct { 297 u_char opcode; 298 } cmd; 299 struct { 300 u_char chan; 301 u_char intr; 302 u_char scsi_dev:3; 303 u_char :5; 304 } reply; 305 }; 306 307 struct aha_mailbox { 308 struct { 309 u_char opcode; 310 u_char nmbx; 311 physaddr addr; 312 } cmd; 313 }; 314 315 struct aha_unlock { 316 struct { 317 u_char opcode; 318 u_char junk; 319 u_char magic; 320 } cmd; 321 }; 322 323 struct aha_devices { 324 struct { 325 u_char opcode; 326 } cmd; 327 struct { 328 u_char lun_map[8]; 329 } reply; 330 }; 331 332 struct aha_setup { 333 struct { 334 u_char opcode; 335 u_char len; 336 } cmd; 337 struct { 338 u_char sync_neg:1; 339 u_char parity:1; 340 u_char :6; 341 u_char speed; 342 u_char bus_on; 343 u_char bus_off; 344 u_char num_mbx; 345 u_char mbx[3]; 346 struct { 347 u_char offset:4; 348 u_char period:3; 349 u_char valid:1; 350 } sync[8]; 351 u_char disc_sts; 352 } reply; 353 }; 354 355 #define INT9 0x01 356 #define INT10 0x02 357 #define INT11 0x04 358 #define INT12 0x08 359 #define INT14 0x20 360 #define INT15 0x40 361 362 #define EISADMA 0x00 363 #define CHAN0 0x01 364 #define CHAN5 0x20 365 #define CHAN6 0x40 366 #define CHAN7 0x80 367
Indexes created Fri Sep 26 20:09:58 GMT 2025