ahareg.h revision 1.9
1 /* $NetBSD: ahareg.h,v 1.9 1999/04/15 23:51:45 mjl Exp $ */ 2 3 /*- 4 * Copyright (c) 1997-99 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Originally written by Julian Elischer (julian (at) tfs.com) 42 * for TRW Financial Systems for use under the MACH(2.5) operating system. 43 * 44 * TRW Financial Systems, in accordance with their agreement with Carnegie 45 * Mellon University, makes this software available to CMU to distribute 46 * or use in any manner that they see fit as long as this message is kept with 47 * the software. For this reason TFS also grants any other persons or 48 * organisations permission to use or modify this software. 49 * 50 * TFS supplies this software to be publicly redistributed 51 * on the understanding that TFS is not responsible for the correct 52 * functioning of this software in any circumstances. 53 */ 54 55 typedef u_int8_t physaddr[3]; 56 typedef u_int8_t physlen[3]; 57 #define ltophys _lto3b 58 #define phystol _3btol 59 60 /* 61 * I/O port offsets 62 */ 63 #define AHA_CTRL_PORT 0 /* control (wo) */ 64 #define AHA_STAT_PORT 0 /* status (ro) */ 65 #define AHA_CMD_PORT 1 /* command (wo) */ 66 #define AHA_DATA_PORT 1 /* data (ro) */ 67 #define AHA_INTR_PORT 2 /* interrupt status (ro) */ 68 69 /* 70 * AHA_CTRL bits 71 */ 72 #define AHA_CTRL_HRST 0x80 /* Hardware reset */ 73 #define AHA_CTRL_SRST 0x40 /* Software reset */ 74 #define AHA_CTRL_IRST 0x20 /* Interrupt reset */ 75 #define AHA_CTRL_SCRST 0x10 /* SCSI bus reset */ 76 77 /* 78 * AHA_STAT bits 79 */ 80 #define AHA_STAT_STST 0x80 /* Self test in Progress */ 81 #define AHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ 82 #define AHA_STAT_INIT 0x20 /* Mbx Init required */ 83 #define AHA_STAT_IDLE 0x10 /* Host Adapter Idle */ 84 #define AHA_STAT_CDF 0x08 /* cmd/data out port full */ 85 #define AHA_STAT_DF 0x04 /* Data in port full */ 86 #define AHA_STAT_INVDCMD 0x01 /* Invalid command */ 87 88 /* 89 * AHA_CMD opcodes 90 */ 91 #define AHA_NOP 0x00 /* No operation */ 92 #define AHA_MBX_INIT 0x01 /* Mbx initialization */ 93 #define AHA_START_SCSI 0x02 /* start scsi command */ 94 #define AHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ 95 #define AHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ 96 #if 0 97 #define AHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ 98 #define AHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ 99 #define AHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ 100 #define AHA_SPEED_SET 0x09 /* set transfer speed */ 101 #endif 102 #define AHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ 103 #define AHA_INQUIRE_CONFIG 0x0b /* return configuration data */ 104 #define AHA_TARGET_EN 0x0c /* enable target mode */ 105 #define AHA_INQUIRE_SETUP 0x0d /* return setup data */ 106 #define AHA_ECHO 0x1e /* Echo command data */ 107 #define AHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ 108 #define AHA_EXT_BIOS 0x28 /* return extended bios info */ 109 #define AHA_MBX_ENABLE 0x29 /* enable mail box interface */ 110 111 /* 112 * AHA_INTR bits 113 */ 114 #define AHA_INTR_ANYINTR 0x80 /* Any interrupt */ 115 #define AHA_INTR_SCRD 0x08 /* SCSI reset detected */ 116 #define AHA_INTR_HACC 0x04 /* Command complete */ 117 #define AHA_INTR_MBOA 0x02 /* MBX out empty */ 118 #define AHA_INTR_MBIF 0x01 /* MBX in full */ 119 120 /* 121 * AHA Board IDs 122 */ 123 #define BOARD_1540_16HEAD_BIOS 0x00 124 #define BOARD_1540_64HEAD_BIOS 0x30 125 #define BOARD_1540 0x31 126 #define BOARD_1542 0x41 /* aha-1540/1542 w/64-h bios */ 127 #define BOARD_1640 0x42 /* aha-1640 */ 128 #define BOARD_1740 0x43 /* aha-1740A/1742A/1744 */ 129 #define BOARD_1542C 0x44 /* aha-1542C */ 130 #define BOARD_1542CF 0x45 /* aha-1542CF */ 131 #define BOARD_1542CP 0x46 /* aha-1542CP, plug and play */ 132 133 struct aha_mbx_out { 134 u_char cmd; 135 physaddr ccb_addr; 136 }; 137 138 struct aha_mbx_in { 139 u_char stat; 140 physaddr ccb_addr; 141 }; 142 143 /* 144 * mbo.cmd values 145 */ 146 #define AHA_MBO_FREE 0x0 /* MBO entry is free */ 147 #define AHA_MBO_START 0x1 /* MBO activate entry */ 148 #define AHA_MBO_ABORT 0x2 /* MBO abort entry */ 149 150 /* 151 * mbi.stat values 152 */ 153 #define AHA_MBI_FREE 0x0 /* MBI entry is free */ 154 #define AHA_MBI_OK 0x1 /* completed without error */ 155 #define AHA_MBI_ABORT 0x2 /* aborted ccb */ 156 #define AHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ 157 #define AHA_MBI_ERROR 0x4 /* Completed with error */ 158 159 /* FOR OLD VERSIONS OF THE !%$@ this may have to be 16 (yuk) */ 160 #define AHA_NSEG 17 /* Number of scatter gather segments <= 16 */ 161 /* allow 64 K i/o (min) */ 162 163 struct aha_scat_gath { 164 physlen seg_len; 165 physaddr seg_addr; 166 }; 167 168 struct aha_ccb { 169 u_char opcode; 170 u_char lun:3; 171 u_char data_in:1; /* must be 0 */ 172 u_char data_out:1; /* must be 0 */ 173 u_char target:3; 174 u_char scsi_cmd_length; 175 u_char req_sense_length; 176 physlen data_length; 177 physaddr data_addr; 178 physaddr link_addr; 179 u_char link_id; 180 u_char host_stat; 181 u_char target_stat; 182 u_char reserved[2]; 183 struct scsi_generic scsi_cmd; 184 struct scsipi_sense_data scsi_sense; 185 struct aha_scat_gath scat_gath[AHA_NSEG]; 186 /*----------------------------------------------------------------*/ 187 TAILQ_ENTRY(aha_ccb) chain; 188 struct aha_ccb *nexthash; 189 u_long hashkey; 190 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ 191 int flags; 192 #define CCB_ALLOC 0x01 193 #define CCB_ABORT 0x02 194 #ifdef AHADIAG 195 #define CCB_SENDING 0x04 196 #endif 197 int timeout; 198 199 /* 200 * This DMA map maps the buffer involved in the transfer. 201 * Its contents are loaded into "scat_gath" above. 202 */ 203 bus_dmamap_t dmamap_xfer; 204 }; 205 206 /* 207 * opcode fields 208 */ 209 #define AHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ 210 #define AHA_TARGET_CCB 0x01 /* SCSI Target CCB */ 211 #define AHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scatter gather */ 212 #define AHA_RESET_CCB 0x81 /* SCSI Bus reset */ 213 214 /* 215 * aha_ccb.host_stat values 216 */ 217 #define AHA_OK 0x00 /* cmd ok */ 218 #define AHA_LINK_OK 0x0a /* Link cmd ok */ 219 #define AHA_LINK_IT 0x0b /* Link cmd ok + int */ 220 #define AHA_SEL_TIMEOUT 0x11 /* Selection time out */ 221 #define AHA_OVER_UNDER 0x12 /* Data over/under run */ 222 #define AHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ 223 #define AHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ 224 #define AHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ 225 #define AHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ 226 #define AHA_BAD_LINK 0x17 /* Not same values of LUN for links */ 227 #define AHA_INV_TARGET 0x18 /* Invalid target direction */ 228 #define AHA_CCB_DUP 0x19 /* Duplicate CCB received */ 229 #define AHA_INV_CCB 0x1a /* Invalid CCB or segment list */ 230 231 struct aha_revision { 232 struct { 233 u_char opcode; 234 } cmd; 235 struct { 236 u_char boardid; /* type of board */ 237 /* 0x31 = AHA-1540 */ 238 /* 0x41 = AHA-1540A/1542A/1542B */ 239 /* 0x42 = AHA-1640 */ 240 /* 0x43 = AHA-1542C */ 241 /* 0x44 = AHA-1542CF */ 242 /* 0x45 = AHA-1542CF, BIOS v2.01 */ 243 /* 0x46 = AHA-1542CP */ 244 u_char spec_opts; /* special options ID */ 245 /* 0x41 = Board is standard model */ 246 u_char revision_1; /* firmware revision [0-9A-Z] */ 247 u_char revision_2; /* firmware revision [0-9A-Z] */ 248 } reply; 249 }; 250 251 struct aha_extbios { 252 struct { 253 u_char opcode; 254 } cmd; 255 struct { 256 u_char flags; /* Bit 3 == 1 extended bios enabled */ 257 u_char mailboxlock; /* mail box lock code to unlock it */ 258 } reply; 259 }; 260 261 struct aha_toggle { 262 struct { 263 u_char opcode; 264 u_char enable; 265 } cmd; 266 }; 267 268 struct aha_config { 269 struct { 270 u_char opcode; 271 } cmd; 272 struct { 273 u_char chan; 274 u_char intr; 275 u_char scsi_dev:3; 276 u_char :5; 277 } reply; 278 }; 279 280 struct aha_mailbox { 281 struct { 282 u_char opcode; 283 u_char nmbx; 284 physaddr addr; 285 } cmd; 286 }; 287 288 struct aha_unlock { 289 struct { 290 u_char opcode; 291 u_char junk; 292 u_char magic; 293 } cmd; 294 }; 295 296 struct aha_devices { 297 struct { 298 u_char opcode; 299 } cmd; 300 struct { 301 u_char lun_map[8]; 302 } reply; 303 }; 304 305 struct aha_setup { 306 struct { 307 u_char opcode; 308 u_char len; 309 } cmd; 310 struct { 311 u_char sync_neg:1; 312 u_char parity:1; 313 u_char :6; 314 u_char speed; 315 u_char bus_on; 316 u_char bus_off; 317 u_char num_mbx; 318 u_char mbx[3]; 319 struct { 320 u_char offset:4; 321 u_char period:3; 322 u_char valid:1; 323 } sync[8]; 324 u_char disc_sts; 325 } reply; 326 }; 327 328 #define INT9 0x01 329 #define INT10 0x02 330 #define INT11 0x04 331 #define INT12 0x08 332 #define INT14 0x20 333 #define INT15 0x40 334 335 #define EISADMA 0x00 336 #define CHAN0 0x01 337 #define CHAN5 0x20 338 #define CHAN6 0x40 339 #define CHAN7 0x80 340
Indexes created Sun Sep 28 16:09:52 GMT 2025