aic79xx_inline.h revision 1.6
1 /* $NetBSD: aic79xx_inline.h,v 1.6 2003/08/29 00:46:06 thorpej Exp $ */ 2 3 /* 4 * Inline routines shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2003 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * Id: //depot/aic7xxx/aic7xxx/aic79xx_inline.h#49 $ 43 * 44 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_inline.h,v 1.10 2003/05/26 21:18:48 gibbs Exp $ 45 */ 46 /* 47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 48 */ 49 50 #ifndef _AIC79XX_INLINE_H_ 51 #define _AIC79XX_INLINE_H_ 52 53 /******************************** Debugging ***********************************/ 54 static __inline char *ahd_name(struct ahd_softc *); 55 56 static __inline char * 57 ahd_name(struct ahd_softc *ahd) 58 { 59 return (ahd->name); 60 } 61 62 /************************ Sequencer Execution Control *************************/ 63 static __inline void ahd_known_modes(struct ahd_softc *, ahd_mode, ahd_mode); 64 static __inline ahd_mode_state ahd_build_mode_state(struct ahd_softc *, 65 ahd_mode, ahd_mode); 66 static __inline void ahd_extract_mode_state(struct ahd_softc *, 67 ahd_mode_state, ahd_mode *, ahd_mode *); 68 static __inline void ahd_set_modes(struct ahd_softc *, ahd_mode, ahd_mode); 69 static __inline void ahd_update_modes(struct ahd_softc *); 70 static __inline void ahd_assert_modes(struct ahd_softc *, ahd_mode, 71 ahd_mode, const char *, int); 72 static __inline ahd_mode_state ahd_save_modes(struct ahd_softc *); 73 static __inline void ahd_restore_modes(struct ahd_softc *, ahd_mode_state); 74 static __inline int ahd_is_paused(struct ahd_softc *); 75 static __inline void ahd_pause(struct ahd_softc *); 76 static __inline void ahd_unpause(struct ahd_softc *); 77 78 static __inline void 79 ahd_known_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst) 80 { 81 ahd->src_mode = src; 82 ahd->dst_mode = dst; 83 ahd->saved_src_mode = src; 84 ahd->saved_dst_mode = dst; 85 } 86 87 static __inline ahd_mode_state 88 ahd_build_mode_state(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst) 89 { 90 return ((src << SRC_MODE_SHIFT) | (dst << DST_MODE_SHIFT)); 91 } 92 93 static __inline void 94 ahd_extract_mode_state(struct ahd_softc *ahd, ahd_mode_state state, 95 ahd_mode *src, ahd_mode *dst) 96 { 97 *src = (state & SRC_MODE) >> SRC_MODE_SHIFT; 98 *dst = (state & DST_MODE) >> DST_MODE_SHIFT; 99 } 100 101 static __inline void 102 ahd_set_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst) 103 { 104 if (ahd->src_mode == src && ahd->dst_mode == dst) 105 return; 106 #ifdef AHD_DEBUG 107 if (ahd->src_mode == AHD_MODE_UNKNOWN 108 || ahd->dst_mode == AHD_MODE_UNKNOWN) 109 panic("Setting mode prior to saving it.\n"); 110 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0) 111 printf("%s: Setting mode 0x%x\n", ahd_name(ahd), 112 ahd_build_mode_state(ahd, src, dst)); 113 #endif 114 ahd_outb(ahd, MODE_PTR, ahd_build_mode_state(ahd, src, dst)); 115 ahd->src_mode = src; 116 ahd->dst_mode = dst; 117 } 118 119 static __inline void 120 ahd_update_modes(struct ahd_softc *ahd) 121 { 122 ahd_mode_state mode_ptr; 123 ahd_mode src; 124 ahd_mode dst; 125 126 mode_ptr = ahd_inb(ahd, MODE_PTR); 127 #ifdef AHD_DEBUG 128 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0) 129 printf("Reading mode 0x%x\n", mode_ptr); 130 #endif 131 ahd_extract_mode_state(ahd, mode_ptr, &src, &dst); 132 ahd_known_modes(ahd, src, dst); 133 } 134 135 static __inline void 136 ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode, 137 ahd_mode dstmode, const char *file, int line) 138 { 139 #ifdef AHD_DEBUG 140 if ((srcmode & AHD_MK_MSK(ahd->src_mode)) == 0 141 || (dstmode & AHD_MK_MSK(ahd->dst_mode)) == 0) { 142 panic("%s:%s:%d: Mode assertion failed.\n", 143 ahd_name(ahd), file, line); 144 } 145 #endif 146 } 147 148 static __inline ahd_mode_state 149 ahd_save_modes(struct ahd_softc *ahd) 150 { 151 if (ahd->src_mode == AHD_MODE_UNKNOWN 152 || ahd->dst_mode == AHD_MODE_UNKNOWN) 153 ahd_update_modes(ahd); 154 155 return (ahd_build_mode_state(ahd, ahd->src_mode, ahd->dst_mode)); 156 } 157 158 static __inline void 159 ahd_restore_modes(struct ahd_softc *ahd, ahd_mode_state state) 160 { 161 ahd_mode src; 162 ahd_mode dst; 163 164 ahd_extract_mode_state(ahd, state, &src, &dst); 165 ahd_set_modes(ahd, src, dst); 166 } 167 168 #define AHD_ASSERT_MODES(ahd, source, dest) \ 169 ahd_assert_modes(ahd, source, dest, __FILE__, __LINE__); 170 171 /* 172 * Determine whether the sequencer has halted code execution. 173 * Returns non-zero status if the sequencer is stopped. 174 */ 175 static __inline int 176 ahd_is_paused(struct ahd_softc *ahd) 177 { 178 return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0); 179 } 180 181 /* 182 * Request that the sequencer stop and wait, indefinitely, for it 183 * to stop. The sequencer will only acknowledge that it is paused 184 * once it has reached an instruction boundary and PAUSEDIS is 185 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS 186 * for critical sections. 187 */ 188 static __inline void 189 ahd_pause(struct ahd_softc *ahd) 190 { 191 ahd_outb(ahd, HCNTRL, ahd->pause); 192 193 /* 194 * Since the sequencer can disable pausing in a critical section, we 195 * must loop until it actually stops. 196 */ 197 while (ahd_is_paused(ahd) == 0) 198 ; 199 } 200 201 /* 202 * Allow the sequencer to continue program execution. 203 * We check here to ensure that no additional interrupt 204 * sources that would cause the sequencer to halt have been 205 * asserted. If, for example, a SCSI bus reset is detected 206 * while we are fielding a different, pausing, interrupt type, 207 * we don't want to release the sequencer before going back 208 * into our interrupt handler and dealing with this new 209 * condition. 210 */ 211 static __inline void 212 ahd_unpause(struct ahd_softc *ahd) 213 { 214 /* 215 * Automatically restore our modes to those saved 216 * prior to the first change of the mode. 217 */ 218 if (ahd->saved_src_mode != AHD_MODE_UNKNOWN 219 && ahd->saved_dst_mode != AHD_MODE_UNKNOWN) { 220 if ((ahd->flags & AHD_UPDATE_PEND_CMDS) != 0) 221 ahd_reset_cmds_pending(ahd); 222 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 223 } 224 225 if ((ahd_inb(ahd, INTSTAT) & ~CMDCMPLT) == 0) 226 ahd_outb(ahd, HCNTRL, ahd->unpause); 227 228 ahd_known_modes(ahd, AHD_MODE_UNKNOWN, AHD_MODE_UNKNOWN); 229 } 230 231 /*********************** Scatter Gather List Handling *************************/ 232 static __inline void *ahd_sg_setup(struct ahd_softc *, struct scb *, 233 void *, bus_addr_t, bus_size_t, int); 234 static __inline void ahd_setup_scb_common(struct ahd_softc *, struct scb *); 235 static __inline void ahd_setup_data_scb(struct ahd_softc *, struct scb *); 236 static __inline void ahd_setup_noxfer_scb(struct ahd_softc *, struct scb *); 237 238 static __inline void * 239 ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb, 240 void *sgptr, bus_addr_t addr, bus_size_t len, int last) 241 { 242 scb->sg_count++; 243 if (sizeof(bus_addr_t) > 4 244 && (ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 245 struct ahd_dma64_seg *sg; 246 247 sg = (struct ahd_dma64_seg *)sgptr; 248 sg->addr = ahd_htole64(addr); 249 sg->len = ahd_htole32(len | (last ? AHD_DMA_LAST_SEG : 0)); 250 return (sg + 1); 251 } else { 252 struct ahd_dma_seg *sg; 253 254 sg = (struct ahd_dma_seg *)sgptr; 255 sg->addr = ahd_htole32(addr & 0xFFFFFFFF); 256 sg->len = ahd_htole32(len | ((addr >> 8) & 0x7F000000) 257 | (last ? AHD_DMA_LAST_SEG : 0)); 258 return (sg + 1); 259 } 260 } 261 262 static __inline void 263 ahd_setup_scb_common(struct ahd_softc *ahd, struct scb *scb) 264 { 265 /* XXX Handle target mode SCBs. */ 266 scb->crc_retry_count = 0; 267 if ((scb->flags & SCB_PACKETIZED) != 0) { 268 /* XXX what about ACA?? It is type 4, but TAG_TYPE == 0x3. */ 269 scb->hscb->task_attribute= scb->hscb->control & SCB_TAG_TYPE; 270 } 271 272 if (scb->hscb->cdb_len <= MAX_CDB_LEN_WITH_SENSE_ADDR 273 || (scb->hscb->cdb_len & SCB_CDB_LEN_PTR) != 0) 274 scb->hscb->shared_data.idata.cdb_plus_saddr.sense_addr = 275 ahd_htole32(scb->sense_busaddr); 276 } 277 278 static __inline void 279 ahd_setup_data_scb(struct ahd_softc *ahd, struct scb *scb) 280 { 281 /* 282 * Copy the first SG into the "current" data ponter area. 283 */ 284 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 285 struct ahd_dma64_seg *sg; 286 287 sg = (struct ahd_dma64_seg *)scb->sg_list; 288 scb->hscb->dataptr = sg->addr; 289 scb->hscb->datacnt = sg->len; 290 } else { 291 struct ahd_dma_seg *sg; 292 uint32_t *dataptr_words; 293 294 sg = (struct ahd_dma_seg *)scb->sg_list; 295 dataptr_words = (uint32_t*)&scb->hscb->dataptr; 296 dataptr_words[0] = sg->addr; 297 dataptr_words[1] = 0; 298 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) { 299 uint64_t high_addr; 300 301 high_addr = ahd_le32toh(sg->len) & 0x7F000000; 302 scb->hscb->dataptr |= ahd_htole64(high_addr << 8); 303 } 304 scb->hscb->datacnt = sg->len; 305 } 306 /* 307 * Note where to find the SG entries in bus space. 308 * We also set the full residual flag which the 309 * sequencer will clear as soon as a data transfer 310 * occurs. 311 */ 312 scb->hscb->sgptr = ahd_htole32(scb->sg_list_busaddr|SG_FULL_RESID); 313 } 314 315 static __inline void 316 ahd_setup_noxfer_scb(struct ahd_softc *ahd, struct scb *scb) 317 { 318 scb->hscb->sgptr = ahd_htole32(SG_LIST_NULL); 319 scb->hscb->dataptr = 0; 320 scb->hscb->datacnt = 0; 321 } 322 323 /************************** Memory mapping routines ***************************/ 324 static __inline size_t ahd_sg_size(struct ahd_softc *); 325 static __inline void * 326 ahd_sg_bus_to_virt(struct ahd_softc *, struct scb *, 327 uint32_t); 328 static __inline uint32_t 329 ahd_sg_virt_to_bus(struct ahd_softc *, struct scb *, 330 void *); 331 static __inline void ahd_sync_scb(struct ahd_softc *, struct scb *, int); 332 static __inline void ahd_sync_sglist(struct ahd_softc *, struct scb *, int); 333 static __inline void ahd_sync_sense(struct ahd_softc *, struct scb *, int); 334 static __inline uint32_t 335 ahd_targetcmd_offset(struct ahd_softc *, u_int); 336 337 static __inline size_t 338 ahd_sg_size(struct ahd_softc *ahd) 339 { 340 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 341 return (sizeof(struct ahd_dma64_seg)); 342 return (sizeof(struct ahd_dma_seg)); 343 } 344 345 static __inline void * 346 ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr) 347 { 348 bus_addr_t sg_offset; 349 350 /* sg_list_phys points to entry 1, not 0 */ 351 sg_offset = sg_busaddr - (scb->sg_list_busaddr - ahd_sg_size(ahd)); 352 return ((uint8_t *)scb->sg_list + sg_offset); 353 } 354 355 static __inline uint32_t 356 ahd_sg_virt_to_bus(struct ahd_softc *ahd, struct scb *scb, void *sg) 357 { 358 bus_addr_t sg_offset; 359 360 /* sg_list_phys points to entry 1, not 0 */ 361 sg_offset = ((uint8_t *)sg - (uint8_t *)scb->sg_list) 362 - ahd_sg_size(ahd); 363 364 return (scb->sg_list_busaddr + sg_offset); 365 } 366 367 static __inline void 368 ahd_sync_scb(struct ahd_softc *ahd, struct scb *scb, int op) 369 { 370 ahd_dmamap_sync(ahd, ahd->parent_dmat, scb->hscb_map->dmamap, 371 /*offset*/(uint8_t*)scb->hscb - scb->hscb_map->vaddr, 372 /*len*/sizeof(*scb->hscb), op); 373 } 374 375 static __inline void 376 ahd_sync_sglist(struct ahd_softc *ahd, struct scb *scb, int op) 377 { 378 if (scb->sg_count == 0) 379 return; 380 381 ahd_dmamap_sync(ahd, ahd->parent_dmat, scb->sg_map->dmamap, 382 /*offset*/scb->sg_list_busaddr - ahd_sg_size(ahd), 383 /*len*/ahd_sg_size(ahd) * scb->sg_count, op); 384 } 385 386 static __inline void 387 ahd_sync_sense(struct ahd_softc *ahd, struct scb *scb, int op) 388 { 389 ahd_dmamap_sync(ahd, ahd->parent_dmat, 390 scb->sense_map->dmamap, 391 /*offset*/scb->sense_busaddr, 392 /*len*/AHD_SENSE_BUFSIZE, op); 393 } 394 395 static __inline uint32_t 396 ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index) 397 { 398 return (((uint8_t *)&ahd->targetcmds[index]) 399 - (uint8_t *)ahd->qoutfifo); 400 } 401 402 /*********************** Miscelaneous Support Functions ***********************/ 403 static __inline void ahd_complete_scb(struct ahd_softc *, struct scb *); 404 static __inline void ahd_update_residual(struct ahd_softc *, struct scb *); 405 static __inline struct ahd_initiator_tinfo * 406 ahd_fetch_transinfo(struct ahd_softc *, char, u_int, 407 u_int, struct ahd_tmode_tstate **); 408 static __inline uint16_t 409 ahd_inw(struct ahd_softc *, u_int); 410 static __inline void ahd_outw(struct ahd_softc *, u_int, u_int); 411 static __inline uint32_t 412 ahd_inl(struct ahd_softc *, u_int); 413 static __inline void ahd_outl(struct ahd_softc *, u_int, uint32_t); 414 static __inline uint64_t 415 ahd_inq(struct ahd_softc *, u_int); 416 static __inline void ahd_outq(struct ahd_softc *, u_int, uint64_t); 417 static __inline u_int ahd_get_scbptr(struct ahd_softc *); 418 static __inline void ahd_set_scbptr(struct ahd_softc *, u_int); 419 static __inline u_int ahd_get_hnscb_qoff(struct ahd_softc *); 420 static __inline void ahd_set_hnscb_qoff(struct ahd_softc *, u_int); 421 static __inline u_int ahd_get_hescb_qoff(struct ahd_softc *); 422 static __inline void ahd_set_hescb_qoff(struct ahd_softc *, u_int); 423 static __inline u_int ahd_get_snscb_qoff(struct ahd_softc *); 424 static __inline void ahd_set_snscb_qoff(struct ahd_softc *, u_int); 425 static __inline u_int ahd_get_sescb_qoff(struct ahd_softc *); 426 static __inline void ahd_set_sescb_qoff(struct ahd_softc *, u_int); 427 static __inline u_int ahd_get_sdscb_qoff(struct ahd_softc *); 428 static __inline void ahd_set_sdscb_qoff(struct ahd_softc *, u_int); 429 static __inline u_int ahd_inb_scbram(struct ahd_softc *, u_int); 430 static __inline u_int ahd_inw_scbram(struct ahd_softc *, u_int); 431 static __inline uint32_t 432 ahd_inl_scbram(struct ahd_softc *, u_int); 433 static __inline void ahd_swap_with_next_hscb(struct ahd_softc *, 434 struct scb *); 435 static __inline void ahd_queue_scb(struct ahd_softc *, struct scb *); 436 static __inline uint8_t * 437 ahd_get_sense_buf(struct ahd_softc *, struct scb *); 438 static __inline uint32_t 439 ahd_get_sense_bufaddr(struct ahd_softc *, struct scb *); 440 static __inline void ahd_post_scb(struct ahd_softc *, struct scb *); 441 442 443 static __inline void 444 ahd_post_scb(struct ahd_softc *ahd, struct scb *scb) 445 { 446 uint32_t sgptr; 447 448 sgptr = ahd_le32toh(scb->hscb->sgptr); 449 if ((sgptr & SG_STATUS_VALID) != 0) 450 ahd_handle_scb_status(ahd, scb); 451 else 452 ahd_done(ahd, scb); 453 } 454 455 static __inline void 456 ahd_complete_scb(struct ahd_softc *ahd, struct scb *scb) 457 { 458 uint32_t sgptr; 459 460 sgptr = ahd_le32toh(scb->hscb->sgptr); 461 if ((sgptr & SG_STATUS_VALID) != 0) 462 ahd_handle_scb_status(ahd, scb); 463 else 464 ahd_done(ahd, scb); 465 } 466 467 /* 468 * Determine whether the sequencer reported a residual 469 * for this SCB/transaction. 470 */ 471 static __inline void 472 ahd_update_residual(struct ahd_softc *ahd, struct scb *scb) 473 { 474 uint32_t sgptr; 475 476 sgptr = ahd_le32toh(scb->hscb->sgptr); 477 if ((sgptr & SG_STATUS_VALID) != 0) 478 ahd_calc_residual(ahd, scb); 479 } 480 481 /* 482 * Return pointers to the transfer negotiation information 483 * for the specified our_id/remote_id pair. 484 */ 485 static __inline struct ahd_initiator_tinfo * 486 ahd_fetch_transinfo(struct ahd_softc *ahd, char channel, u_int our_id, 487 u_int remote_id, struct ahd_tmode_tstate **tstate) 488 { 489 /* 490 * Transfer data structures are stored from the perspective 491 * of the target role. Since the parameters for a connection 492 * in the initiator role to a given target are the same as 493 * when the roles are reversed, we pretend we are the target. 494 */ 495 if (channel == 'B') 496 our_id += 8; 497 *tstate = ahd->enabled_targets[our_id]; 498 return (&(*tstate)->transinfo[remote_id]); 499 } 500 501 #define AHD_COPY_COL_IDX(dst, src) \ 502 do { \ 503 dst->hscb->scsiid = src->hscb->scsiid; \ 504 dst->hscb->lun = src->hscb->lun; \ 505 } while (0) 506 507 static __inline uint16_t 508 ahd_inw(struct ahd_softc *ahd, u_int port) 509 { 510 return ((ahd_inb(ahd, port+1) << 8) | ahd_inb(ahd, port)); 511 } 512 513 static __inline void 514 ahd_outw(struct ahd_softc *ahd, u_int port, u_int value) 515 { 516 ahd_outb(ahd, port, value & 0xFF); 517 ahd_outb(ahd, port+1, (value >> 8) & 0xFF); 518 } 519 520 static __inline uint32_t 521 ahd_inl(struct ahd_softc *ahd, u_int port) 522 { 523 return ((ahd_inb(ahd, port)) 524 | (ahd_inb(ahd, port+1) << 8) 525 | (ahd_inb(ahd, port+2) << 16) 526 | (ahd_inb(ahd, port+3) << 24)); 527 } 528 529 static __inline void 530 ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value) 531 { 532 ahd_outb(ahd, port, (value) & 0xFF); 533 ahd_outb(ahd, port+1, ((value) >> 8) & 0xFF); 534 ahd_outb(ahd, port+2, ((value) >> 16) & 0xFF); 535 ahd_outb(ahd, port+3, ((value) >> 24) & 0xFF); 536 } 537 538 static __inline uint64_t 539 ahd_inq(struct ahd_softc *ahd, u_int port) 540 { 541 return ((ahd_inb(ahd, port)) 542 | (ahd_inb(ahd, port+1) << 8) 543 | (ahd_inb(ahd, port+2) << 16) 544 | (ahd_inb(ahd, port+3) << 24) 545 | (((uint64_t)ahd_inb(ahd, port+4)) << 32) 546 | (((uint64_t)ahd_inb(ahd, port+5)) << 40) 547 | (((uint64_t)ahd_inb(ahd, port+6)) << 48) 548 | (((uint64_t)ahd_inb(ahd, port+7)) << 56)); 549 } 550 551 static __inline void 552 ahd_outq(struct ahd_softc *ahd, u_int port, uint64_t value) 553 { 554 ahd_outb(ahd, port, value & 0xFF); 555 ahd_outb(ahd, port+1, (value >> 8) & 0xFF); 556 ahd_outb(ahd, port+2, (value >> 16) & 0xFF); 557 ahd_outb(ahd, port+3, (value >> 24) & 0xFF); 558 ahd_outb(ahd, port+4, (value >> 32) & 0xFF); 559 ahd_outb(ahd, port+5, (value >> 40) & 0xFF); 560 ahd_outb(ahd, port+6, (value >> 48) & 0xFF); 561 ahd_outb(ahd, port+7, (value >> 56) & 0xFF); 562 } 563 564 static __inline u_int 565 ahd_get_scbptr(struct ahd_softc *ahd) 566 { 567 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 568 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 569 return (ahd_inb(ahd, SCBPTR) | (ahd_inb(ahd, SCBPTR + 1) << 8)); 570 } 571 572 static __inline void 573 ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr) 574 { 575 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 576 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 577 ahd_outb(ahd, SCBPTR, scbptr & 0xFF); 578 ahd_outb(ahd, SCBPTR+1, (scbptr >> 8) & 0xFF); 579 } 580 581 static __inline u_int 582 ahd_get_hnscb_qoff(struct ahd_softc *ahd) 583 { 584 return (ahd_inw_atomic(ahd, HNSCB_QOFF)); 585 } 586 587 static __inline void 588 ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value) 589 { 590 ahd_outw_atomic(ahd, HNSCB_QOFF, value); 591 } 592 593 static __inline u_int 594 ahd_get_hescb_qoff(struct ahd_softc *ahd) 595 { 596 return (ahd_inb(ahd, HESCB_QOFF)); 597 } 598 599 static __inline void 600 ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value) 601 { 602 ahd_outb(ahd, HESCB_QOFF, value); 603 } 604 605 static __inline u_int 606 ahd_get_snscb_qoff(struct ahd_softc *ahd) 607 { 608 u_int oldvalue; 609 610 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 611 oldvalue = ahd_inw(ahd, SNSCB_QOFF); 612 ahd_outw(ahd, SNSCB_QOFF, oldvalue); 613 return (oldvalue); 614 } 615 616 static __inline void 617 ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value) 618 { 619 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 620 ahd_outw(ahd, SNSCB_QOFF, value); 621 } 622 623 static __inline u_int 624 ahd_get_sescb_qoff(struct ahd_softc *ahd) 625 { 626 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 627 return (ahd_inb(ahd, SESCB_QOFF)); 628 } 629 630 static __inline void 631 ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value) 632 { 633 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 634 ahd_outb(ahd, SESCB_QOFF, value); 635 } 636 637 static __inline u_int 638 ahd_get_sdscb_qoff(struct ahd_softc *ahd) 639 { 640 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 641 return (ahd_inb(ahd, SDSCB_QOFF) | (ahd_inb(ahd, SDSCB_QOFF + 1) << 8)); 642 } 643 644 static __inline void 645 ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value) 646 { 647 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 648 ahd_outb(ahd, SDSCB_QOFF, value & 0xFF); 649 ahd_outb(ahd, SDSCB_QOFF+1, (value >> 8) & 0xFF); 650 } 651 652 static __inline u_int 653 ahd_inb_scbram(struct ahd_softc *ahd, u_int offset) 654 { 655 u_int value; 656 657 /* 658 * Workaround PCI-X Rev A. hardware bug. 659 * After a host read of SCB memory, the chip 660 * may become confused into thinking prefetch 661 * was required. This starts the discard timer 662 * running and can cause an unexpected discard 663 * timer interrupt. The work around is to read 664 * a normal register prior to the exhaustion of 665 * the discard timer. The mode pointer register 666 * has no side effects and so serves well for 667 * this purpose. 668 * 669 * Razor #528 670 */ 671 value = ahd_inb(ahd, offset); 672 if ((ahd->flags & AHD_PCIX_SCBRAM_RD_BUG) != 0) 673 ahd_inb(ahd, MODE_PTR); 674 return (value); 675 } 676 677 static __inline u_int 678 ahd_inw_scbram(struct ahd_softc *ahd, u_int offset) 679 { 680 return (ahd_inb_scbram(ahd, offset) 681 | (ahd_inb_scbram(ahd, offset+1) << 8)); 682 } 683 684 static __inline uint32_t 685 ahd_inl_scbram(struct ahd_softc *ahd, u_int offset) 686 { 687 return (ahd_inb_scbram(ahd, offset) 688 | (ahd_inb_scbram(ahd, offset+1) << 8) 689 | (ahd_inb_scbram(ahd, offset+2) << 16) 690 | (ahd_inb_scbram(ahd, offset+3) << 24)); 691 } 692 693 static __inline struct scb * 694 ahd_lookup_scb(struct ahd_softc *ahd, u_int tag) 695 { 696 struct scb* scb; 697 698 if (tag >= AHD_SCB_MAX) 699 return (NULL); 700 scb = ahd->scb_data.scbindex[tag]; 701 if (scb != NULL) 702 ahd_sync_scb(ahd, scb, 703 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 704 return (scb); 705 } 706 707 static __inline void 708 ahd_swap_with_next_hscb(struct ahd_softc *ahd, struct scb *scb) 709 { 710 struct hardware_scb *q_hscb; 711 struct map_node *q_hscb_map; 712 uint32_t saved_hscb_busaddr; 713 714 /* 715 * Our queuing method is a bit tricky. The card 716 * knows in advance which HSCB (by address) to download, 717 * and we can't disappoint it. To achieve this, the next 718 * HSCB to download is saved off in ahd->next_queued_hscb. 719 * When we are called to queue "an arbitrary scb", 720 * we copy the contents of the incoming HSCB to the one 721 * the sequencer knows about, swap HSCB pointers and 722 * finally assign the SCB to the tag indexed location 723 * in the scb_array. This makes sure that we can still 724 * locate the correct SCB by SCB_TAG. 725 */ 726 q_hscb = ahd->next_queued_hscb; 727 q_hscb_map = ahd->next_queued_hscb_map; 728 saved_hscb_busaddr = q_hscb->hscb_busaddr; 729 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb)); 730 q_hscb->hscb_busaddr = saved_hscb_busaddr; 731 q_hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 732 733 /* Now swap HSCB pointers. */ 734 ahd->next_queued_hscb = scb->hscb; 735 ahd->next_queued_hscb_map = scb->hscb_map; 736 scb->hscb = q_hscb; 737 scb->hscb_map = q_hscb_map; 738 739 KASSERT((vaddr_t)scb->hscb >= (vaddr_t)scb->hscb_map->vaddr && 740 (vaddr_t)scb->hscb < (vaddr_t)scb->hscb_map->vaddr + PAGE_SIZE); 741 742 /* Now define the mapping from tag to SCB in the scbindex */ 743 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = scb; 744 } 745 746 /* 747 * Tell the sequencer about a new transaction to execute. 748 */ 749 static __inline void 750 ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb) 751 { 752 ahd_swap_with_next_hscb(ahd, scb); 753 754 if (SCBID_IS_NULL(SCB_GET_TAG(scb))) 755 panic("Attempt to queue invalid SCB tag %x\n", 756 SCB_GET_TAG(scb)); 757 758 /* 759 * Keep a history of SCBs we've downloaded in the qinfifo. 760 */ 761 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 762 ahd->qinfifonext++; 763 764 if (scb->sg_count != 0) 765 ahd_setup_data_scb(ahd, scb); 766 else 767 ahd_setup_noxfer_scb(ahd, scb); 768 ahd_setup_scb_common(ahd, scb); 769 770 /* 771 * Make sure our data is consistent from the 772 * perspective of the adapter. 773 */ 774 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 775 776 #ifdef AHD_DEBUG 777 if ((ahd_debug & AHD_SHOW_QUEUE) != 0) { 778 uint64_t host_dataptr; 779 780 host_dataptr = ahd_le64toh(scb->hscb->dataptr); 781 printf("%s: Queueing SCB 0x%x bus addr 0x%x - 0x%x%x/0x%x\n", 782 ahd_name(ahd), 783 SCB_GET_TAG(scb), ahd_le32toh(scb->hscb->hscb_busaddr), 784 (u_int)((host_dataptr >> 32) & 0xFFFFFFFF), 785 (u_int)(host_dataptr & 0xFFFFFFFF), 786 ahd_le32toh(scb->hscb->datacnt)); 787 } 788 #endif 789 /* Tell the adapter about the newly queued SCB */ 790 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 791 } 792 793 static __inline uint8_t * 794 ahd_get_sense_buf(struct ahd_softc *ahd, struct scb *scb) 795 { 796 return (scb->sense_data); 797 } 798 799 static __inline uint32_t 800 ahd_get_sense_bufaddr(struct ahd_softc *ahd, struct scb *scb) 801 { 802 return (scb->sense_busaddr); 803 } 804 805 /************************** Interrupt Processing ******************************/ 806 static __inline void ahd_sync_qoutfifo(struct ahd_softc *, int); 807 static __inline void ahd_sync_tqinfifo(struct ahd_softc *, int); 808 static __inline u_int ahd_check_cmdcmpltqueues(struct ahd_softc *); 809 static __inline int ahd_intr(void *); 810 static __inline void ahd_minphys(struct buf *); 811 812 static __inline void 813 ahd_sync_qoutfifo(struct ahd_softc *ahd, int op) 814 { 815 ahd_dmamap_sync(ahd, ahd->parent_dmat, ahd->shared_data_map.dmamap, 816 /*offset*/0, /*len*/AHD_SCB_MAX * sizeof(uint16_t), op); 817 } 818 819 static __inline void 820 ahd_sync_tqinfifo(struct ahd_softc *ahd, int op) 821 { 822 #ifdef AHD_TARGET_MODE 823 if ((ahd->flags & AHD_TARGETROLE) != 0) { 824 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, 825 ahd->shared_data_map.dmamap, 826 ahd_targetcmd_offset(ahd, 0), 827 sizeof(struct target_cmd) * AHD_TMODE_CMDS, 828 op); 829 } 830 #endif 831 } 832 833 /* 834 * See if the firmware has posted any completed commands 835 * into our in-core command complete fifos. 836 */ 837 #define AHD_RUN_QOUTFIFO 0x1 838 #define AHD_RUN_TQINFIFO 0x2 839 static __inline u_int 840 ahd_check_cmdcmpltqueues(struct ahd_softc *ahd) 841 { 842 u_int retval; 843 844 retval = 0; 845 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, ahd->shared_data_map.dmamap, 846 /*offset*/ahd->qoutfifonext, /*len*/2, 847 BUS_DMASYNC_POSTREAD); 848 if ((ahd->qoutfifo[ahd->qoutfifonext] 849 & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) 850 retval |= AHD_RUN_QOUTFIFO; 851 #ifdef AHD_TARGET_MODE 852 if ((ahd->flags & AHD_TARGETROLE) != 0 853 && (ahd->flags & AHD_TQINFIFO_BLOCKED) == 0) { 854 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, 855 ahd->shared_data_map.dmamap, 856 ahd_targetcmd_offset(ahd, ahd->tqinfifofnext), 857 /*len*/sizeof(struct target_cmd), 858 BUS_DMASYNC_POSTREAD); 859 if (ahd->targetcmds[ahd->tqinfifonext].cmd_valid != 0) 860 retval |= AHD_RUN_TQINFIFO; 861 } 862 #endif 863 return (retval); 864 } 865 866 /* 867 * Catch an interrupt from the adapter 868 */ 869 static __inline int 870 ahd_intr(void *arg) 871 { 872 struct ahd_softc *ahd = (struct ahd_softc*)arg; 873 u_int intstat; 874 875 if ((ahd->pause & INTEN) == 0) { 876 /* 877 * Our interrupt is not enabled on the chip 878 * and may be disabled for re-entrancy reasons, 879 * so just return. This is likely just a shared 880 * interrupt. 881 */ 882 return (0); 883 } 884 885 /* 886 * Instead of directly reading the interrupt status register, 887 * infer the cause of the interrupt by checking our in-core 888 * completion queues. This avoids a costly PCI bus read in 889 * most cases. 890 */ 891 if ((ahd->flags & AHD_ALL_INTERRUPTS) == 0 892 && (ahd_check_cmdcmpltqueues(ahd) != 0)) 893 intstat = CMDCMPLT; 894 else 895 intstat = ahd_inb(ahd, INTSTAT); 896 897 if ((intstat & INT_PEND) == 0) 898 return (0); 899 900 if (intstat & CMDCMPLT) { 901 ahd_outb(ahd, CLRINT, CLRCMDINT); 902 903 /* 904 * Ensure that the chip sees that we've cleared 905 * this interrupt before we walk the output fifo. 906 * Otherwise, we may, due to posted bus writes, 907 * clear the interrupt after we finish the scan, 908 * and after the sequencer has added new entries 909 * and asserted the interrupt again. 910 */ 911 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 912 if (ahd_is_paused(ahd)) { 913 /* 914 * Potentially lost SEQINT. 915 * If SEQINTCODE is non-zero, 916 * simulate the SEQINT. 917 */ 918 if (ahd_inb(ahd, SEQINTCODE) != NO_SEQINT) 919 intstat |= SEQINT; 920 } 921 } else { 922 ahd_flush_device_writes(ahd); 923 } 924 scsipi_channel_freeze(&ahd->sc_channel, 1); 925 ahd_run_qoutfifo(ahd); 926 scsipi_channel_thaw(&ahd->sc_channel, 1); 927 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]++; 928 ahd->cmdcmplt_total++; 929 #ifdef AHD_TARGET_MODE 930 if ((ahd->flags & AHD_TARGETROLE) != 0) 931 ahd_run_tqinfifo(ahd, /*paused*/FALSE); 932 #endif 933 if (intstat == CMDCMPLT) 934 return 1; 935 } 936 937 /* 938 * Handle statuses that may invalidate our cached 939 * copy of INTSTAT separately. 940 */ 941 if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0) { 942 /* Hot eject. Do nothing */ 943 } else if (intstat & HWERRINT) { 944 ahd_handle_hwerrint(ahd); 945 } else if ((intstat & (PCIINT|SPLTINT)) != 0) { 946 ahd->bus_intr(ahd); 947 } else { 948 949 if ((intstat & SEQINT) != 0) 950 ahd_handle_seqint(ahd, intstat); 951 952 if ((intstat & SCSIINT) != 0) 953 ahd_handle_scsiint(ahd, intstat); 954 } 955 956 return (1); 957 } 958 959 static __inline void 960 ahd_minphys(bp) 961 struct buf *bp; 962 { 963 /* 964 * Even though the card can transfer up to 16megs per command 965 * we are limited by the number of segments in the DMA segment 966 * list that we can hold. The worst case is that all pages are 967 * discontinuous physically, hense the "page per segment" limit 968 * enforced here. 969 */ 970 if (bp->b_bcount > AHD_MAXTRANSFER_SIZE) { 971 bp->b_bcount = AHD_MAXTRANSFER_SIZE; 972 } 973 minphys(bp); 974 } 975 976 static __inline u_int32_t scsi_4btoul(u_int8_t *); 977 978 static __inline u_int32_t 979 scsi_4btoul(u_int8_t *bytes) 980 { 981 u_int32_t rv; 982 983 rv = (bytes[0] << 24) | 984 (bytes[1] << 16) | 985 (bytes[2] << 8) | 986 bytes[3]; 987 return (rv); 988 } 989 990 991 #endif /* _AIC79XX_INLINE_H_ */ 992
Indexes created Fri Oct 17 09:09:57 GMT 2025