aic79xx_inline.h revision 1.7
1 /* $NetBSD: aic79xx_inline.h,v 1.7 2003/08/29 01:28:52 thorpej Exp $ */ 2 3 /* 4 * Inline routines shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2003 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * Id: //depot/aic7xxx/aic7xxx/aic79xx_inline.h#50 $ 43 * 44 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_inline.h,v 1.11 2003/05/26 21:26:52 gibbs Exp $ 45 */ 46 /* 47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 48 */ 49 50 #ifndef _AIC79XX_INLINE_H_ 51 #define _AIC79XX_INLINE_H_ 52 53 /******************************** Debugging ***********************************/ 54 static __inline char *ahd_name(struct ahd_softc *); 55 56 static __inline char * 57 ahd_name(struct ahd_softc *ahd) 58 { 59 return (ahd->name); 60 } 61 62 /************************ Sequencer Execution Control *************************/ 63 static __inline void ahd_known_modes(struct ahd_softc *, ahd_mode, ahd_mode); 64 static __inline ahd_mode_state ahd_build_mode_state(struct ahd_softc *, 65 ahd_mode, ahd_mode); 66 static __inline void ahd_extract_mode_state(struct ahd_softc *, 67 ahd_mode_state, ahd_mode *, ahd_mode *); 68 static __inline void ahd_set_modes(struct ahd_softc *, ahd_mode, ahd_mode); 69 static __inline void ahd_update_modes(struct ahd_softc *); 70 static __inline void ahd_assert_modes(struct ahd_softc *, ahd_mode, 71 ahd_mode, const char *, int); 72 static __inline ahd_mode_state ahd_save_modes(struct ahd_softc *); 73 static __inline void ahd_restore_modes(struct ahd_softc *, ahd_mode_state); 74 static __inline int ahd_is_paused(struct ahd_softc *); 75 static __inline void ahd_pause(struct ahd_softc *); 76 static __inline void ahd_unpause(struct ahd_softc *); 77 78 static __inline void 79 ahd_known_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst) 80 { 81 ahd->src_mode = src; 82 ahd->dst_mode = dst; 83 ahd->saved_src_mode = src; 84 ahd->saved_dst_mode = dst; 85 } 86 87 static __inline ahd_mode_state 88 ahd_build_mode_state(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst) 89 { 90 return ((src << SRC_MODE_SHIFT) | (dst << DST_MODE_SHIFT)); 91 } 92 93 static __inline void 94 ahd_extract_mode_state(struct ahd_softc *ahd, ahd_mode_state state, 95 ahd_mode *src, ahd_mode *dst) 96 { 97 *src = (state & SRC_MODE) >> SRC_MODE_SHIFT; 98 *dst = (state & DST_MODE) >> DST_MODE_SHIFT; 99 } 100 101 static __inline void 102 ahd_set_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst) 103 { 104 if (ahd->src_mode == src && ahd->dst_mode == dst) 105 return; 106 #ifdef AHD_DEBUG 107 if (ahd->src_mode == AHD_MODE_UNKNOWN 108 || ahd->dst_mode == AHD_MODE_UNKNOWN) 109 panic("Setting mode prior to saving it.\n"); 110 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0) 111 printf("%s: Setting mode 0x%x\n", ahd_name(ahd), 112 ahd_build_mode_state(ahd, src, dst)); 113 #endif 114 ahd_outb(ahd, MODE_PTR, ahd_build_mode_state(ahd, src, dst)); 115 ahd->src_mode = src; 116 ahd->dst_mode = dst; 117 } 118 119 static __inline void 120 ahd_update_modes(struct ahd_softc *ahd) 121 { 122 ahd_mode_state mode_ptr; 123 ahd_mode src; 124 ahd_mode dst; 125 126 mode_ptr = ahd_inb(ahd, MODE_PTR); 127 #ifdef AHD_DEBUG 128 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0) 129 printf("Reading mode 0x%x\n", mode_ptr); 130 #endif 131 ahd_extract_mode_state(ahd, mode_ptr, &src, &dst); 132 ahd_known_modes(ahd, src, dst); 133 } 134 135 static __inline void 136 ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode, 137 ahd_mode dstmode, const char *file, int line) 138 { 139 #ifdef AHD_DEBUG 140 if ((srcmode & AHD_MK_MSK(ahd->src_mode)) == 0 141 || (dstmode & AHD_MK_MSK(ahd->dst_mode)) == 0) { 142 panic("%s:%s:%d: Mode assertion failed.\n", 143 ahd_name(ahd), file, line); 144 } 145 #endif 146 } 147 148 static __inline ahd_mode_state 149 ahd_save_modes(struct ahd_softc *ahd) 150 { 151 if (ahd->src_mode == AHD_MODE_UNKNOWN 152 || ahd->dst_mode == AHD_MODE_UNKNOWN) 153 ahd_update_modes(ahd); 154 155 return (ahd_build_mode_state(ahd, ahd->src_mode, ahd->dst_mode)); 156 } 157 158 static __inline void 159 ahd_restore_modes(struct ahd_softc *ahd, ahd_mode_state state) 160 { 161 ahd_mode src; 162 ahd_mode dst; 163 164 ahd_extract_mode_state(ahd, state, &src, &dst); 165 ahd_set_modes(ahd, src, dst); 166 } 167 168 #define AHD_ASSERT_MODES(ahd, source, dest) \ 169 ahd_assert_modes(ahd, source, dest, __FILE__, __LINE__); 170 171 /* 172 * Determine whether the sequencer has halted code execution. 173 * Returns non-zero status if the sequencer is stopped. 174 */ 175 static __inline int 176 ahd_is_paused(struct ahd_softc *ahd) 177 { 178 return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0); 179 } 180 181 /* 182 * Request that the sequencer stop and wait, indefinitely, for it 183 * to stop. The sequencer will only acknowledge that it is paused 184 * once it has reached an instruction boundary and PAUSEDIS is 185 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS 186 * for critical sections. 187 */ 188 static __inline void 189 ahd_pause(struct ahd_softc *ahd) 190 { 191 ahd_outb(ahd, HCNTRL, ahd->pause); 192 193 /* 194 * Since the sequencer can disable pausing in a critical section, we 195 * must loop until it actually stops. 196 */ 197 while (ahd_is_paused(ahd) == 0) 198 ; 199 } 200 201 /* 202 * Allow the sequencer to continue program execution. 203 * We check here to ensure that no additional interrupt 204 * sources that would cause the sequencer to halt have been 205 * asserted. If, for example, a SCSI bus reset is detected 206 * while we are fielding a different, pausing, interrupt type, 207 * we don't want to release the sequencer before going back 208 * into our interrupt handler and dealing with this new 209 * condition. 210 */ 211 static __inline void 212 ahd_unpause(struct ahd_softc *ahd) 213 { 214 /* 215 * Automatically restore our modes to those saved 216 * prior to the first change of the mode. 217 */ 218 if (ahd->saved_src_mode != AHD_MODE_UNKNOWN 219 && ahd->saved_dst_mode != AHD_MODE_UNKNOWN) { 220 if ((ahd->flags & AHD_UPDATE_PEND_CMDS) != 0) 221 ahd_reset_cmds_pending(ahd); 222 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 223 } 224 225 if ((ahd_inb(ahd, INTSTAT) & ~CMDCMPLT) == 0) 226 ahd_outb(ahd, HCNTRL, ahd->unpause); 227 228 ahd_known_modes(ahd, AHD_MODE_UNKNOWN, AHD_MODE_UNKNOWN); 229 } 230 231 /*********************** Scatter Gather List Handling *************************/ 232 static __inline void *ahd_sg_setup(struct ahd_softc *, struct scb *, 233 void *, bus_addr_t, bus_size_t, int); 234 static __inline void ahd_setup_scb_common(struct ahd_softc *, struct scb *); 235 static __inline void ahd_setup_data_scb(struct ahd_softc *, struct scb *); 236 static __inline void ahd_setup_noxfer_scb(struct ahd_softc *, struct scb *); 237 238 static __inline void * 239 ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb, 240 void *sgptr, bus_addr_t addr, bus_size_t len, int last) 241 { 242 scb->sg_count++; 243 if (sizeof(bus_addr_t) > 4 244 && (ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 245 struct ahd_dma64_seg *sg; 246 247 sg = (struct ahd_dma64_seg *)sgptr; 248 sg->addr = ahd_htole64(addr); 249 sg->len = ahd_htole32(len | (last ? AHD_DMA_LAST_SEG : 0)); 250 return (sg + 1); 251 } else { 252 struct ahd_dma_seg *sg; 253 254 sg = (struct ahd_dma_seg *)sgptr; 255 sg->addr = ahd_htole32(addr & 0xFFFFFFFF); 256 sg->len = ahd_htole32(len | ((addr >> 8) & 0x7F000000) 257 | (last ? AHD_DMA_LAST_SEG : 0)); 258 return (sg + 1); 259 } 260 } 261 262 static __inline void 263 ahd_setup_scb_common(struct ahd_softc *ahd, struct scb *scb) 264 { 265 /* XXX Handle target mode SCBs. */ 266 scb->crc_retry_count = 0; 267 if ((scb->flags & SCB_PACKETIZED) != 0) { 268 /* XXX what about ACA?? It is type 4, but TAG_TYPE == 0x3. */ 269 scb->hscb->task_attribute = scb->hscb->control & SCB_TAG_TYPE; 270 } else { 271 if (ahd_get_transfer_length(scb) & 0x01) 272 scb->hscb->task_attribute = SCB_XFERLEN_ODD; 273 else 274 scb->hscb->task_attribute = 0; 275 } 276 277 if (scb->hscb->cdb_len <= MAX_CDB_LEN_WITH_SENSE_ADDR 278 || (scb->hscb->cdb_len & SCB_CDB_LEN_PTR) != 0) 279 scb->hscb->shared_data.idata.cdb_plus_saddr.sense_addr = 280 ahd_htole32(scb->sense_busaddr); 281 } 282 283 static __inline void 284 ahd_setup_data_scb(struct ahd_softc *ahd, struct scb *scb) 285 { 286 /* 287 * Copy the first SG into the "current" data ponter area. 288 */ 289 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 290 struct ahd_dma64_seg *sg; 291 292 sg = (struct ahd_dma64_seg *)scb->sg_list; 293 scb->hscb->dataptr = sg->addr; 294 scb->hscb->datacnt = sg->len; 295 } else { 296 struct ahd_dma_seg *sg; 297 uint32_t *dataptr_words; 298 299 sg = (struct ahd_dma_seg *)scb->sg_list; 300 dataptr_words = (uint32_t*)&scb->hscb->dataptr; 301 dataptr_words[0] = sg->addr; 302 dataptr_words[1] = 0; 303 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) { 304 uint64_t high_addr; 305 306 high_addr = ahd_le32toh(sg->len) & 0x7F000000; 307 scb->hscb->dataptr |= ahd_htole64(high_addr << 8); 308 } 309 scb->hscb->datacnt = sg->len; 310 } 311 /* 312 * Note where to find the SG entries in bus space. 313 * We also set the full residual flag which the 314 * sequencer will clear as soon as a data transfer 315 * occurs. 316 */ 317 scb->hscb->sgptr = ahd_htole32(scb->sg_list_busaddr|SG_FULL_RESID); 318 } 319 320 static __inline void 321 ahd_setup_noxfer_scb(struct ahd_softc *ahd, struct scb *scb) 322 { 323 scb->hscb->sgptr = ahd_htole32(SG_LIST_NULL); 324 scb->hscb->dataptr = 0; 325 scb->hscb->datacnt = 0; 326 } 327 328 /************************** Memory mapping routines ***************************/ 329 static __inline size_t ahd_sg_size(struct ahd_softc *); 330 static __inline void * 331 ahd_sg_bus_to_virt(struct ahd_softc *, struct scb *, 332 uint32_t); 333 static __inline uint32_t 334 ahd_sg_virt_to_bus(struct ahd_softc *, struct scb *, 335 void *); 336 static __inline void ahd_sync_scb(struct ahd_softc *, struct scb *, int); 337 static __inline void ahd_sync_sglist(struct ahd_softc *, struct scb *, int); 338 static __inline void ahd_sync_sense(struct ahd_softc *, struct scb *, int); 339 static __inline uint32_t 340 ahd_targetcmd_offset(struct ahd_softc *, u_int); 341 342 static __inline size_t 343 ahd_sg_size(struct ahd_softc *ahd) 344 { 345 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 346 return (sizeof(struct ahd_dma64_seg)); 347 return (sizeof(struct ahd_dma_seg)); 348 } 349 350 static __inline void * 351 ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr) 352 { 353 bus_addr_t sg_offset; 354 355 /* sg_list_phys points to entry 1, not 0 */ 356 sg_offset = sg_busaddr - (scb->sg_list_busaddr - ahd_sg_size(ahd)); 357 return ((uint8_t *)scb->sg_list + sg_offset); 358 } 359 360 static __inline uint32_t 361 ahd_sg_virt_to_bus(struct ahd_softc *ahd, struct scb *scb, void *sg) 362 { 363 bus_addr_t sg_offset; 364 365 /* sg_list_phys points to entry 1, not 0 */ 366 sg_offset = ((uint8_t *)sg - (uint8_t *)scb->sg_list) 367 - ahd_sg_size(ahd); 368 369 return (scb->sg_list_busaddr + sg_offset); 370 } 371 372 static __inline void 373 ahd_sync_scb(struct ahd_softc *ahd, struct scb *scb, int op) 374 { 375 ahd_dmamap_sync(ahd, ahd->parent_dmat, scb->hscb_map->dmamap, 376 /*offset*/(uint8_t*)scb->hscb - scb->hscb_map->vaddr, 377 /*len*/sizeof(*scb->hscb), op); 378 } 379 380 static __inline void 381 ahd_sync_sglist(struct ahd_softc *ahd, struct scb *scb, int op) 382 { 383 if (scb->sg_count == 0) 384 return; 385 386 ahd_dmamap_sync(ahd, ahd->parent_dmat, scb->sg_map->dmamap, 387 /*offset*/scb->sg_list_busaddr - ahd_sg_size(ahd), 388 /*len*/ahd_sg_size(ahd) * scb->sg_count, op); 389 } 390 391 static __inline void 392 ahd_sync_sense(struct ahd_softc *ahd, struct scb *scb, int op) 393 { 394 ahd_dmamap_sync(ahd, ahd->parent_dmat, 395 scb->sense_map->dmamap, 396 /*offset*/scb->sense_busaddr, 397 /*len*/AHD_SENSE_BUFSIZE, op); 398 } 399 400 static __inline uint32_t 401 ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index) 402 { 403 return (((uint8_t *)&ahd->targetcmds[index]) 404 - (uint8_t *)ahd->qoutfifo); 405 } 406 407 /*********************** Miscelaneous Support Functions ***********************/ 408 static __inline void ahd_complete_scb(struct ahd_softc *, struct scb *); 409 static __inline void ahd_update_residual(struct ahd_softc *, struct scb *); 410 static __inline struct ahd_initiator_tinfo * 411 ahd_fetch_transinfo(struct ahd_softc *, char, u_int, 412 u_int, struct ahd_tmode_tstate **); 413 static __inline uint16_t 414 ahd_inw(struct ahd_softc *, u_int); 415 static __inline void ahd_outw(struct ahd_softc *, u_int, u_int); 416 static __inline uint32_t 417 ahd_inl(struct ahd_softc *, u_int); 418 static __inline void ahd_outl(struct ahd_softc *, u_int, uint32_t); 419 static __inline uint64_t 420 ahd_inq(struct ahd_softc *, u_int); 421 static __inline void ahd_outq(struct ahd_softc *, u_int, uint64_t); 422 static __inline u_int ahd_get_scbptr(struct ahd_softc *); 423 static __inline void ahd_set_scbptr(struct ahd_softc *, u_int); 424 static __inline u_int ahd_get_hnscb_qoff(struct ahd_softc *); 425 static __inline void ahd_set_hnscb_qoff(struct ahd_softc *, u_int); 426 static __inline u_int ahd_get_hescb_qoff(struct ahd_softc *); 427 static __inline void ahd_set_hescb_qoff(struct ahd_softc *, u_int); 428 static __inline u_int ahd_get_snscb_qoff(struct ahd_softc *); 429 static __inline void ahd_set_snscb_qoff(struct ahd_softc *, u_int); 430 static __inline u_int ahd_get_sescb_qoff(struct ahd_softc *); 431 static __inline void ahd_set_sescb_qoff(struct ahd_softc *, u_int); 432 static __inline u_int ahd_get_sdscb_qoff(struct ahd_softc *); 433 static __inline void ahd_set_sdscb_qoff(struct ahd_softc *, u_int); 434 static __inline u_int ahd_inb_scbram(struct ahd_softc *, u_int); 435 static __inline u_int ahd_inw_scbram(struct ahd_softc *, u_int); 436 static __inline uint32_t 437 ahd_inl_scbram(struct ahd_softc *, u_int); 438 static __inline void ahd_swap_with_next_hscb(struct ahd_softc *, 439 struct scb *); 440 static __inline void ahd_queue_scb(struct ahd_softc *, struct scb *); 441 static __inline uint8_t * 442 ahd_get_sense_buf(struct ahd_softc *, struct scb *); 443 static __inline uint32_t 444 ahd_get_sense_bufaddr(struct ahd_softc *, struct scb *); 445 static __inline void ahd_post_scb(struct ahd_softc *, struct scb *); 446 447 448 static __inline void 449 ahd_post_scb(struct ahd_softc *ahd, struct scb *scb) 450 { 451 uint32_t sgptr; 452 453 sgptr = ahd_le32toh(scb->hscb->sgptr); 454 if ((sgptr & SG_STATUS_VALID) != 0) 455 ahd_handle_scb_status(ahd, scb); 456 else 457 ahd_done(ahd, scb); 458 } 459 460 static __inline void 461 ahd_complete_scb(struct ahd_softc *ahd, struct scb *scb) 462 { 463 uint32_t sgptr; 464 465 sgptr = ahd_le32toh(scb->hscb->sgptr); 466 if ((sgptr & SG_STATUS_VALID) != 0) 467 ahd_handle_scb_status(ahd, scb); 468 else 469 ahd_done(ahd, scb); 470 } 471 472 /* 473 * Determine whether the sequencer reported a residual 474 * for this SCB/transaction. 475 */ 476 static __inline void 477 ahd_update_residual(struct ahd_softc *ahd, struct scb *scb) 478 { 479 uint32_t sgptr; 480 481 sgptr = ahd_le32toh(scb->hscb->sgptr); 482 if ((sgptr & SG_STATUS_VALID) != 0) 483 ahd_calc_residual(ahd, scb); 484 } 485 486 /* 487 * Return pointers to the transfer negotiation information 488 * for the specified our_id/remote_id pair. 489 */ 490 static __inline struct ahd_initiator_tinfo * 491 ahd_fetch_transinfo(struct ahd_softc *ahd, char channel, u_int our_id, 492 u_int remote_id, struct ahd_tmode_tstate **tstate) 493 { 494 /* 495 * Transfer data structures are stored from the perspective 496 * of the target role. Since the parameters for a connection 497 * in the initiator role to a given target are the same as 498 * when the roles are reversed, we pretend we are the target. 499 */ 500 if (channel == 'B') 501 our_id += 8; 502 *tstate = ahd->enabled_targets[our_id]; 503 return (&(*tstate)->transinfo[remote_id]); 504 } 505 506 #define AHD_COPY_COL_IDX(dst, src) \ 507 do { \ 508 dst->hscb->scsiid = src->hscb->scsiid; \ 509 dst->hscb->lun = src->hscb->lun; \ 510 } while (0) 511 512 static __inline uint16_t 513 ahd_inw(struct ahd_softc *ahd, u_int port) 514 { 515 return ((ahd_inb(ahd, port+1) << 8) | ahd_inb(ahd, port)); 516 } 517 518 static __inline void 519 ahd_outw(struct ahd_softc *ahd, u_int port, u_int value) 520 { 521 ahd_outb(ahd, port, value & 0xFF); 522 ahd_outb(ahd, port+1, (value >> 8) & 0xFF); 523 } 524 525 static __inline uint32_t 526 ahd_inl(struct ahd_softc *ahd, u_int port) 527 { 528 return ((ahd_inb(ahd, port)) 529 | (ahd_inb(ahd, port+1) << 8) 530 | (ahd_inb(ahd, port+2) << 16) 531 | (ahd_inb(ahd, port+3) << 24)); 532 } 533 534 static __inline void 535 ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value) 536 { 537 ahd_outb(ahd, port, (value) & 0xFF); 538 ahd_outb(ahd, port+1, ((value) >> 8) & 0xFF); 539 ahd_outb(ahd, port+2, ((value) >> 16) & 0xFF); 540 ahd_outb(ahd, port+3, ((value) >> 24) & 0xFF); 541 } 542 543 static __inline uint64_t 544 ahd_inq(struct ahd_softc *ahd, u_int port) 545 { 546 return ((ahd_inb(ahd, port)) 547 | (ahd_inb(ahd, port+1) << 8) 548 | (ahd_inb(ahd, port+2) << 16) 549 | (ahd_inb(ahd, port+3) << 24) 550 | (((uint64_t)ahd_inb(ahd, port+4)) << 32) 551 | (((uint64_t)ahd_inb(ahd, port+5)) << 40) 552 | (((uint64_t)ahd_inb(ahd, port+6)) << 48) 553 | (((uint64_t)ahd_inb(ahd, port+7)) << 56)); 554 } 555 556 static __inline void 557 ahd_outq(struct ahd_softc *ahd, u_int port, uint64_t value) 558 { 559 ahd_outb(ahd, port, value & 0xFF); 560 ahd_outb(ahd, port+1, (value >> 8) & 0xFF); 561 ahd_outb(ahd, port+2, (value >> 16) & 0xFF); 562 ahd_outb(ahd, port+3, (value >> 24) & 0xFF); 563 ahd_outb(ahd, port+4, (value >> 32) & 0xFF); 564 ahd_outb(ahd, port+5, (value >> 40) & 0xFF); 565 ahd_outb(ahd, port+6, (value >> 48) & 0xFF); 566 ahd_outb(ahd, port+7, (value >> 56) & 0xFF); 567 } 568 569 static __inline u_int 570 ahd_get_scbptr(struct ahd_softc *ahd) 571 { 572 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 573 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 574 return (ahd_inb(ahd, SCBPTR) | (ahd_inb(ahd, SCBPTR + 1) << 8)); 575 } 576 577 static __inline void 578 ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr) 579 { 580 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 581 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 582 ahd_outb(ahd, SCBPTR, scbptr & 0xFF); 583 ahd_outb(ahd, SCBPTR+1, (scbptr >> 8) & 0xFF); 584 } 585 586 static __inline u_int 587 ahd_get_hnscb_qoff(struct ahd_softc *ahd) 588 { 589 return (ahd_inw_atomic(ahd, HNSCB_QOFF)); 590 } 591 592 static __inline void 593 ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value) 594 { 595 ahd_outw_atomic(ahd, HNSCB_QOFF, value); 596 } 597 598 static __inline u_int 599 ahd_get_hescb_qoff(struct ahd_softc *ahd) 600 { 601 return (ahd_inb(ahd, HESCB_QOFF)); 602 } 603 604 static __inline void 605 ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value) 606 { 607 ahd_outb(ahd, HESCB_QOFF, value); 608 } 609 610 static __inline u_int 611 ahd_get_snscb_qoff(struct ahd_softc *ahd) 612 { 613 u_int oldvalue; 614 615 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 616 oldvalue = ahd_inw(ahd, SNSCB_QOFF); 617 ahd_outw(ahd, SNSCB_QOFF, oldvalue); 618 return (oldvalue); 619 } 620 621 static __inline void 622 ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value) 623 { 624 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 625 ahd_outw(ahd, SNSCB_QOFF, value); 626 } 627 628 static __inline u_int 629 ahd_get_sescb_qoff(struct ahd_softc *ahd) 630 { 631 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 632 return (ahd_inb(ahd, SESCB_QOFF)); 633 } 634 635 static __inline void 636 ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value) 637 { 638 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 639 ahd_outb(ahd, SESCB_QOFF, value); 640 } 641 642 static __inline u_int 643 ahd_get_sdscb_qoff(struct ahd_softc *ahd) 644 { 645 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 646 return (ahd_inb(ahd, SDSCB_QOFF) | (ahd_inb(ahd, SDSCB_QOFF + 1) << 8)); 647 } 648 649 static __inline void 650 ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value) 651 { 652 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 653 ahd_outb(ahd, SDSCB_QOFF, value & 0xFF); 654 ahd_outb(ahd, SDSCB_QOFF+1, (value >> 8) & 0xFF); 655 } 656 657 static __inline u_int 658 ahd_inb_scbram(struct ahd_softc *ahd, u_int offset) 659 { 660 u_int value; 661 662 /* 663 * Workaround PCI-X Rev A. hardware bug. 664 * After a host read of SCB memory, the chip 665 * may become confused into thinking prefetch 666 * was required. This starts the discard timer 667 * running and can cause an unexpected discard 668 * timer interrupt. The work around is to read 669 * a normal register prior to the exhaustion of 670 * the discard timer. The mode pointer register 671 * has no side effects and so serves well for 672 * this purpose. 673 * 674 * Razor #528 675 */ 676 value = ahd_inb(ahd, offset); 677 if ((ahd->flags & AHD_PCIX_SCBRAM_RD_BUG) != 0) 678 ahd_inb(ahd, MODE_PTR); 679 return (value); 680 } 681 682 static __inline u_int 683 ahd_inw_scbram(struct ahd_softc *ahd, u_int offset) 684 { 685 return (ahd_inb_scbram(ahd, offset) 686 | (ahd_inb_scbram(ahd, offset+1) << 8)); 687 } 688 689 static __inline uint32_t 690 ahd_inl_scbram(struct ahd_softc *ahd, u_int offset) 691 { 692 return (ahd_inb_scbram(ahd, offset) 693 | (ahd_inb_scbram(ahd, offset+1) << 8) 694 | (ahd_inb_scbram(ahd, offset+2) << 16) 695 | (ahd_inb_scbram(ahd, offset+3) << 24)); 696 } 697 698 static __inline struct scb * 699 ahd_lookup_scb(struct ahd_softc *ahd, u_int tag) 700 { 701 struct scb* scb; 702 703 if (tag >= AHD_SCB_MAX) 704 return (NULL); 705 scb = ahd->scb_data.scbindex[tag]; 706 if (scb != NULL) 707 ahd_sync_scb(ahd, scb, 708 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 709 return (scb); 710 } 711 712 static __inline void 713 ahd_swap_with_next_hscb(struct ahd_softc *ahd, struct scb *scb) 714 { 715 struct hardware_scb *q_hscb; 716 struct map_node *q_hscb_map; 717 uint32_t saved_hscb_busaddr; 718 719 /* 720 * Our queuing method is a bit tricky. The card 721 * knows in advance which HSCB (by address) to download, 722 * and we can't disappoint it. To achieve this, the next 723 * HSCB to download is saved off in ahd->next_queued_hscb. 724 * When we are called to queue "an arbitrary scb", 725 * we copy the contents of the incoming HSCB to the one 726 * the sequencer knows about, swap HSCB pointers and 727 * finally assign the SCB to the tag indexed location 728 * in the scb_array. This makes sure that we can still 729 * locate the correct SCB by SCB_TAG. 730 */ 731 q_hscb = ahd->next_queued_hscb; 732 q_hscb_map = ahd->next_queued_hscb_map; 733 saved_hscb_busaddr = q_hscb->hscb_busaddr; 734 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb)); 735 q_hscb->hscb_busaddr = saved_hscb_busaddr; 736 q_hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 737 738 /* Now swap HSCB pointers. */ 739 ahd->next_queued_hscb = scb->hscb; 740 ahd->next_queued_hscb_map = scb->hscb_map; 741 scb->hscb = q_hscb; 742 scb->hscb_map = q_hscb_map; 743 744 KASSERT((vaddr_t)scb->hscb >= (vaddr_t)scb->hscb_map->vaddr && 745 (vaddr_t)scb->hscb < (vaddr_t)scb->hscb_map->vaddr + PAGE_SIZE); 746 747 /* Now define the mapping from tag to SCB in the scbindex */ 748 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = scb; 749 } 750 751 /* 752 * Tell the sequencer about a new transaction to execute. 753 */ 754 static __inline void 755 ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb) 756 { 757 ahd_swap_with_next_hscb(ahd, scb); 758 759 if (SCBID_IS_NULL(SCB_GET_TAG(scb))) 760 panic("Attempt to queue invalid SCB tag %x\n", 761 SCB_GET_TAG(scb)); 762 763 /* 764 * Keep a history of SCBs we've downloaded in the qinfifo. 765 */ 766 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 767 ahd->qinfifonext++; 768 769 if (scb->sg_count != 0) 770 ahd_setup_data_scb(ahd, scb); 771 else 772 ahd_setup_noxfer_scb(ahd, scb); 773 ahd_setup_scb_common(ahd, scb); 774 775 /* 776 * Make sure our data is consistent from the 777 * perspective of the adapter. 778 */ 779 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 780 781 #ifdef AHD_DEBUG 782 if ((ahd_debug & AHD_SHOW_QUEUE) != 0) { 783 uint64_t host_dataptr; 784 785 host_dataptr = ahd_le64toh(scb->hscb->dataptr); 786 printf("%s: Queueing SCB 0x%x bus addr 0x%x - 0x%x%x/0x%x\n", 787 ahd_name(ahd), 788 SCB_GET_TAG(scb), ahd_le32toh(scb->hscb->hscb_busaddr), 789 (u_int)((host_dataptr >> 32) & 0xFFFFFFFF), 790 (u_int)(host_dataptr & 0xFFFFFFFF), 791 ahd_le32toh(scb->hscb->datacnt)); 792 } 793 #endif 794 /* Tell the adapter about the newly queued SCB */ 795 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 796 } 797 798 static __inline uint8_t * 799 ahd_get_sense_buf(struct ahd_softc *ahd, struct scb *scb) 800 { 801 return (scb->sense_data); 802 } 803 804 static __inline uint32_t 805 ahd_get_sense_bufaddr(struct ahd_softc *ahd, struct scb *scb) 806 { 807 return (scb->sense_busaddr); 808 } 809 810 /************************** Interrupt Processing ******************************/ 811 static __inline void ahd_sync_qoutfifo(struct ahd_softc *, int); 812 static __inline void ahd_sync_tqinfifo(struct ahd_softc *, int); 813 static __inline u_int ahd_check_cmdcmpltqueues(struct ahd_softc *); 814 static __inline int ahd_intr(void *); 815 static __inline void ahd_minphys(struct buf *); 816 817 static __inline void 818 ahd_sync_qoutfifo(struct ahd_softc *ahd, int op) 819 { 820 ahd_dmamap_sync(ahd, ahd->parent_dmat, ahd->shared_data_map.dmamap, 821 /*offset*/0, /*len*/AHD_SCB_MAX * sizeof(uint16_t), op); 822 } 823 824 static __inline void 825 ahd_sync_tqinfifo(struct ahd_softc *ahd, int op) 826 { 827 #ifdef AHD_TARGET_MODE 828 if ((ahd->flags & AHD_TARGETROLE) != 0) { 829 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, 830 ahd->shared_data_map.dmamap, 831 ahd_targetcmd_offset(ahd, 0), 832 sizeof(struct target_cmd) * AHD_TMODE_CMDS, 833 op); 834 } 835 #endif 836 } 837 838 /* 839 * See if the firmware has posted any completed commands 840 * into our in-core command complete fifos. 841 */ 842 #define AHD_RUN_QOUTFIFO 0x1 843 #define AHD_RUN_TQINFIFO 0x2 844 static __inline u_int 845 ahd_check_cmdcmpltqueues(struct ahd_softc *ahd) 846 { 847 u_int retval; 848 849 retval = 0; 850 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, ahd->shared_data_map.dmamap, 851 /*offset*/ahd->qoutfifonext, /*len*/2, 852 BUS_DMASYNC_POSTREAD); 853 if ((ahd->qoutfifo[ahd->qoutfifonext] 854 & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) 855 retval |= AHD_RUN_QOUTFIFO; 856 #ifdef AHD_TARGET_MODE 857 if ((ahd->flags & AHD_TARGETROLE) != 0 858 && (ahd->flags & AHD_TQINFIFO_BLOCKED) == 0) { 859 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, 860 ahd->shared_data_map.dmamap, 861 ahd_targetcmd_offset(ahd, ahd->tqinfifofnext), 862 /*len*/sizeof(struct target_cmd), 863 BUS_DMASYNC_POSTREAD); 864 if (ahd->targetcmds[ahd->tqinfifonext].cmd_valid != 0) 865 retval |= AHD_RUN_TQINFIFO; 866 } 867 #endif 868 return (retval); 869 } 870 871 /* 872 * Catch an interrupt from the adapter 873 */ 874 static __inline int 875 ahd_intr(void *arg) 876 { 877 struct ahd_softc *ahd = (struct ahd_softc*)arg; 878 u_int intstat; 879 880 if ((ahd->pause & INTEN) == 0) { 881 /* 882 * Our interrupt is not enabled on the chip 883 * and may be disabled for re-entrancy reasons, 884 * so just return. This is likely just a shared 885 * interrupt. 886 */ 887 return (0); 888 } 889 890 /* 891 * Instead of directly reading the interrupt status register, 892 * infer the cause of the interrupt by checking our in-core 893 * completion queues. This avoids a costly PCI bus read in 894 * most cases. 895 */ 896 if ((ahd->flags & AHD_ALL_INTERRUPTS) == 0 897 && (ahd_check_cmdcmpltqueues(ahd) != 0)) 898 intstat = CMDCMPLT; 899 else 900 intstat = ahd_inb(ahd, INTSTAT); 901 902 if ((intstat & INT_PEND) == 0) 903 return (0); 904 905 if (intstat & CMDCMPLT) { 906 ahd_outb(ahd, CLRINT, CLRCMDINT); 907 908 /* 909 * Ensure that the chip sees that we've cleared 910 * this interrupt before we walk the output fifo. 911 * Otherwise, we may, due to posted bus writes, 912 * clear the interrupt after we finish the scan, 913 * and after the sequencer has added new entries 914 * and asserted the interrupt again. 915 */ 916 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 917 if (ahd_is_paused(ahd)) { 918 /* 919 * Potentially lost SEQINT. 920 * If SEQINTCODE is non-zero, 921 * simulate the SEQINT. 922 */ 923 if (ahd_inb(ahd, SEQINTCODE) != NO_SEQINT) 924 intstat |= SEQINT; 925 } 926 } else { 927 ahd_flush_device_writes(ahd); 928 } 929 scsipi_channel_freeze(&ahd->sc_channel, 1); 930 ahd_run_qoutfifo(ahd); 931 scsipi_channel_thaw(&ahd->sc_channel, 1); 932 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]++; 933 ahd->cmdcmplt_total++; 934 #ifdef AHD_TARGET_MODE 935 if ((ahd->flags & AHD_TARGETROLE) != 0) 936 ahd_run_tqinfifo(ahd, /*paused*/FALSE); 937 #endif 938 if (intstat == CMDCMPLT) 939 return 1; 940 } 941 942 /* 943 * Handle statuses that may invalidate our cached 944 * copy of INTSTAT separately. 945 */ 946 if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0) { 947 /* Hot eject. Do nothing */ 948 } else if (intstat & HWERRINT) { 949 ahd_handle_hwerrint(ahd); 950 } else if ((intstat & (PCIINT|SPLTINT)) != 0) { 951 ahd->bus_intr(ahd); 952 } else { 953 954 if ((intstat & SEQINT) != 0) 955 ahd_handle_seqint(ahd, intstat); 956 957 if ((intstat & SCSIINT) != 0) 958 ahd_handle_scsiint(ahd, intstat); 959 } 960 961 return (1); 962 } 963 964 static __inline void 965 ahd_minphys(bp) 966 struct buf *bp; 967 { 968 /* 969 * Even though the card can transfer up to 16megs per command 970 * we are limited by the number of segments in the DMA segment 971 * list that we can hold. The worst case is that all pages are 972 * discontinuous physically, hense the "page per segment" limit 973 * enforced here. 974 */ 975 if (bp->b_bcount > AHD_MAXTRANSFER_SIZE) { 976 bp->b_bcount = AHD_MAXTRANSFER_SIZE; 977 } 978 minphys(bp); 979 } 980 981 static __inline u_int32_t scsi_4btoul(u_int8_t *); 982 983 static __inline u_int32_t 984 scsi_4btoul(u_int8_t *bytes) 985 { 986 u_int32_t rv; 987 988 rv = (bytes[0] << 24) | 989 (bytes[1] << 16) | 990 (bytes[2] << 8) | 991 bytes[3]; 992 return (rv); 993 } 994 995 996 #endif /* _AIC79XX_INLINE_H_ */ 997
Indexes created Mon Sep 29 03:10:08 GMT 2025