arn9003.c revision 1.1
1 /* $NetBSD: arn9003.c,v 1.1 2013/03/30 02:53:01 christos Exp $ */ 2 /* $OpenBSD: ar9003.c,v 1.25 2012/10/20 09:53:32 stsp Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 * Routines for AR9003 family. 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: arn9003.c,v 1.1 2013/03/30 02:53:01 christos Exp $"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/queue.h> 37 #include <sys/callout.h> 38 #include <sys/conf.h> 39 #include <sys/device.h> 40 41 #include <sys/bus.h> 42 #include <sys/endian.h> 43 #include <sys/intr.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/ip.h> 56 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_amrr.h> 59 #include <net80211/ieee80211_radiotap.h> 60 61 #include <dev/ic/athnreg.h> 62 #include <dev/ic/athnvar.h> 63 #include <dev/ic/arn9003reg.h> 64 #include <dev/ic/arn9003.h> 65 66 #define Static static 67 68 Static void ar9003_calib_iq(struct athn_softc *); 69 Static int ar9003_calib_tx_iq(struct athn_softc *); 70 Static int ar9003_compute_predistortion(struct athn_softc *, 71 const uint32_t *, const uint32_t *); 72 Static void ar9003_disable_ofdm_weak_signal(struct athn_softc *); 73 Static void ar9003_disable_phy(struct athn_softc *); 74 Static int ar9003_dma_alloc(struct athn_softc *); 75 Static void ar9003_dma_free(struct athn_softc *); 76 Static void ar9003_do_calib(struct athn_softc *); 77 Static void ar9003_do_noisefloor_calib(struct athn_softc *); 78 Static void ar9003_enable_antenna_diversity(struct athn_softc *); 79 Static void ar9003_enable_ofdm_weak_signal(struct athn_softc *); 80 Static void ar9003_enable_predistorter(struct athn_softc *, int); 81 Static int ar9003_find_rom(struct athn_softc *); 82 Static void ar9003_force_txgain(struct athn_softc *, uint32_t); 83 Static int ar9003_get_desired_txgain(struct athn_softc *, int, int); 84 Static int ar9003_get_iq_corr(struct athn_softc *, int32_t[], int32_t[]); 85 Static void ar9003_gpio_config_input(struct athn_softc *, int); 86 Static void ar9003_gpio_config_output(struct athn_softc *, int, int); 87 Static int ar9003_gpio_read(struct athn_softc *, int); 88 Static void ar9003_gpio_write(struct athn_softc *, int, int); 89 Static void ar9003_hw_init(struct athn_softc *, struct ieee80211_channel *, 90 struct ieee80211_channel *); 91 Static void ar9003_init_baseband(struct athn_softc *); 92 Static void ar9003_init_chains(struct athn_softc *); 93 Static int ar9003_intr(struct athn_softc *); 94 Static void ar9003_next_calib(struct athn_softc *); 95 Static void ar9003_paprd_enable(struct athn_softc *); 96 Static int ar9003_paprd_tx_tone(struct athn_softc *); 97 Static void ar9003_paprd_tx_tone_done(struct athn_softc *); 98 Static int ar9003_read_eep_data(struct athn_softc *, uint32_t, void *, 99 int); 100 Static int ar9003_read_eep_word(struct athn_softc *, uint32_t, 101 uint16_t *); 102 Static int ar9003_read_otp_data(struct athn_softc *, uint32_t, void *, 103 int); 104 Static int ar9003_read_otp_word(struct athn_softc *, uint32_t, 105 uint32_t *); 106 Static int ar9003_read_rom(struct athn_softc *); 107 Static void ar9003_reset_rx_gain(struct athn_softc *, 108 struct ieee80211_channel *); 109 Static void ar9003_reset_tx_gain(struct athn_softc *, 110 struct ieee80211_channel *); 111 Static int ar9003_restore_rom_block(struct athn_softc *, uint8_t, 112 uint8_t, const uint8_t *, size_t); 113 Static void ar9003_rf_bus_release(struct athn_softc *); 114 Static int ar9003_rf_bus_request(struct athn_softc *); 115 Static void ar9003_rfsilent_init(struct athn_softc *); 116 Static int ar9003_rx_alloc(struct athn_softc *, int, int); 117 Static void ar9003_rx_enable(struct athn_softc *); 118 Static void ar9003_rx_free(struct athn_softc *, int); 119 Static void ar9003_rx_intr(struct athn_softc *, int); 120 Static int ar9003_rx_process(struct athn_softc *, int); 121 Static void ar9003_rx_radiotap(struct athn_softc *, struct mbuf *, 122 struct ar_rx_status *); 123 Static void ar9003_set_cck_weak_signal(struct athn_softc *, int); 124 Static void ar9003_set_delta_slope(struct athn_softc *, 125 struct ieee80211_channel *, struct ieee80211_channel *); 126 Static void ar9003_set_firstep_level(struct athn_softc *, int); 127 Static void ar9003_set_noise_immunity_level(struct athn_softc *, int); 128 Static void ar9003_set_phy(struct athn_softc *, struct ieee80211_channel *, 129 struct ieee80211_channel *); 130 Static void ar9003_set_rf_mode(struct athn_softc *, 131 struct ieee80211_channel *); 132 Static void ar9003_set_rxchains(struct athn_softc *); 133 Static void ar9003_set_spur_immunity_level(struct athn_softc *, int); 134 Static void ar9003_set_training_gain(struct athn_softc *, int); 135 Static int ar9003_swba_intr(struct athn_softc *); 136 Static int ar9003_tx(struct athn_softc *, struct mbuf *, 137 struct ieee80211_node *, int); 138 Static int ar9003_tx_alloc(struct athn_softc *); 139 Static void ar9003_tx_free(struct athn_softc *); 140 Static void ar9003_tx_intr(struct athn_softc *); 141 Static int ar9003_tx_process(struct athn_softc *); 142 143 #ifdef notused 144 Static void ar9003_bb_load_noisefloor(struct athn_softc *); 145 Static void ar9003_get_noisefloor(struct athn_softc *, 146 struct ieee80211_channel *); 147 Static void ar9003_paprd_calib(struct athn_softc *, 148 struct ieee80211_channel *); 149 Static void ar9003_read_noisefloor(struct athn_softc *, int16_t *, 150 int16_t *); 151 Static void ar9003_write_noisefloor(struct athn_softc *, int16_t *, 152 int16_t *); 153 Static void ar9300_noisefloor_calib(struct athn_softc *); 154 #endif /* notused */ 155 156 /* 157 * XXX: See if_iwn.c:MCLGETIalt() for a better solution. 158 * XXX: Put this in a header or in athn.c so it can be shared between 159 * ar5008.c and ar9003.c? 160 */ 161 static struct mbuf * 162 MCLGETI(struct athn_softc *sc __unused, int how, 163 struct ifnet *ifp __unused, u_int size) 164 { 165 struct mbuf *m; 166 167 MGETHDR(m, how, MT_DATA); 168 if (m == NULL) 169 return NULL; 170 171 MEXTMALLOC(m, size, how); 172 if ((m->m_flags & M_EXT) == 0) { 173 m_freem(m); 174 return NULL; 175 } 176 return m; 177 } 178 179 PUBLIC int 180 ar9003_attach(struct athn_softc *sc) 181 { 182 struct athn_ops *ops = &sc->sc_ops; 183 int error; 184 185 /* Set callbacks for AR9003 family. */ 186 ops->gpio_read = ar9003_gpio_read; 187 ops->gpio_write = ar9003_gpio_write; 188 ops->gpio_config_input = ar9003_gpio_config_input; 189 ops->gpio_config_output = ar9003_gpio_config_output; 190 ops->rfsilent_init = ar9003_rfsilent_init; 191 192 ops->dma_alloc = ar9003_dma_alloc; 193 ops->dma_free = ar9003_dma_free; 194 ops->rx_enable = ar9003_rx_enable; 195 ops->intr = ar9003_intr; 196 ops->tx = ar9003_tx; 197 198 ops->set_rf_mode = ar9003_set_rf_mode; 199 ops->rf_bus_request = ar9003_rf_bus_request; 200 ops->rf_bus_release = ar9003_rf_bus_release; 201 ops->set_phy = ar9003_set_phy; 202 ops->set_delta_slope = ar9003_set_delta_slope; 203 ops->enable_antenna_diversity = ar9003_enable_antenna_diversity; 204 ops->init_baseband = ar9003_init_baseband; 205 ops->disable_phy = ar9003_disable_phy; 206 ops->set_rxchains = ar9003_set_rxchains; 207 ops->noisefloor_calib = ar9003_do_noisefloor_calib; 208 ops->do_calib = ar9003_do_calib; 209 ops->next_calib = ar9003_next_calib; 210 ops->hw_init = ar9003_hw_init; 211 212 ops->set_noise_immunity_level = ar9003_set_noise_immunity_level; 213 ops->enable_ofdm_weak_signal = ar9003_enable_ofdm_weak_signal; 214 ops->disable_ofdm_weak_signal = ar9003_disable_ofdm_weak_signal; 215 ops->set_cck_weak_signal = ar9003_set_cck_weak_signal; 216 ops->set_firstep_level = ar9003_set_firstep_level; 217 ops->set_spur_immunity_level = ar9003_set_spur_immunity_level; 218 219 /* Set MAC registers offsets. */ 220 sc->sc_obs_off = AR_OBS; 221 sc->sc_gpio_input_en_off = AR_GPIO_INPUT_EN_VAL; 222 223 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 224 athn_config_nonpcie(sc); 225 else 226 athn_config_pcie(sc); 227 228 /* Determine ROM type and location. */ 229 if ((error = ar9003_find_rom(sc)) != 0) { 230 printf("%s: could not find ROM\n", device_xname(sc->sc_dev)); 231 return error; 232 } 233 /* Read entire ROM content in memory. */ 234 if ((error = ar9003_read_rom(sc)) != 0) { 235 printf("%s: could not read ROM\n", device_xname(sc->sc_dev)); 236 return error; 237 } 238 239 /* Determine if it is a non-enterprise AR9003 card. */ 240 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_MPSD) 241 sc->sc_flags |= ATHN_FLAG_NON_ENTERPRISE; 242 243 ops->setup(sc); 244 return 0; 245 } 246 247 /* 248 * Read 16-bit word from EEPROM. 249 */ 250 Static int 251 ar9003_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val) 252 { 253 uint32_t reg; 254 int ntries; 255 256 reg = AR_READ(sc, AR_EEPROM_OFFSET(addr)); 257 for (ntries = 0; ntries < 1000; ntries++) { 258 reg = AR_READ(sc, AR_EEPROM_STATUS_DATA); 259 if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY | 260 AR_EEPROM_STATUS_DATA_PROT_ACCESS))) { 261 *val = MS(reg, AR_EEPROM_STATUS_DATA_VAL); 262 return 0; 263 } 264 DELAY(10); 265 } 266 *val = 0xffff; 267 return ETIMEDOUT; 268 } 269 270 /* 271 * Read an arbitrary number of bytes at a specified address in EEPROM. 272 * NB: The address may not be 16-bit aligned. 273 */ 274 Static int 275 ar9003_read_eep_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 276 { 277 uint8_t *dst = buf; 278 uint16_t val; 279 int error; 280 281 if (len > 0 && (addr & 1)) { 282 /* Deal with non-aligned reads. */ 283 addr >>= 1; 284 error = ar9003_read_eep_word(sc, addr, &val); 285 if (error != 0) 286 return error; 287 *dst++ = val & 0xff; 288 addr--; 289 len--; 290 } 291 else 292 addr >>= 1; 293 for (; len >= 2; addr--, len -= 2) { 294 error = ar9003_read_eep_word(sc, addr, &val); 295 if (error != 0) 296 return error; 297 *dst++ = val >> 8; 298 *dst++ = val & 0xff; 299 } 300 if (len > 0) { 301 error = ar9003_read_eep_word(sc, addr, &val); 302 if (error != 0) 303 return error; 304 *dst++ = val >> 8; 305 } 306 return 0; 307 } 308 309 /* 310 * Read 32-bit word from OTPROM. 311 */ 312 Static int 313 ar9003_read_otp_word(struct athn_softc *sc, uint32_t addr, uint32_t *val) 314 { 315 uint32_t reg; 316 int ntries; 317 318 reg = AR_READ(sc, AR_OTP_BASE(addr)); 319 for (ntries = 0; ntries < 1000; ntries++) { 320 reg = AR_READ(sc, AR_OTP_STATUS); 321 if (MS(reg, AR_OTP_STATUS_TYPE) == AR_OTP_STATUS_VALID) { 322 *val = AR_READ(sc, AR_OTP_READ_DATA); 323 return 0; 324 } 325 DELAY(10); 326 } 327 return ETIMEDOUT; 328 } 329 330 /* 331 * Read an arbitrary number of bytes at a specified address in OTPROM. 332 * NB: The address may not be 32-bit aligned. 333 */ 334 Static int 335 ar9003_read_otp_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 336 { 337 uint8_t *dst = buf; 338 uint32_t val; 339 int error; 340 341 /* NB: not optimal for non-aligned reads, but correct. */ 342 for (; len > 0; addr--, len--) { 343 error = ar9003_read_otp_word(sc, addr >> 2, &val); 344 if (error != 0) 345 return error; 346 *dst++ = (val >> ((addr & 3) * 8)) & 0xff; 347 } 348 return 0; 349 } 350 351 /* 352 * Determine if the chip has an external EEPROM or an OTPROM and its size. 353 */ 354 Static int 355 ar9003_find_rom(struct athn_softc *sc) 356 { 357 struct athn_ops *ops = &sc->sc_ops; 358 uint32_t hdr; 359 int error; 360 361 /* Try EEPROM. */ 362 ops->read_rom_data = ar9003_read_eep_data; 363 364 sc->sc_eep_size = AR_SREV_9485(sc) ? 4096 : 1024; 365 sc->sc_eep_base = sc->sc_eep_size - 1; 366 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 367 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 368 return 0; 369 370 sc->sc_eep_size = 512; 371 sc->sc_eep_base = sc->sc_eep_size - 1; 372 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 373 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 374 return 0; 375 376 /* Try OTPROM. */ 377 ops->read_rom_data = ar9003_read_otp_data; 378 379 sc->sc_eep_size = 1024; 380 sc->sc_eep_base = sc->sc_eep_size - 1; 381 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 382 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 383 return 0; 384 385 sc->sc_eep_size = 512; 386 sc->sc_eep_base = sc->sc_eep_size - 1; 387 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 388 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 389 return 0; 390 391 return EIO; /* Not found. */ 392 } 393 394 Static int 395 ar9003_restore_rom_block(struct athn_softc *sc, uint8_t alg, uint8_t ref, 396 const uint8_t *buf, size_t len) 397 { 398 const uint8_t *def, *ptr, *end; 399 uint8_t *eep = sc->sc_eep; 400 size_t off, clen; 401 402 if (alg == AR_EEP_COMPRESS_BLOCK) { 403 /* Block contains chunks that shadow ROM template. */ 404 def = sc->sc_ops.get_rom_template(sc, ref); 405 if (def == NULL) { 406 DPRINTFN(DBG_INIT, sc, "unknown template image %d\n", 407 ref); 408 return EINVAL; 409 } 410 /* Start with template. */ 411 memcpy(eep, def, sc->sc_eep_size); 412 /* Shadow template with chunks. */ 413 off = 0; /* Offset in ROM image. */ 414 ptr = buf; /* Offset in block. */ 415 end = buf + len; 416 /* Process chunks. */ 417 while (ptr + 2 <= end) { 418 off += *ptr++; /* Gap with previous chunk. */ 419 clen = *ptr++; /* Chunk length. */ 420 /* Make sure block is large enough. */ 421 if (ptr + clen > end) 422 return EINVAL; 423 /* Make sure chunk fits in ROM image. */ 424 if (off + clen > sc->sc_eep_size) 425 return EINVAL; 426 /* Restore chunk. */ 427 DPRINTFN(DBG_INIT, sc, "ROM chunk @%zd/%zd\n", 428 off, clen); 429 memcpy(&eep[off], ptr, clen); 430 ptr += clen; 431 off += clen; 432 } 433 } 434 else if (alg == AR_EEP_COMPRESS_NONE) { 435 /* Block contains full ROM image. */ 436 if (len != sc->sc_eep_size) { 437 DPRINTFN(DBG_INIT, sc, "block length mismatch %zd\n", 438 len); 439 return EINVAL; 440 } 441 memcpy(eep, buf, len); 442 } 443 return 0; 444 } 445 446 Static int 447 ar9003_read_rom(struct athn_softc *sc) 448 { 449 struct athn_ops *ops = &sc->sc_ops; 450 uint8_t *buf, *ptr, alg, ref; 451 uint16_t sum, rsum; 452 uint32_t hdr; 453 int error, addr; 454 size_t len, i, j; 455 456 /* Allocate space to store ROM in host memory. */ 457 sc->sc_eep = malloc(sc->sc_eep_size, M_DEVBUF, M_NOWAIT); 458 if (sc->sc_eep == NULL) 459 return ENOMEM; 460 461 /* Allocate temporary buffer to store ROM blocks. */ 462 buf = malloc(2048, M_DEVBUF, M_NOWAIT); 463 if (buf == NULL) 464 return ENOMEM; 465 466 /* Restore vendor-specified ROM blocks. */ 467 addr = sc->sc_eep_base; 468 for (i = 0; i < 100; i++) { 469 /* Read block header. */ 470 error = ops->read_rom_data(sc, addr, &hdr, sizeof(hdr)); 471 if (error != 0) 472 break; 473 if (hdr == 0 || hdr == 0xffffffff) 474 break; 475 addr -= sizeof(hdr); 476 477 /* Extract bits from header. */ 478 ptr = (uint8_t *)&hdr; 479 alg = (ptr[0] & 0xe0) >> 5; 480 ref = (ptr[1] & 0x80) >> 2 | (ptr[0] & 0x1f); 481 len = (ptr[1] & 0x7f) << 4 | (ptr[2] & 0xf0) >> 4; 482 DPRINTFN(DBG_INIT, sc, 483 "ROM block %zd: alg=%d ref=%d len=%zd\n", 484 i, alg, ref, len); 485 486 /* Read block data (len <= 0x7ff). */ 487 error = ops->read_rom_data(sc, addr, buf, len); 488 if (error != 0) 489 break; 490 addr -= len; 491 492 /* Read block checksum. */ 493 error = ops->read_rom_data(sc, addr, &sum, sizeof(sum)); 494 if (error != 0) 495 break; 496 addr -= sizeof(sum); 497 498 /* Compute block checksum. */ 499 rsum = 0; 500 for (j = 0; j < len; j++) 501 rsum += buf[j]; 502 /* Compare to that in ROM. */ 503 if (le16toh(sum) != rsum) { 504 DPRINTFN(DBG_INIT, sc, 505 "bad block checksum 0x%x/0x%x\n", 506 le16toh(sum), rsum); 507 continue; /* Skip bad block. */ 508 } 509 /* Checksum is correct, restore block. */ 510 ar9003_restore_rom_block(sc, alg, ref, buf, len); 511 } 512 #if BYTE_ORDER == BIG_ENDIAN 513 /* NB: ROM is always little endian. */ 514 if (error == 0) 515 ops->swap_rom(sc); 516 #endif 517 free(buf, M_DEVBUF); 518 return error; 519 } 520 521 /* 522 * Access to General Purpose Input/Output ports. 523 */ 524 Static int 525 ar9003_gpio_read(struct athn_softc *sc, int pin) 526 { 527 528 KASSERT(pin < sc->sc_ngpiopins); 529 return ((AR_READ(sc, AR_GPIO_IN) & AR9300_GPIO_IN_VAL) & 530 (1 << pin)) != 0; 531 } 532 533 Static void 534 ar9003_gpio_write(struct athn_softc *sc, int pin, int set) 535 { 536 uint32_t reg; 537 538 KASSERT(pin < sc->sc_ngpiopins); 539 reg = AR_READ(sc, AR_GPIO_IN_OUT); 540 if (set) 541 reg |= 1 << pin; 542 else 543 reg &= ~(1 << pin); 544 AR_WRITE(sc, AR_GPIO_IN_OUT, reg); 545 AR_WRITE_BARRIER(sc); 546 } 547 548 Static void 549 ar9003_gpio_config_input(struct athn_softc *sc, int pin) 550 { 551 uint32_t reg; 552 553 reg = AR_READ(sc, AR_GPIO_OE_OUT); 554 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 555 reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2); 556 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 557 AR_WRITE_BARRIER(sc); 558 } 559 560 Static void 561 ar9003_gpio_config_output(struct athn_softc *sc, int pin, int type) 562 { 563 uint32_t reg; 564 int mux, off; 565 566 mux = pin / 6; 567 off = pin % 6; 568 569 reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux)); 570 reg &= ~(0x1f << (off * 5)); 571 reg |= (type & 0x1f) << (off * 5); 572 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg); 573 574 reg = AR_READ(sc, AR_GPIO_OE_OUT); 575 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 576 reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2); 577 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 578 AR_WRITE_BARRIER(sc); 579 } 580 581 Static void 582 ar9003_rfsilent_init(struct athn_softc *sc) 583 { 584 uint32_t reg; 585 586 /* Configure hardware radio switch. */ 587 AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 588 reg = AR_READ(sc, AR_GPIO_INPUT_MUX2); 589 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); 590 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg); 591 ar9003_gpio_config_input(sc, sc->sc_rfsilent_pin); 592 AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB); 593 if (!(sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED)) { 594 AR_SETBITS(sc, AR_GPIO_INTR_POL, 595 AR_GPIO_INTR_POL_PIN(sc->sc_rfsilent_pin)); 596 } 597 AR_WRITE_BARRIER(sc); 598 } 599 600 Static int 601 ar9003_dma_alloc(struct athn_softc *sc) 602 { 603 int error; 604 605 error = ar9003_tx_alloc(sc); 606 if (error != 0) 607 return error; 608 609 error = ar9003_rx_alloc(sc, ATHN_QID_LP, AR9003_RX_LP_QDEPTH); 610 if (error != 0) 611 return error; 612 613 error = ar9003_rx_alloc(sc, ATHN_QID_HP, AR9003_RX_HP_QDEPTH); 614 if (error != 0) 615 return error; 616 617 return 0; 618 } 619 620 Static void 621 ar9003_dma_free(struct athn_softc *sc) 622 { 623 624 ar9003_tx_free(sc); 625 ar9003_rx_free(sc, ATHN_QID_LP); 626 ar9003_rx_free(sc, ATHN_QID_HP); 627 } 628 629 Static int 630 ar9003_tx_alloc(struct athn_softc *sc) 631 { 632 struct athn_tx_buf *bf; 633 bus_size_t size; 634 int error, nsegs, i; 635 636 /* 637 * Allocate Tx status ring. 638 */ 639 size = AR9003_NTXSTATUS * sizeof(struct ar_tx_status); 640 641 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 642 BUS_DMA_NOWAIT, &sc->sc_txsmap); 643 if (error != 0) 644 goto fail; 645 646 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_txsseg, 1, 647 // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 648 &nsegs, BUS_DMA_NOWAIT); 649 if (error != 0) 650 goto fail; 651 652 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_txsseg, 1, size, 653 (void **)&sc->sc_txsring, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 654 if (error != 0) 655 goto fail; 656 657 error = bus_dmamap_load_raw(sc->sc_dmat, sc->sc_txsmap, &sc->sc_txsseg, 658 1, size, BUS_DMA_NOWAIT | BUS_DMA_READ); 659 if (error != 0) 660 goto fail; 661 662 /* 663 * Allocate a pool of Tx descriptors shared between all Tx queues. 664 */ 665 size = ATHN_NTXBUFS * sizeof(struct ar_tx_desc); 666 667 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 668 BUS_DMA_NOWAIT, &sc->sc_map); 669 if (error != 0) 670 goto fail; 671 672 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_seg, 1, 673 // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 674 &nsegs, BUS_DMA_NOWAIT); 675 if (error != 0) 676 goto fail; 677 678 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, 1, size, 679 (void **)&sc->sc_descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 680 if (error != 0) 681 goto fail; 682 683 error = bus_dmamap_load_raw(sc->sc_dmat, sc->sc_map, &sc->sc_seg, 1, size, 684 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 685 if (error != 0) 686 goto fail; 687 688 SIMPLEQ_INIT(&sc->sc_txbufs); 689 for (i = 0; i < ATHN_NTXBUFS; i++) { 690 bf = &sc->sc_txpool[i]; 691 692 error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ, 693 AR9003_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT, 694 &bf->bf_map); 695 if (error != 0) { 696 printf("%s: could not create Tx buf DMA map\n", 697 device_xname(sc->sc_dev)); 698 goto fail; 699 } 700 701 bf->bf_descs = &((struct ar_tx_desc *)sc->sc_descs)[i]; 702 bf->bf_daddr = sc->sc_map->dm_segs[0].ds_addr + 703 i * sizeof(struct ar_tx_desc); 704 705 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 706 } 707 return 0; 708 fail: 709 ar9003_tx_free(sc); 710 return error; 711 } 712 713 Static void 714 ar9003_tx_free(struct athn_softc *sc) 715 { 716 struct athn_tx_buf *bf; 717 int i; 718 719 for (i = 0; i < ATHN_NTXBUFS; i++) { 720 bf = &sc->sc_txpool[i]; 721 722 if (bf->bf_map != NULL) 723 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 724 } 725 /* Free Tx descriptors. */ 726 if (sc->sc_map != NULL) { 727 if (sc->sc_descs != NULL) { 728 bus_dmamap_unload(sc->sc_dmat, sc->sc_map); 729 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 730 ATHN_NTXBUFS * sizeof(struct ar_tx_desc)); 731 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 732 } 733 bus_dmamap_destroy(sc->sc_dmat, sc->sc_map); 734 } 735 /* Free Tx status ring. */ 736 if (sc->sc_txsmap != NULL) { 737 if (sc->sc_txsring != NULL) { 738 bus_dmamap_unload(sc->sc_dmat, sc->sc_txsmap); 739 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_txsring, 740 AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 741 bus_dmamem_free(sc->sc_dmat, &sc->sc_txsseg, 1); 742 } 743 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsmap); 744 } 745 } 746 747 Static int 748 ar9003_rx_alloc(struct athn_softc *sc, int qid, int count) 749 { 750 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 751 struct athn_rx_buf *bf; 752 struct ar_rx_status *ds; 753 int error, i; 754 755 rxq->bf = malloc(count * sizeof(*bf), M_DEVBUF, M_NOWAIT | M_ZERO); 756 if (rxq->bf == NULL) 757 return ENOMEM; 758 759 rxq->count = count; 760 761 for (i = 0; i < rxq->count; i++) { 762 bf = &rxq->bf[i]; 763 764 error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1, 765 ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 766 &bf->bf_map); 767 if (error != 0) { 768 printf("%s: could not create Rx buf DMA map\n", 769 device_xname(sc->sc_dev)); 770 goto fail; 771 } 772 /* 773 * Assumes MCLGETI returns cache-line-size aligned buffers. 774 */ 775 bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 776 if (bf->bf_m == NULL) { 777 printf("%s: could not allocate Rx mbuf\n", 778 device_xname(sc->sc_dev)); 779 error = ENOBUFS; 780 goto fail; 781 } 782 783 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 784 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 785 BUS_DMA_NOWAIT); 786 if (error != 0) { 787 printf("%s: could not DMA map Rx buffer\n", 788 device_xname(sc->sc_dev)); 789 goto fail; 790 } 791 792 ds = mtod(bf->bf_m, struct ar_rx_status *); 793 memset(ds, 0, sizeof(*ds)); 794 bf->bf_desc = ds; 795 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 796 797 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 798 BUS_DMASYNC_PREREAD); 799 } 800 return 0; 801 fail: 802 ar9003_rx_free(sc, qid); 803 return error; 804 } 805 806 Static void 807 ar9003_rx_free(struct athn_softc *sc, int qid) 808 { 809 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 810 struct athn_rx_buf *bf; 811 int i; 812 813 if (rxq->bf == NULL) 814 return; 815 for (i = 0; i < rxq->count; i++) { 816 bf = &rxq->bf[i]; 817 818 if (bf->bf_map != NULL) 819 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 820 if (bf->bf_m != NULL) 821 m_freem(bf->bf_m); 822 } 823 free(rxq->bf, M_DEVBUF); 824 } 825 826 PUBLIC void 827 ar9003_reset_txsring(struct athn_softc *sc) 828 { 829 830 sc->sc_txscur = 0; 831 memset(sc->sc_txsring, 0, AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 832 AR_WRITE(sc, AR_Q_STATUS_RING_START, 833 sc->sc_txsmap->dm_segs[0].ds_addr); 834 AR_WRITE(sc, AR_Q_STATUS_RING_END, 835 sc->sc_txsmap->dm_segs[0].ds_addr + sc->sc_txsmap->dm_segs[0].ds_len); 836 AR_WRITE_BARRIER(sc); 837 } 838 839 Static void 840 ar9003_rx_enable(struct athn_softc *sc) 841 { 842 struct athn_rxq *rxq; 843 struct athn_rx_buf *bf; 844 struct ar_rx_status *ds; 845 uint32_t reg; 846 int qid, i; 847 848 reg = AR_READ(sc, AR_RXBP_THRESH); 849 reg = RW(reg, AR_RXBP_THRESH_HP, 1); 850 reg = RW(reg, AR_RXBP_THRESH_LP, 1); 851 AR_WRITE(sc, AR_RXBP_THRESH, reg); 852 853 /* Set Rx buffer size. */ 854 AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds)); 855 856 for (qid = 0; qid < 2; qid++) { 857 rxq = &sc->sc_rxq[qid]; 858 859 /* Setup Rx status descriptors. */ 860 SIMPLEQ_INIT(&rxq->head); 861 for (i = 0; i < rxq->count; i++) { 862 bf = &rxq->bf[i]; 863 ds = bf->bf_desc; 864 865 memset(ds, 0, sizeof(*ds)); 866 if (qid == ATHN_QID_LP) 867 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 868 else 869 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 870 AR_WRITE_BARRIER(sc); 871 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 872 } 873 } 874 /* Enable Rx. */ 875 AR_WRITE(sc, AR_CR, 0); 876 AR_WRITE_BARRIER(sc); 877 } 878 879 Static void 880 ar9003_rx_radiotap(struct athn_softc *sc, struct mbuf *m, 881 struct ar_rx_status *ds) 882 { 883 struct athn_rx_radiotap_header *tap = &sc->sc_rxtap; 884 struct ieee80211com *ic = &sc->sc_ic; 885 uint64_t tsf; 886 uint32_t tstamp; 887 uint8_t rate; 888 889 /* Extend the 15-bit timestamp from Rx status to 64-bit TSF. */ 890 tstamp = ds->ds_status3; 891 tsf = AR_READ(sc, AR_TSF_U32); 892 tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32); 893 if ((tsf & 0x7fff) < tstamp) 894 tsf -= 0x8000; 895 tsf = (tsf & ~0x7fff) | tstamp; 896 897 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 898 tap->wr_tsft = htole64(tsf); 899 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 900 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 901 tap->wr_dbm_antsignal = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 902 /* XXX noise. */ 903 tap->wr_antenna = MS(ds->ds_status4, AR_RXS4_ANTENNA); 904 tap->wr_rate = 0; /* In case it can't be found below. */ 905 rate = MS(ds->ds_status1, AR_RXS1_RATE); 906 if (rate & 0x80) { /* HT. */ 907 /* Bit 7 set means HT MCS instead of rate. */ 908 tap->wr_rate = rate; 909 if (!(ds->ds_status4 & AR_RXS4_GI)) 910 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 911 912 } 913 else if (rate & 0x10) { /* CCK. */ 914 if (rate & 0x04) 915 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 916 switch (rate & ~0x14) { 917 case 0xb: tap->wr_rate = 2; break; 918 case 0xa: tap->wr_rate = 4; break; 919 case 0x9: tap->wr_rate = 11; break; 920 case 0x8: tap->wr_rate = 22; break; 921 } 922 } 923 else { /* OFDM. */ 924 switch (rate) { 925 case 0xb: tap->wr_rate = 12; break; 926 case 0xf: tap->wr_rate = 18; break; 927 case 0xa: tap->wr_rate = 24; break; 928 case 0xe: tap->wr_rate = 36; break; 929 case 0x9: tap->wr_rate = 48; break; 930 case 0xd: tap->wr_rate = 72; break; 931 case 0x8: tap->wr_rate = 96; break; 932 case 0xc: tap->wr_rate = 108; break; 933 } 934 } 935 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 936 } 937 938 Static int 939 ar9003_rx_process(struct athn_softc *sc, int qid) 940 { 941 struct ieee80211com *ic = &sc->sc_ic; 942 struct ifnet *ifp = &sc->sc_if; 943 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 944 struct athn_rx_buf *bf; 945 struct ar_rx_status *ds; 946 struct ieee80211_frame *wh; 947 struct ieee80211_node *ni; 948 struct mbuf *m, *m1; 949 size_t len; 950 u_int32_t rstamp; 951 int error, rssi; 952 953 bf = SIMPLEQ_FIRST(&rxq->head); 954 if (__predict_false(bf == NULL)) { /* Should not happen. */ 955 printf("%s: Rx queue is empty!\n", device_xname(sc->sc_dev)); 956 return ENOENT; 957 } 958 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 959 BUS_DMASYNC_POSTREAD); 960 961 ds = mtod(bf->bf_m, struct ar_rx_status *); 962 if (!(ds->ds_status1 & AR_RXS1_DONE)) 963 return EBUSY; 964 965 /* Check that it is a valid Rx status descriptor. */ 966 if ((ds->ds_info & (AR_RXI_DESC_ID_M | AR_RXI_DESC_TX | 967 AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS)) 968 goto skip; 969 970 if (!(ds->ds_status11 & AR_RXS11_FRAME_OK)) { 971 if (ds->ds_status11 & AR_RXS11_CRC_ERR) 972 DPRINTFN(DBG_RX, sc, "CRC error\n"); 973 else if (ds->ds_status11 & AR_RXS11_PHY_ERR) 974 DPRINTFN(DBG_RX, sc, "PHY error=0x%x\n", 975 MS(ds->ds_status11, AR_RXS11_PHY_ERR_CODE)); 976 else if (ds->ds_status11 & AR_RXS11_DECRYPT_CRC_ERR) 977 DPRINTFN(DBG_RX, sc, "Decryption CRC error\n"); 978 else if (ds->ds_status11 & AR_RXS11_MICHAEL_ERR) { 979 DPRINTFN(DBG_RX, sc, "Michael MIC failure\n"); 980 /* Report Michael MIC failures to net80211. */ 981 982 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 983 m = bf->bf_m; 984 m->m_pkthdr.rcvif = ifp; 985 m->m_data = (void *)&ds[1]; 986 m->m_pkthdr.len = m->m_len = len; 987 wh = mtod(m, struct ieee80211_frame *); 988 989 ieee80211_notify_michael_failure(ic, wh, 990 0 /* XXX: keyix */); 991 } 992 ifp->if_ierrors++; 993 goto skip; 994 } 995 996 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 997 if (__predict_false(len < IEEE80211_MIN_LEN || 998 len > ATHN_RXBUFSZ - sizeof(*ds))) { 999 DPRINTFN(DBG_RX, sc, "corrupted descriptor length=%zd\n", 1000 len); 1001 ifp->if_ierrors++; 1002 goto skip; 1003 } 1004 1005 /* Allocate a new Rx buffer. */ 1006 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 1007 if (__predict_false(m1 == NULL)) { 1008 ic->ic_stats.is_rx_nobuf++; 1009 ifp->if_ierrors++; 1010 goto skip; 1011 } 1012 1013 /* Unmap the old Rx buffer. */ 1014 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1015 1016 /* Map the new Rx buffer. */ 1017 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *), 1018 ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1019 if (__predict_false(error != 0)) { 1020 m_freem(m1); 1021 1022 /* Remap the old Rx buffer or panic. */ 1023 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 1024 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 1025 BUS_DMA_NOWAIT | BUS_DMA_READ); 1026 KASSERT(error != 0); 1027 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1028 ifp->if_ierrors++; 1029 goto skip; 1030 } 1031 bf->bf_desc = mtod(m1, struct ar_rx_status *); 1032 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1033 1034 m = bf->bf_m; 1035 bf->bf_m = m1; 1036 1037 /* Finalize mbuf. */ 1038 m->m_pkthdr.rcvif = ifp; 1039 /* Strip Rx status descriptor from head. */ 1040 m->m_data = (void *)&ds[1]; 1041 m->m_pkthdr.len = m->m_len = len; 1042 1043 /* Grab a reference to the source node. */ 1044 wh = mtod(m, struct ieee80211_frame *); 1045 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1046 1047 /* Remove any HW padding after the 802.11 header. */ 1048 if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) { 1049 u_int hdrlen = ieee80211_anyhdrsize(wh); 1050 if (hdrlen & 3) { 1051 ovbcopy(wh, (uint8_t *)wh + 2, hdrlen); 1052 m_adj(m, 2); 1053 } 1054 } 1055 if (__predict_false(sc->sc_drvbpf != NULL)) 1056 ar9003_rx_radiotap(sc, m, ds); 1057 /* Trim 802.11 FCS after radiotap. */ 1058 m_adj(m, -IEEE80211_CRC_LEN); 1059 1060 /* Send the frame to the 802.11 layer. */ 1061 rssi = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 1062 rstamp = ds->ds_status3; 1063 ieee80211_input(ic, m, ni, rssi, rstamp); 1064 1065 /* Node is no longer needed. */ 1066 ieee80211_free_node(ni); 1067 1068 skip: 1069 /* Unlink this descriptor from head. */ 1070 SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list); 1071 memset(bf->bf_desc, 0, sizeof(*ds)); 1072 1073 /* Re-use this descriptor and link it to tail. */ 1074 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 1075 BUS_DMASYNC_PREREAD); 1076 1077 if (qid == ATHN_QID_LP) 1078 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 1079 else 1080 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 1081 AR_WRITE_BARRIER(sc); 1082 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 1083 1084 /* Re-enable Rx. */ 1085 AR_WRITE(sc, AR_CR, 0); 1086 AR_WRITE_BARRIER(sc); 1087 return 0; 1088 } 1089 1090 Static void 1091 ar9003_rx_intr(struct athn_softc *sc, int qid) 1092 { 1093 1094 while (ar9003_rx_process(sc, qid) == 0) 1095 continue; 1096 } 1097 1098 Static int 1099 ar9003_tx_process(struct athn_softc *sc) 1100 { 1101 struct ifnet *ifp = &sc->sc_if; 1102 struct athn_txq *txq; 1103 struct athn_node *an; 1104 struct athn_tx_buf *bf; 1105 struct ar_tx_status *ds; 1106 uint8_t qid, failcnt; 1107 1108 ds = &((struct ar_tx_status *)sc->sc_txsring)[sc->sc_txscur]; 1109 if (!(ds->ds_status8 & AR_TXS8_DONE)) 1110 return EBUSY; 1111 1112 sc->sc_txscur = (sc->sc_txscur + 1) % AR9003_NTXSTATUS; 1113 1114 /* Check that it is a valid Tx status descriptor. */ 1115 if ((ds->ds_info & (AR_TXI_DESC_ID_M | AR_TXI_DESC_TX)) != 1116 (SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX)) { 1117 memset(ds, 0, sizeof(*ds)); 1118 return 0; 1119 } 1120 /* Retrieve the queue that was used to send this PDU. */ 1121 qid = MS(ds->ds_info, AR_TXI_QCU_NUM); 1122 txq = &sc->sc_txq[qid]; 1123 1124 bf = SIMPLEQ_FIRST(&txq->head); 1125 if (bf == NULL || bf == txq->wait) { 1126 memset(ds, 0, sizeof(*ds)); 1127 return 0; 1128 } 1129 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1130 ifp->if_opackets++; 1131 1132 sc->sc_tx_timer = 0; 1133 1134 if (ds->ds_status3 & AR_TXS3_EXCESSIVE_RETRIES) 1135 ifp->if_oerrors++; 1136 1137 if (ds->ds_status3 & AR_TXS3_UNDERRUN) 1138 athn_inc_tx_trigger_level(sc); 1139 1140 /* Wakeup PA predistortion state machine. */ 1141 if (bf->bf_txflags & ATHN_TXFLAG_PAPRD) 1142 ar9003_paprd_tx_tone_done(sc); 1143 1144 an = (struct athn_node *)bf->bf_ni; 1145 /* 1146 * NB: the data fail count contains the number of un-acked tries 1147 * for the final series used. We must add the number of tries for 1148 * each series that was fully processed. 1149 */ 1150 failcnt = MS(ds->ds_status3, AR_TXS3_DATA_FAIL_CNT); 1151 /* NB: Assume two tries per series. */ 1152 failcnt += MS(ds->ds_status8, AR_TXS8_FINAL_IDX) * 2; 1153 1154 /* Update rate control statistics. */ 1155 an->amn.amn_txcnt++; 1156 if (failcnt > 0) 1157 an->amn.amn_retrycnt++; 1158 1159 DPRINTFN(DBG_TX, sc, "Tx done qid=%d status3=%d fail count=%d\n", 1160 qid, ds->ds_status3, failcnt); 1161 1162 /* Reset Tx status descriptor. */ 1163 memset(ds, 0, sizeof(*ds)); 1164 1165 /* Unmap Tx buffer. */ 1166 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1167 BUS_DMASYNC_POSTWRITE); 1168 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1169 1170 m_freem(bf->bf_m); 1171 bf->bf_m = NULL; 1172 ieee80211_free_node(bf->bf_ni); 1173 bf->bf_ni = NULL; 1174 1175 /* Link Tx buffer back to global free list. */ 1176 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1177 1178 /* Queue buffers that are waiting if there is new room. */ 1179 if (--txq->queued < AR9003_TX_QDEPTH && txq->wait != NULL) { 1180 AR_WRITE(sc, AR_QTXDP(qid), txq->wait->bf_daddr); 1181 AR_WRITE_BARRIER(sc); 1182 txq->wait = SIMPLEQ_NEXT(txq->wait, bf_list); 1183 } 1184 return 0; 1185 } 1186 1187 Static void 1188 ar9003_tx_intr(struct athn_softc *sc) 1189 { 1190 struct ifnet *ifp = &sc->sc_if; 1191 1192 while (ar9003_tx_process(sc) == 0); 1193 1194 if (!SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 1195 ifp->if_flags &= ~IFF_OACTIVE; 1196 ifp->if_start(ifp); 1197 } 1198 } 1199 1200 #ifndef IEEE80211_STA_ONLY 1201 /* 1202 * Process Software Beacon Alert interrupts. 1203 */ 1204 Static int 1205 ar9003_swba_intr(struct athn_softc *sc) 1206 { 1207 struct ieee80211com *ic = &sc->sc_ic; 1208 struct ifnet *ifp = &sc->sc_if; 1209 struct ieee80211_node *ni = ic->ic_bss; 1210 struct athn_tx_buf *bf = sc->sc_bcnbuf; 1211 struct ieee80211_frame *wh; 1212 struct ieee80211_beacon_offsets bo; 1213 struct ar_tx_desc *ds; 1214 struct mbuf *m; 1215 uint32_t sum; 1216 uint8_t ridx, hwrate; 1217 int error, totlen; 1218 1219 #if notyet 1220 if (ic->ic_tim_mcast_pending && 1221 IF_IS_EMPTY(&ni->ni_savedq) && 1222 SIMPLEQ_EMPTY(&sc->sc_txq[ATHN_QID_CAB].head)) 1223 ic->ic_tim_mcast_pending = 0; 1224 #endif 1225 if (ic->ic_dtim_count == 0) 1226 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1227 else 1228 ic->ic_dtim_count--; 1229 1230 /* Make sure previous beacon has been sent. */ 1231 if (athn_tx_pending(sc, ATHN_QID_BEACON)) { 1232 DPRINTFN(DBG_INTR, sc, "beacon stuck\n"); 1233 return EBUSY; 1234 } 1235 /* Get new beacon. */ 1236 m = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 1237 if (__predict_false(m == NULL)) 1238 return ENOBUFS; 1239 /* Assign sequence number. */ 1240 /* XXX: use non-QoS tid? */ 1241 wh = mtod(m, struct ieee80211_frame *); 1242 *(uint16_t *)&wh->i_seq[0] = 1243 htole16(ic->ic_bss->ni_txseqs[0] << IEEE80211_SEQ_SEQ_SHIFT); 1244 ic->ic_bss->ni_txseqs[0]++; 1245 1246 /* Unmap and free old beacon if any. */ 1247 if (__predict_true(bf->bf_m != NULL)) { 1248 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1249 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1250 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1251 m_freem(bf->bf_m); 1252 bf->bf_m = NULL; 1253 } 1254 /* DMA map new beacon. */ 1255 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1256 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1257 if (__predict_false(error != 0)) { 1258 m_freem(m); 1259 return error; 1260 } 1261 bf->bf_m = m; 1262 1263 /* Setup Tx descriptor (simplified ar9003_tx()). */ 1264 ds = bf->bf_descs; 1265 memset(ds, 0, sizeof(*ds)); 1266 1267 ds->ds_info = 1268 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1269 SM(AR_TXI_DESC_NDWORDS, 23) | 1270 SM(AR_TXI_QCU_NUM, ATHN_QID_BEACON) | 1271 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1272 1273 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1274 ds->ds_ctl11 = SM(AR_TXC11_FRAME_LEN, totlen); 1275 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, AR_MAX_RATE_POWER); 1276 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, AR_FRAME_TYPE_BEACON); 1277 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1278 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, AR_ENCR_TYPE_CLEAR); 1279 1280 /* Write number of tries. */ 1281 ds->ds_ctl13 = SM(AR_TXC13_XMIT_DATA_TRIES0, 1); 1282 1283 /* Write Tx rate. */ 1284 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1285 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1286 hwrate = athn_rates[ridx].hwrate; 1287 ds->ds_ctl14 = SM(AR_TXC14_XMIT_RATE0, hwrate); 1288 1289 /* Write Tx chains. */ 1290 ds->ds_ctl18 = SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask); 1291 1292 ds->ds_segs[0].ds_data = bf->bf_map->dm_segs[0].ds_addr; 1293 /* Segment length must be a multiple of 4. */ 1294 ds->ds_segs[0].ds_ctl |= SM(AR_TXC_BUF_LEN, 1295 (bf->bf_map->dm_segs[0].ds_len + 3) & ~3); 1296 /* Compute Tx descriptor checksum. */ 1297 sum = ds->ds_info; 1298 sum += ds->ds_segs[0].ds_data; 1299 sum += ds->ds_segs[0].ds_ctl; 1300 sum = (sum >> 16) + (sum & 0xffff); 1301 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1302 1303 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1304 BUS_DMASYNC_PREWRITE); 1305 1306 /* Stop Tx DMA before putting the new beacon on the queue. */ 1307 athn_stop_tx_dma(sc, ATHN_QID_BEACON); 1308 1309 AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr); 1310 1311 for(;;) { 1312 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) 1313 break; 1314 1315 IF_DEQUEUE(&ni->ni_savedq, m); 1316 if (m == NULL) 1317 break; 1318 if (!IF_IS_EMPTY(&ni->ni_savedq)) { 1319 /* more queued frames, set the more data bit */ 1320 wh = mtod(m, struct ieee80211_frame *); 1321 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 1322 } 1323 1324 if (sc->sc_ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) { 1325 ieee80211_free_node(ni); 1326 ifp->if_oerrors++; 1327 break; 1328 } 1329 } 1330 1331 /* Kick Tx. */ 1332 AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON); 1333 AR_WRITE_BARRIER(sc); 1334 return 0; 1335 } 1336 #endif 1337 1338 Static int 1339 ar9003_intr(struct athn_softc *sc) 1340 { 1341 uint32_t intr, intr2, intr5, sync; 1342 1343 /* Get pending interrupts. */ 1344 intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE); 1345 if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) { 1346 intr = AR_READ(sc, AR_INTR_SYNC_CAUSE); 1347 if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0) 1348 return 0; /* Not for us. */ 1349 } 1350 1351 if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 1352 (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 1353 intr = AR_READ(sc, AR_ISR); 1354 else 1355 intr = 0; 1356 sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync; 1357 if (intr == 0 && sync == 0) 1358 return 0; /* Not for us. */ 1359 1360 if (intr != 0) { 1361 if (intr & AR_ISR_BCNMISC) { 1362 intr2 = AR_READ(sc, AR_ISR_S2); 1363 #ifdef notyet 1364 if (intr2 & AR_ISR_S2_TIM) 1365 /* TBD */; 1366 if (intr2 & AR_ISR_S2_TSFOOR) 1367 /* TBD */; 1368 if (intr2 & AR_ISR_S2_BB_WATCHDOG) 1369 /* TBD */; 1370 #endif 1371 } 1372 intr = AR_READ(sc, AR_ISR_RAC); 1373 if (intr == AR_INTR_SPURIOUS) 1374 return 1; 1375 1376 #ifndef IEEE80211_STA_ONLY 1377 if (intr & AR_ISR_SWBA) 1378 ar9003_swba_intr(sc); 1379 #endif 1380 if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 1381 ar9003_rx_intr(sc, ATHN_QID_LP); 1382 if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 1383 ar9003_rx_intr(sc, ATHN_QID_LP); 1384 if (intr & AR_ISR_HP_RXOK) 1385 ar9003_rx_intr(sc, ATHN_QID_HP); 1386 1387 if (intr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 1388 ar9003_tx_intr(sc); 1389 if (intr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) 1390 ar9003_tx_intr(sc); 1391 1392 if (intr & AR_ISR_GENTMR) { 1393 intr5 = AR_READ(sc, AR_ISR_S5_S); 1394 DPRINTFN(DBG_INTR, sc, 1395 "GENTMR trigger=%d thresh=%d\n", 1396 MS(intr5, AR_ISR_S5_GENTIMER_TRIG), 1397 MS(intr5, AR_ISR_S5_GENTIMER_THRESH)); 1398 } 1399 } 1400 if (sync != 0) { 1401 if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 1402 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF); 1403 AR_WRITE(sc, AR_RC, 0); 1404 } 1405 1406 if ((sc->sc_flags & ATHN_FLAG_RFSILENT) && 1407 (sync & AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin))) { 1408 struct ifnet *ifp = &sc->sc_if; 1409 1410 printf("%s: radio switch turned off\n", 1411 device_xname(sc->sc_dev)); 1412 /* Turn the interface down. */ 1413 ifp->if_flags &= ~IFF_UP; 1414 athn_stop(ifp, 1); 1415 return 1; 1416 } 1417 1418 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync); 1419 (void)AR_READ(sc, AR_INTR_SYNC_CAUSE); 1420 } 1421 return 1; 1422 } 1423 1424 Static int 1425 ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 1426 int txflags) 1427 { 1428 struct ieee80211com *ic = &sc->sc_ic; 1429 struct ieee80211_key *k = NULL; 1430 struct ieee80211_frame *wh; 1431 struct athn_series series[4]; 1432 struct ar_tx_desc *ds; 1433 struct athn_txq *txq; 1434 struct athn_tx_buf *bf; 1435 struct athn_node *an = (void *)ni; 1436 struct mbuf *m1; 1437 uint32_t sum; 1438 uint16_t qos; 1439 uint8_t txpower, type, encrtype, ridx[4]; 1440 int i, error, totlen, hasqos, qid; 1441 1442 /* Grab a Tx buffer from our global free list. */ 1443 bf = SIMPLEQ_FIRST(&sc->sc_txbufs); 1444 KASSERT(bf != NULL); 1445 1446 /* Map 802.11 frame type to hardware frame type. */ 1447 wh = mtod(m, struct ieee80211_frame *); 1448 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1449 IEEE80211_FC0_TYPE_MGT) { 1450 /* NB: Beacons do not use ar9003_tx(). */ 1451 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1452 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1453 type = AR_FRAME_TYPE_PROBE_RESP; 1454 else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1455 IEEE80211_FC0_SUBTYPE_ATIM) 1456 type = AR_FRAME_TYPE_ATIM; 1457 else 1458 type = AR_FRAME_TYPE_NORMAL; 1459 } 1460 else if ((wh->i_fc[0] & 1461 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1462 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_PS_POLL)) { 1463 type = AR_FRAME_TYPE_PSPOLL; 1464 } 1465 else 1466 type = AR_FRAME_TYPE_NORMAL; 1467 1468 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1469 k = ieee80211_crypto_encap(ic, ni, m); 1470 if (k == NULL) 1471 return ENOBUFS; 1472 1473 /* packet header may have moved, reset our local pointer */ 1474 wh = mtod(m, struct ieee80211_frame *); 1475 } 1476 1477 /* XXX 2-byte padding for QoS and 4-addr headers. */ 1478 1479 /* Select the HW Tx queue to use for this frame. */ 1480 if ((hasqos = ieee80211_has_qos(wh))) { 1481 #ifdef notyet_edca 1482 uint8_t tid; 1483 1484 qos = ieee80211_get_qos(wh); 1485 tid = qos & IEEE80211_QOS_TID; 1486 qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)]; 1487 #else 1488 qos = ieee80211_get_qos(wh); 1489 qid = ATHN_QID_AC_BE; 1490 #endif /* notyet_edca */ 1491 } 1492 else if (type == AR_FRAME_TYPE_PSPOLL) { 1493 qos = 0; 1494 qid = ATHN_QID_PSPOLL; 1495 } 1496 else if (txflags & ATHN_TXFLAG_CAB) { 1497 qos = 0; 1498 qid = ATHN_QID_CAB; 1499 } 1500 else { 1501 qos = 0; 1502 qid = ATHN_QID_AC_BE; 1503 } 1504 txq = &sc->sc_txq[qid]; 1505 1506 /* Select the transmit rates to use for this frame. */ 1507 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1508 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 1509 IEEE80211_FC0_TYPE_DATA) { 1510 /* Use lowest rate for all tries. */ 1511 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1512 (ic->ic_curmode == IEEE80211_MODE_11A) ? 1513 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1514 } 1515 else if (ic->ic_fixed_rate != -1) { 1516 /* Use same fixed rate for all tries. */ 1517 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1518 sc->sc_fixed_ridx; 1519 } 1520 else { 1521 int txrate = ni->ni_txrate; 1522 /* Use fallback table of the node. */ 1523 for (i = 0; i < 4; i++) { 1524 ridx[i] = an->ridx[txrate]; 1525 txrate = an->fallback[txrate]; 1526 } 1527 } 1528 1529 if (__predict_false(sc->sc_drvbpf != NULL)) { 1530 struct athn_tx_radiotap_header *tap = &sc->sc_txtap; 1531 1532 tap->wt_flags = 0; 1533 /* Use initial transmit rate. */ 1534 tap->wt_rate = athn_rates[ridx[0]].rate; 1535 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1536 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1537 // XXX tap->wt_hwqueue = qid; 1538 if (ridx[0] != ATHN_RIDX_CCK1 && 1539 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1540 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1541 1542 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 1543 } 1544 1545 /* DMA map mbuf. */ 1546 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1547 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1548 if (__predict_false(error != 0)) { 1549 if (error != EFBIG) { 1550 printf("%s: can't map mbuf (error %d)\n", 1551 device_xname(sc->sc_dev), error); 1552 m_freem(m); 1553 return error; 1554 } 1555 /* 1556 * DMA mapping requires too many DMA segments; linearize 1557 * mbuf in kernel virtual address space and retry. 1558 */ 1559 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1560 if (m1 == NULL) { 1561 m_freem(m); 1562 return ENOBUFS; 1563 } 1564 if (m->m_pkthdr.len > (int)MHLEN) { 1565 MCLGET(m1, M_DONTWAIT); 1566 if (!(m1->m_flags & M_EXT)) { 1567 m_freem(m); 1568 m_freem(m1); 1569 return ENOBUFS; 1570 } 1571 } 1572 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 1573 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1574 m_freem(m); 1575 m = m1; 1576 1577 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1578 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1579 if (error != 0) { 1580 printf("%s: can't map mbuf (error %d)\n", 1581 device_xname(sc->sc_dev), error); 1582 m_freem(m); 1583 return error; 1584 } 1585 } 1586 bf->bf_m = m; 1587 bf->bf_ni = ni; 1588 bf->bf_txflags = txflags; 1589 1590 wh = mtod(m, struct ieee80211_frame *); 1591 1592 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1593 1594 /* Setup Tx descriptor. */ 1595 ds = bf->bf_descs; 1596 memset(ds, 0, sizeof(*ds)); 1597 1598 ds->ds_info = 1599 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1600 SM(AR_TXI_DESC_NDWORDS, 23) | 1601 SM(AR_TXI_QCU_NUM, qid) | 1602 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1603 1604 ds->ds_ctl11 = AR_TXC11_CLR_DEST_MASK; 1605 txpower = AR_MAX_RATE_POWER; /* Get from per-rate registers. */ 1606 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, txpower); 1607 1608 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, type); 1609 1610 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1611 (hasqos && (qos & IEEE80211_QOS_ACKPOLICY_MASK) == 1612 IEEE80211_QOS_ACKPOLICY_NOACK)) 1613 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1614 1615 #if notyet 1616 if (0 && k != NULL) { 1617 uintptr_t entry; 1618 1619 /* 1620 * Map 802.11 cipher to hardware encryption type and 1621 * compute MIC+ICV overhead. 1622 */ 1623 switch (k->k_cipher) { 1624 case IEEE80211_CIPHER_WEP40: 1625 case IEEE80211_CIPHER_WEP104: 1626 encrtype = AR_ENCR_TYPE_WEP; 1627 totlen += 4; 1628 break; 1629 case IEEE80211_CIPHER_TKIP: 1630 encrtype = AR_ENCR_TYPE_TKIP; 1631 totlen += 12; 1632 break; 1633 case IEEE80211_CIPHER_CCMP: 1634 encrtype = AR_ENCR_TYPE_AES; 1635 totlen += 8; 1636 break; 1637 default: 1638 panic("unsupported cipher"); 1639 } 1640 /* 1641 * NB: The key cache entry index is stored in the key 1642 * private field when the key is installed. 1643 */ 1644 entry = (uintptr_t)k->k_priv; 1645 ds->ds_ctl12 |= SM(AR_TXC12_DEST_IDX, entry); 1646 ds->ds_ctl11 |= AR_TXC11_DEST_IDX_VALID; 1647 } 1648 else 1649 #endif 1650 encrtype = AR_ENCR_TYPE_CLEAR; 1651 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, encrtype); 1652 1653 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 1654 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1655 /* NB: Group frames are sent using CCK in 802.11b/g. */ 1656 if (totlen > ic->ic_rtsthreshold) { 1657 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1658 } 1659 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1660 athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) { 1661 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1662 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1663 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1664 ds->ds_ctl11 |= AR_TXC11_CTS_ENABLE; 1665 } 1666 } 1667 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1668 /* Disable multi-rate retries when protection is used. */ 1669 ridx[1] = ridx[2] = ridx[3] = ridx[0]; 1670 } 1671 /* Setup multi-rate retries. */ 1672 for (i = 0; i < 4; i++) { 1673 series[i].hwrate = athn_rates[ridx[i]].hwrate; 1674 if (athn_rates[ridx[i]].phy == IEEE80211_T_DS && 1675 ridx[i] != ATHN_RIDX_CCK1 && 1676 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1677 series[i].hwrate |= 0x04; 1678 series[i].dur = 0; 1679 } 1680 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1681 /* Compute duration for each series. */ 1682 for (i = 0; i < 4; i++) { 1683 series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN, 1684 athn_rates[ridx[i]].rspridx, ic->ic_flags); 1685 } 1686 } 1687 /* If this is a PA training frame, select the Tx chain to use. */ 1688 if (__predict_false(txflags & ATHN_TXFLAG_PAPRD)) { 1689 ds->ds_ctl12 |= SM(AR_TXC12_PAPRD_CHAIN_MASK, 1690 1 << sc->sc_paprd_curchain); 1691 } 1692 1693 /* Write number of tries for each series. */ 1694 ds->ds_ctl13 = 1695 SM(AR_TXC13_XMIT_DATA_TRIES0, 2) | 1696 SM(AR_TXC13_XMIT_DATA_TRIES1, 2) | 1697 SM(AR_TXC13_XMIT_DATA_TRIES2, 2) | 1698 SM(AR_TXC13_XMIT_DATA_TRIES3, 4); 1699 1700 /* Tell HW to update duration field in 802.11 header. */ 1701 if (type != AR_FRAME_TYPE_PSPOLL) 1702 ds->ds_ctl13 |= AR_TXC13_DUR_UPDATE_ENA; 1703 1704 /* Write Tx rate for each series. */ 1705 ds->ds_ctl14 = 1706 SM(AR_TXC14_XMIT_RATE0, series[0].hwrate) | 1707 SM(AR_TXC14_XMIT_RATE1, series[1].hwrate) | 1708 SM(AR_TXC14_XMIT_RATE2, series[2].hwrate) | 1709 SM(AR_TXC14_XMIT_RATE3, series[3].hwrate); 1710 1711 /* Write duration for each series. */ 1712 ds->ds_ctl15 = 1713 SM(AR_TXC15_PACKET_DUR0, series[0].dur) | 1714 SM(AR_TXC15_PACKET_DUR1, series[1].dur); 1715 ds->ds_ctl16 = 1716 SM(AR_TXC16_PACKET_DUR2, series[2].dur) | 1717 SM(AR_TXC16_PACKET_DUR3, series[3].dur); 1718 1719 if ((sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) && 1720 ic->ic_curmode == IEEE80211_MODE_11A) { 1721 /* 1722 * In order to not exceed PCIe power requirements, we only 1723 * use two Tx chains for MCS0~15 on 5GHz band on these chips. 1724 */ 1725 ds->ds_ctl18 = 1726 SM(AR_TXC18_CHAIN_SEL0, 1727 (ridx[0] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1728 SM(AR_TXC18_CHAIN_SEL1, 1729 (ridx[1] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1730 SM(AR_TXC18_CHAIN_SEL2, 1731 (ridx[2] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1732 SM(AR_TXC18_CHAIN_SEL3, 1733 (ridx[3] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask); 1734 } 1735 else { 1736 /* Use the same Tx chains for all tries. */ 1737 ds->ds_ctl18 = 1738 SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask) | 1739 SM(AR_TXC18_CHAIN_SEL1, sc->sc_txchainmask) | 1740 SM(AR_TXC18_CHAIN_SEL2, sc->sc_txchainmask) | 1741 SM(AR_TXC18_CHAIN_SEL3, sc->sc_txchainmask); 1742 } 1743 #ifdef notyet 1744 #ifndef IEEE80211_NO_HT 1745 /* Use the same short GI setting for all tries. */ 1746 if (ic->ic_flags & IEEE80211_F_SHGI) 1747 ds->ds_ctl18 |= AR_TXC18_GI0123; 1748 /* Use the same channel width for all tries. */ 1749 if (ic->ic_flags & IEEE80211_F_CBW40) 1750 ds->ds_ctl18 |= AR_TXC18_2040_0123; 1751 #endif 1752 #endif 1753 1754 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1755 uint8_t protridx, hwrate; 1756 uint16_t dur = 0; 1757 1758 /* Use the same protection mode for all tries. */ 1759 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1760 ds->ds_ctl15 |= AR_TXC15_RTSCTS_QUAL01; 1761 ds->ds_ctl16 |= AR_TXC16_RTSCTS_QUAL23; 1762 } 1763 /* Select protection rate (suboptimal but ok). */ 1764 protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1765 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2; 1766 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1767 /* Account for CTS duration. */ 1768 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1769 athn_rates[protridx].rspridx, ic->ic_flags); 1770 } 1771 dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags); 1772 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1773 /* Account for ACK duration. */ 1774 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1775 athn_rates[ridx[0]].rspridx, ic->ic_flags); 1776 } 1777 /* Write protection frame duration and rate. */ 1778 ds->ds_ctl13 |= SM(AR_TXC13_BURST_DUR, dur); 1779 hwrate = athn_rates[protridx].hwrate; 1780 if (protridx == ATHN_RIDX_CCK2 && 1781 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1782 hwrate |= 0x04; 1783 ds->ds_ctl18 |= SM(AR_TXC18_RTSCTS_RATE, hwrate); 1784 } 1785 1786 ds->ds_ctl11 |= SM(AR_TXC11_FRAME_LEN, totlen); 1787 ds->ds_ctl19 = AR_TXC19_NOT_SOUNDING; 1788 1789 for (i = 0; i < bf->bf_map->dm_nsegs; i++) { 1790 ds->ds_segs[i].ds_data = bf->bf_map->dm_segs[i].ds_addr; 1791 ds->ds_segs[i].ds_ctl = SM(AR_TXC_BUF_LEN, 1792 bf->bf_map->dm_segs[i].ds_len); 1793 } 1794 /* Compute Tx descriptor checksum. */ 1795 sum = ds->ds_info + ds->ds_link; 1796 for (i = 0; i < 4; i++) { 1797 sum += ds->ds_segs[i].ds_data; 1798 sum += ds->ds_segs[i].ds_ctl; 1799 } 1800 sum = (sum >> 16) + (sum & 0xffff); 1801 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1802 1803 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1804 BUS_DMASYNC_PREWRITE); 1805 1806 DPRINTFN(DBG_TX, sc, 1807 "Tx qid=%d nsegs=%d ctl11=0x%x ctl12=0x%x ctl14=0x%x\n", 1808 qid, bf->bf_map->dm_nsegs, ds->ds_ctl11, ds->ds_ctl12, 1809 ds->ds_ctl14); 1810 1811 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 1812 SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list); 1813 1814 /* Queue buffer unless hardware FIFO is already full. */ 1815 if (++txq->queued <= AR9003_TX_QDEPTH) { 1816 AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr); 1817 AR_WRITE_BARRIER(sc); 1818 } 1819 else if (txq->wait == NULL) 1820 txq->wait = bf; 1821 return 0; 1822 } 1823 1824 Static void 1825 ar9003_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c) 1826 { 1827 uint32_t reg; 1828 1829 reg = IEEE80211_IS_CHAN_2GHZ(c) ? 1830 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 1831 if (IEEE80211_IS_CHAN_5GHZ(c) && 1832 (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 1833 reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE; 1834 } 1835 AR_WRITE(sc, AR_PHY_MODE, reg); 1836 AR_WRITE_BARRIER(sc); 1837 } 1838 1839 static __inline uint32_t 1840 ar9003_synth_delay(struct athn_softc *sc) 1841 { 1842 uint32_t delay; 1843 1844 delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY); 1845 if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B) 1846 delay = (delay * 4) / 22; 1847 else 1848 delay = delay / 10; /* in 100ns steps */ 1849 return delay; 1850 } 1851 1852 Static int 1853 ar9003_rf_bus_request(struct athn_softc *sc) 1854 { 1855 int ntries; 1856 1857 /* Request RF Bus grant. */ 1858 AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1859 for (ntries = 0; ntries < 10000; ntries++) { 1860 if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN) 1861 return 0; 1862 DELAY(10); 1863 } 1864 DPRINTFN(DBG_RF, sc, "could not kill baseband Rx"); 1865 return ETIMEDOUT; 1866 } 1867 1868 Static void 1869 ar9003_rf_bus_release(struct athn_softc *sc) 1870 { 1871 /* Wait for the synthesizer to settle. */ 1872 DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar9003_synth_delay(sc)); 1873 1874 /* Release the RF Bus grant. */ 1875 AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0); 1876 AR_WRITE_BARRIER(sc); 1877 } 1878 1879 Static void 1880 ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c, 1881 struct ieee80211_channel *extc) 1882 { 1883 uint32_t phy; 1884 1885 phy = AR_READ(sc, AR_PHY_GEN_CTRL); 1886 phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | 1887 AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH; 1888 #ifndef IEEE80211_NO_HT 1889 if (extc != NULL) { 1890 phy |= AR_PHY_GC_DYN2040_EN; 1891 if (extc > c) /* XXX */ 1892 phy |= AR_PHY_GC_DYN2040_PRI_CH; 1893 } 1894 #endif 1895 /* Turn off Green Field detection for now. */ 1896 phy &= ~AR_PHY_GC_GF_DETECT_EN; 1897 AR_WRITE(sc, AR_PHY_GEN_CTRL, phy); 1898 1899 AR_WRITE(sc, AR_2040_MODE, 1900 (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0); 1901 1902 /* Set global transmit timeout. */ 1903 AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25)); 1904 /* Set carrier sense timeout. */ 1905 AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15)); 1906 AR_WRITE_BARRIER(sc); 1907 } 1908 1909 Static void 1910 ar9003_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c, 1911 struct ieee80211_channel *extc) 1912 { 1913 uint32_t coeff, exp, man, reg; 1914 1915 /* Set Delta Slope (exponent and mantissa). */ 1916 coeff = (100 << 24) / c->ic_freq; 1917 athn_get_delta_slope(coeff, &exp, &man); 1918 DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man); 1919 1920 reg = AR_READ(sc, AR_PHY_TIMING3); 1921 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); 1922 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); 1923 AR_WRITE(sc, AR_PHY_TIMING3, reg); 1924 1925 /* For Short GI, coeff is 9/10 that of normal coeff. */ 1926 coeff = (9 * coeff) / 10; 1927 athn_get_delta_slope(coeff, &exp, &man); 1928 DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man); 1929 1930 reg = AR_READ(sc, AR_PHY_SGI_DELTA); 1931 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); 1932 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); 1933 AR_WRITE(sc, AR_PHY_SGI_DELTA, reg); 1934 AR_WRITE_BARRIER(sc); 1935 } 1936 1937 Static void 1938 ar9003_enable_antenna_diversity(struct athn_softc *sc) 1939 { 1940 AR_SETBITS(sc, AR_PHY_CCK_DETECT, 1941 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1942 AR_WRITE_BARRIER(sc); 1943 } 1944 1945 Static void 1946 ar9003_init_baseband(struct athn_softc *sc) 1947 { 1948 uint32_t synth_delay; 1949 1950 synth_delay = ar9003_synth_delay(sc); 1951 /* Activate the PHY (includes baseband activate and synthesizer on). */ 1952 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 1953 AR_WRITE_BARRIER(sc); 1954 DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay); 1955 } 1956 1957 Static void 1958 ar9003_disable_phy(struct athn_softc *sc) 1959 { 1960 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1961 AR_WRITE_BARRIER(sc); 1962 } 1963 1964 Static void 1965 ar9003_init_chains(struct athn_softc *sc) 1966 { 1967 if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5) 1968 AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 1969 1970 /* Setup chain masks. */ 1971 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); 1972 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); 1973 1974 if (sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) { 1975 /* 1976 * All self-generated frames are sent using two Tx chains 1977 * on these chips to not exceed PCIe power requirements. 1978 */ 1979 AR_WRITE(sc, AR_SELFGEN_MASK, 0x3); 1980 } 1981 else 1982 AR_WRITE(sc, AR_SELFGEN_MASK, sc->sc_txchainmask); 1983 AR_WRITE_BARRIER(sc); 1984 } 1985 1986 Static void 1987 ar9003_set_rxchains(struct athn_softc *sc) 1988 { 1989 if (sc->sc_rxchainmask == 0x3 || sc->sc_rxchainmask == 0x5) { 1990 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); 1991 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); 1992 AR_WRITE_BARRIER(sc); 1993 } 1994 } 1995 1996 #ifdef notused 1997 Static void 1998 ar9003_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 1999 { 2000 /* Sign-extends 9-bit value (assumes upper bits are zeroes). */ 2001 #define SIGN_EXT(v) (((v) ^ 0x100) - 0x100) 2002 uint32_t reg; 2003 int i; 2004 2005 for (i = 0; i < sc->sc_nrxchains; i++) { 2006 reg = AR_READ(sc, AR_PHY_CCA(i)); 2007 nf[i] = MS(reg, AR_PHY_MINCCA_PWR); 2008 nf[i] = SIGN_EXT(nf[i]); 2009 2010 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 2011 nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR); 2012 nf_ext[i] = SIGN_EXT(nf_ext[i]); 2013 } 2014 #undef SIGN_EXT 2015 } 2016 #endif /* notused */ 2017 2018 #ifdef notused 2019 Static void 2020 ar9003_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 2021 { 2022 uint32_t reg; 2023 int i; 2024 2025 for (i = 0; i < sc->sc_nrxchains; i++) { 2026 reg = AR_READ(sc, AR_PHY_CCA(i)); 2027 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); 2028 AR_WRITE(sc, AR_PHY_CCA(i), reg); 2029 2030 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 2031 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); 2032 AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg); 2033 } 2034 AR_WRITE_BARRIER(sc); 2035 } 2036 #endif /* notused */ 2037 2038 #ifdef notused 2039 Static void 2040 ar9003_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c) 2041 { 2042 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2043 int16_t cca_min, cca_max; 2044 int i; 2045 2046 if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 2047 /* Noisefloor calibration not finished. */ 2048 return; 2049 } 2050 /* Noisefloor calibration is finished. */ 2051 ar9003_read_noisefloor(sc, nf, nf_ext); 2052 2053 if (IEEE80211_IS_CHAN_2GHZ(c)) { 2054 cca_min = sc->sc_cca_min_2g; 2055 cca_max = sc->sc_cca_max_2g; 2056 } 2057 else { 2058 cca_min = sc->sc_cca_min_5g; 2059 cca_max = sc->sc_cca_max_5g; 2060 } 2061 /* Update noisefloor history. */ 2062 for (i = 0; i < sc->sc_nrxchains; i++) { 2063 if (nf[i] < cca_min) 2064 nf[i] = cca_min; 2065 else if (nf[i] > cca_max) 2066 nf[i] = cca_max; 2067 if (nf_ext[i] < cca_min) 2068 nf_ext[i] = cca_min; 2069 else if (nf_ext[i] > cca_max) 2070 nf_ext[i] = cca_max; 2071 2072 sc->sc_nf_hist[sc->sc_nf_hist_cur].nf[i] = nf[i]; 2073 sc->sc_nf_hist[sc->sc_nf_hist_cur].nf_ext[i] = nf_ext[i]; 2074 } 2075 if (++sc->sc_nf_hist_cur >= ATHN_NF_CAL_HIST_MAX) 2076 sc->sc_nf_hist_cur = 0; 2077 } 2078 #endif /* notused */ 2079 2080 #ifdef notused 2081 Static void 2082 ar9003_bb_load_noisefloor(struct athn_softc *sc) 2083 { 2084 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2085 int i, ntries; 2086 2087 /* Write filtered noisefloor values. */ 2088 for (i = 0; i < sc->sc_nrxchains; i++) { 2089 nf[i] = sc->sc_nf_priv[i] * 2; 2090 nf_ext[i] = sc->sc_nf_ext_priv[i] * 2; 2091 } 2092 ar9003_write_noisefloor(sc, nf, nf_ext); 2093 2094 /* Load filtered noisefloor values into baseband. */ 2095 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2096 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2097 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2098 /* Wait for load to complete. */ 2099 for (ntries = 0; ntries < 1000; ntries++) { 2100 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) 2101 break; 2102 DELAY(10); 2103 } 2104 if (ntries == 1000) { 2105 DPRINTFN(DBG_RF, sc, "failed to load noisefloor values\n"); 2106 return; 2107 } 2108 2109 /* Restore noisefloor values to initial (max) values. */ 2110 for (i = 0; i < AR_MAX_CHAINS; i++) 2111 nf[i] = nf_ext[i] = -50 * 2; 2112 ar9003_write_noisefloor(sc, nf, nf_ext); 2113 } 2114 #endif /* notused */ 2115 2116 #ifdef notused 2117 Static void 2118 ar9300_noisefloor_calib(struct athn_softc *sc) 2119 { 2120 2121 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2122 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2123 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2124 } 2125 #endif /* notused */ 2126 2127 Static void 2128 ar9003_do_noisefloor_calib(struct athn_softc *sc) 2129 { 2130 2131 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2132 } 2133 2134 PUBLIC int 2135 ar9003_init_calib(struct athn_softc *sc) 2136 { 2137 uint8_t txchainmask, rxchainmask; 2138 uint32_t reg; 2139 int ntries; 2140 2141 /* Save chains masks. */ 2142 txchainmask = sc->sc_txchainmask; 2143 rxchainmask = sc->sc_rxchainmask; 2144 /* Configure hardware before calibration. */ 2145 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE) 2146 txchainmask = rxchainmask = 0x3; 2147 else 2148 txchainmask = rxchainmask = 0x7; 2149 ar9003_init_chains(sc); 2150 2151 /* Perform Tx IQ calibration. */ 2152 ar9003_calib_tx_iq(sc); 2153 /* Disable and re-enable the PHY chips. */ 2154 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2155 AR_WRITE_BARRIER(sc); 2156 DELAY(5); 2157 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 2158 2159 /* Calibrate the AGC. */ 2160 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 2161 /* Poll for offset calibration completion. */ 2162 for (ntries = 0; ntries < 10000; ntries++) { 2163 reg = AR_READ(sc, AR_PHY_AGC_CONTROL); 2164 if (!(reg & AR_PHY_AGC_CONTROL_CAL)) 2165 break; 2166 DELAY(10); 2167 } 2168 if (ntries == 10000) 2169 return ETIMEDOUT; 2170 2171 /* Restore chains masks. */ 2172 sc->sc_txchainmask = txchainmask; 2173 sc->sc_rxchainmask = rxchainmask; 2174 ar9003_init_chains(sc); 2175 2176 return 0; 2177 } 2178 2179 Static void 2180 ar9003_do_calib(struct athn_softc *sc) 2181 { 2182 uint32_t reg; 2183 2184 if (sc->sc_cur_calib_mask & ATHN_CAL_IQ) { 2185 reg = AR_READ(sc, AR_PHY_TIMING4); 2186 reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10); 2187 AR_WRITE(sc, AR_PHY_TIMING4, reg); 2188 AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 2189 AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); 2190 AR_WRITE_BARRIER(sc); 2191 } 2192 else if (sc->sc_cur_calib_mask & ATHN_CAL_TEMP) { 2193 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2194 AR_PHY_65NM_CH0_THERM_LOCAL); 2195 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2196 AR_PHY_65NM_CH0_THERM_START); 2197 AR_WRITE_BARRIER(sc); 2198 } 2199 } 2200 2201 Static void 2202 ar9003_next_calib(struct athn_softc *sc) 2203 { 2204 /* Check if we have any calibration in progress. */ 2205 if (sc->sc_cur_calib_mask != 0) { 2206 if (!(AR_READ(sc, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { 2207 /* Calibration completed for current sample. */ 2208 ar9003_calib_iq(sc); 2209 } 2210 } 2211 } 2212 2213 Static void 2214 ar9003_calib_iq(struct athn_softc *sc) 2215 { 2216 struct athn_iq_cal *cal; 2217 uint32_t reg, i_coff_denom, q_coff_denom; 2218 int32_t i_coff, q_coff; 2219 int i, iq_corr_neg; 2220 2221 for (i = 0; i < AR_MAX_CHAINS; i++) { 2222 cal = &sc->sc_calib.iq[i]; 2223 2224 /* Read IQ calibration measures (clear on read). */ 2225 cal->pwr_meas_i = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_0_B(i)); 2226 cal->pwr_meas_q = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_1_B(i)); 2227 cal->iq_corr_meas = 2228 (int32_t)AR_READ(sc, AR_PHY_IQ_ADC_MEAS_2_B(i)); 2229 } 2230 2231 for (i = 0; i < sc->sc_nrxchains; i++) { 2232 cal = &sc->sc_calib.iq[i]; 2233 2234 if (cal->pwr_meas_q == 0) 2235 continue; 2236 2237 if ((iq_corr_neg = cal->iq_corr_meas < 0)) 2238 cal->iq_corr_meas = -cal->iq_corr_meas; 2239 2240 i_coff_denom = 2241 (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 256; 2242 q_coff_denom = cal->pwr_meas_q / 64; 2243 2244 if (i_coff_denom == 0 || q_coff_denom == 0) 2245 continue; /* Prevents division by zero. */ 2246 2247 i_coff = cal->iq_corr_meas / i_coff_denom; 2248 q_coff = (cal->pwr_meas_i / q_coff_denom) - 64; 2249 2250 if (i_coff > 63) 2251 i_coff = 63; 2252 else if (i_coff < -63) 2253 i_coff = -63; 2254 /* Negate i_coff if iq_corr_meas is positive. */ 2255 if (!iq_corr_neg) 2256 i_coff = -i_coff; 2257 if (q_coff > 63) 2258 q_coff = 63; 2259 else if (q_coff < -63) 2260 q_coff = -63; 2261 2262 DPRINTFN(DBG_RF, sc, "IQ calibration for chain %d\n", i); 2263 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2264 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff); 2265 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff); 2266 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2267 } 2268 2269 /* Apply new settings. */ 2270 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2271 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); 2272 AR_WRITE_BARRIER(sc); 2273 2274 /* IQ calibration done. */ 2275 sc->sc_cur_calib_mask &= ~ATHN_CAL_IQ; 2276 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2277 } 2278 2279 #define DELPT 32 2280 Static int 2281 ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2]) 2282 { 2283 /* Sign-extends 12-bit value (assumes upper bits are zeroes). */ 2284 #define SIGN_EXT(v) (((v) ^ 0x800) - 0x800) 2285 #define SCALE (1 << 15) 2286 #define SHIFT (1 << 8) 2287 struct { 2288 int32_t m, p, c; 2289 } val[2][2]; 2290 int32_t mag[2][2], phs[2][2], cos[2], sin[2]; 2291 int32_t div, f1, f2, f3, m, p, c; 2292 int32_t txmag, txphs, rxmag, rxphs; 2293 int32_t q_coff, i_coff; 2294 int i, j; 2295 2296 /* Extract our twelve signed 12-bit values from res[] array. */ 2297 val[0][0].m = res[0] & 0xfff; 2298 val[0][0].p = (res[0] >> 12) & 0xfff; 2299 val[0][0].c = ((res[0] >> 24) & 0xff) | (res[1] & 0xf) << 8; 2300 2301 val[0][1].m = (res[1] >> 4) & 0xfff; 2302 val[0][1].p = res[2] & 0xfff; 2303 val[0][1].c = (res[2] >> 12) & 0xfff; 2304 2305 val[1][0].m = ((res[2] >> 24) & 0xff) | (res[3] & 0xf) << 8; 2306 val[1][0].p = (res[3] >> 4) & 0xfff; 2307 val[1][0].c = res[4] & 0xfff; 2308 2309 val[1][1].m = (res[4] >> 12) & 0xfff; 2310 val[1][1].p = ((res[4] >> 24) & 0xff) | (res[5] & 0xf) << 8; 2311 val[1][1].c = (res[5] >> 4) & 0xfff; 2312 2313 for (i = 0; i < 2; i++) { 2314 int32_t ymin, ymax; 2315 for (j = 0; j < 2; j++) { 2316 m = SIGN_EXT(val[i][j].m); 2317 p = SIGN_EXT(val[i][j].p); 2318 c = SIGN_EXT(val[i][j].c); 2319 2320 if (p == 0) 2321 return 1; /* Prevent division by 0. */ 2322 2323 mag[i][j] = (m * SCALE) / p; 2324 phs[i][j] = (c * SCALE) / p; 2325 } 2326 sin[i] = ((mag[i][0] - mag[i][1]) * SHIFT) / DELPT; 2327 cos[i] = ((phs[i][0] - phs[i][1]) * SHIFT) / DELPT; 2328 /* Find magnitude by approximation. */ 2329 ymin = MIN(abs(sin[i]), abs(cos[i])); 2330 ymax = MAX(abs(sin[i]), abs(cos[i])); 2331 div = ymax - (ymax / 32) + (ymin / 8) + (ymin / 4); 2332 if (div == 0) 2333 return 1; /* Prevent division by 0. */ 2334 /* Normalize sin and cos by magnitude. */ 2335 sin[i] = (sin[i] * SCALE) / div; 2336 cos[i] = (cos[i] * SCALE) / div; 2337 } 2338 2339 /* Compute IQ mismatch (solve 4x4 linear equation). */ 2340 f1 = cos[0] - cos[1]; 2341 f3 = sin[0] - sin[1]; 2342 f2 = (f1 * f1 + f3 * f3) / SCALE; 2343 if (f2 == 0) 2344 return 1; /* Prevent division by 0. */ 2345 2346 /* Compute Tx magnitude mismatch. */ 2347 txmag = (f1 * ( mag[0][0] - mag[1][0]) + 2348 f3 * ( phs[0][0] - phs[1][0])) / f2; 2349 /* Compute Tx phase mismatch. */ 2350 txphs = (f3 * (-mag[0][0] + mag[1][0]) + 2351 f1 * ( phs[0][0] - phs[1][0])) / f2; 2352 2353 if (txmag == SCALE) 2354 return 1; /* Prevent division by 0. */ 2355 2356 /* Compute Rx magnitude mismatch. */ 2357 rxmag = mag[0][0] - (cos[0] * txmag + sin[0] * txphs) / SCALE; 2358 /* Compute Rx phase mismatch. */ 2359 rxphs = phs[0][0] + (sin[0] * txmag - cos[0] * txphs) / SCALE; 2360 2361 if (-rxmag == SCALE) 2362 return 1; /* Prevent division by 0. */ 2363 2364 txmag = (txmag * SCALE) / (SCALE - txmag); 2365 txphs = -txphs; 2366 2367 q_coff = (txmag * 128) / SCALE; 2368 if (q_coff < -63) 2369 q_coff = -63; 2370 else if (q_coff > 63) 2371 q_coff = 63; 2372 i_coff = (txphs * 256) / SCALE; 2373 if (i_coff < -63) 2374 i_coff = -63; 2375 else if (i_coff > 63) 2376 i_coff = 63; 2377 coeff[0] = q_coff * 128 + i_coff; 2378 2379 rxmag = (-rxmag * SCALE) / (SCALE + rxmag); 2380 rxphs = -rxphs; 2381 2382 q_coff = (rxmag * 128) / SCALE; 2383 if (q_coff < -63) 2384 q_coff = -63; 2385 else if (q_coff > 63) 2386 q_coff = 63; 2387 i_coff = (rxphs * 256) / SCALE; 2388 if (i_coff < -63) 2389 i_coff = -63; 2390 else if (i_coff > 63) 2391 i_coff = 63; 2392 coeff[1] = q_coff * 128 + i_coff; 2393 2394 return 0; 2395 #undef SHIFT 2396 #undef SCALE 2397 #undef SIGN_EXT 2398 } 2399 2400 Static int 2401 ar9003_calib_tx_iq(struct athn_softc *sc) 2402 { 2403 uint32_t reg; 2404 int32_t res[6], coeff[2]; 2405 int i, j, ntries; 2406 2407 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1); 2408 reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT); 2409 AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg); 2410 2411 /* Start Tx IQ calibration. */ 2412 AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL); 2413 /* Wait for completion. */ 2414 for (ntries = 0; ntries < 10000; ntries++) { 2415 reg = AR_READ(sc, AR_PHY_TX_IQCAL_START); 2416 if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL)) 2417 break; 2418 DELAY(10); 2419 } 2420 if (ntries == 10000) 2421 return ETIMEDOUT; 2422 2423 for (i = 0; i < sc->sc_ntxchains; i++) { 2424 /* Read Tx IQ calibration status for this chain. */ 2425 reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i)); 2426 if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED) 2427 return EIO; 2428 /* 2429 * Read Tx IQ calibration results for this chain. 2430 * This consists in twelve signed 12-bit values. 2431 */ 2432 for (j = 0; j < 3; j++) { 2433 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2434 AR_PHY_CHAN_INFO_TAB_S2_READ); 2435 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2436 res[j * 2 + 0] = reg; 2437 2438 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2439 AR_PHY_CHAN_INFO_TAB_S2_READ); 2440 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2441 res[j * 2 + 1] = reg & 0xffff; 2442 } 2443 2444 /* Compute Tx IQ correction. */ 2445 if (ar9003_get_iq_corr(sc, res, coeff) != 0) 2446 return EIO; 2447 2448 /* Write Tx IQ correction coefficients. */ 2449 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)); 2450 reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, 2451 coeff[0]); 2452 AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg); 2453 2454 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2455 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF, 2456 coeff[1] >> 7); 2457 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF, 2458 coeff[1]); 2459 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2460 AR_WRITE_BARRIER(sc); 2461 } 2462 2463 /* Enable Tx IQ correction. */ 2464 AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_3, 2465 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN); 2466 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2467 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN); 2468 AR_WRITE_BARRIER(sc); 2469 return 0; 2470 } 2471 #undef DELPT 2472 2473 /*- 2474 * The power amplifier predistortion state machine works as follows: 2475 * 1) Disable digital predistorters for all Tx chains 2476 * 2) Repeat steps 3~7 for all Tx chains 2477 * 3) Force Tx gain to that of training signal 2478 * 4) Send training signal (asynchronous) 2479 * 5) Wait for training signal to complete (asynchronous) 2480 * 6) Read PA measurements (input power, output power, output phase) 2481 * 7) Compute the predistortion function that linearizes PA output 2482 * 8) Write predistortion functions to hardware tables for all Tx chains 2483 * 9) Enable digital predistorters for all Tx chains 2484 */ 2485 #ifdef notused 2486 Static void 2487 ar9003_paprd_calib(struct athn_softc *sc, struct ieee80211_channel *c) 2488 { 2489 static const int scaling[] = { 2490 261376, 248079, 233759, 220464, 2491 208194, 196949, 185706, 175487 2492 }; 2493 struct athn_ops *ops = &sc->sc_ops; 2494 uint32_t reg, ht20mask, ht40mask; 2495 int i; 2496 2497 /* Read PA predistortion masks from ROM. */ 2498 ops->get_paprd_masks(sc, c, &ht20mask, &ht40mask); 2499 2500 /* AM-to-AM: amplifier's amplitude characteristic. */ 2501 reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM); 2502 reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask); 2503 AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg); 2504 2505 /* AM-to-PM: amplifier's phase transfer characteristic. */ 2506 reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM); 2507 reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask); 2508 AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg); 2509 2510 reg = AR_READ(sc, AR_PHY_PAPRD_HT40); 2511 reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask); 2512 AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg); 2513 2514 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2515 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2516 AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE); 2517 2518 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i)); 2519 reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181); 2520 reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361); 2521 reg &= ~AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA; 2522 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA; 2523 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA; 2524 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg); 2525 2526 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i)); 2527 reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3); 2528 AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg); 2529 } 2530 2531 /* Disable all digital predistorters during calibration. */ 2532 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2533 AR_CLRBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2534 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 2535 } 2536 AR_WRITE_BARRIER(sc); 2537 2538 /* 2539 * Configure training signal. 2540 */ 2541 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1); 2542 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28); 2543 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30); 2544 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE; 2545 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE; 2546 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE; 2547 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE; 2548 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE; 2549 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg); 2550 2551 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL2, 147); 2552 2553 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3); 2554 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4); 2555 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4); 2556 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7); 2557 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1); 2558 if (AR_SREV_9485(sc)) 2559 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3); 2560 else 2561 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6); 2562 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15); 2563 reg |= AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE; 2564 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg); 2565 2566 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4); 2567 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0); 2568 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400); 2569 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100); 2570 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg); 2571 2572 for (i = 0; i < __arraycount(scaling); i++) { 2573 reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i)); 2574 reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]); 2575 AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg); 2576 } 2577 2578 /* Save Tx gain table. */ 2579 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE; i++) 2580 sc->sc_txgain[i] = AR_READ(sc, AR_PHY_TXGAIN_TABLE(i)); 2581 2582 /* Set Tx power of training signal (use setting for MCS0). */ 2583 sc->sc_trainpow = MS(AR_READ(sc, AR_PHY_PWRTX_RATE5), 2584 AR_PHY_PWRTX_RATE5_POWERTXHT20_0) - 4; 2585 2586 /* 2587 * Start PA predistortion calibration state machine. 2588 */ 2589 /* Find first available Tx chain. */ 2590 sc->sc_paprd_curchain = 0; 2591 while (!(sc->sc_txchainmask & (1 << sc->sc_paprd_curchain))) 2592 sc->sc_paprd_curchain++; 2593 2594 /* Make sure training done bit is clear. */ 2595 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 2596 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 2597 AR_WRITE_BARRIER(sc); 2598 2599 /* Transmit training signal. */ 2600 ar9003_paprd_tx_tone(sc); 2601 } 2602 #endif /* notused */ 2603 2604 Static int 2605 ar9003_get_desired_txgain(struct athn_softc *sc, int chain, int pow) 2606 { 2607 int32_t scale, atemp, avolt, tempcal, voltcal, temp, volt; 2608 int32_t tempcorr, voltcorr; 2609 uint32_t reg; 2610 int8_t delta; 2611 2612 scale = MS(AR_READ(sc, AR_PHY_TPC_12), 2613 AR_PHY_TPC_12_DESIRED_SCALE_HT40_5); 2614 2615 reg = AR_READ(sc, AR_PHY_TPC_19); 2616 atemp = MS(reg, AR_PHY_TPC_19_ALPHA_THERM); 2617 avolt = MS(reg, AR_PHY_TPC_19_ALPHA_VOLT); 2618 2619 reg = AR_READ(sc, AR_PHY_TPC_18); 2620 tempcal = MS(reg, AR_PHY_TPC_18_THERM_CAL); 2621 voltcal = MS(reg, AR_PHY_TPC_18_VOLT_CAL); 2622 2623 reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4); 2624 temp = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_THERM); 2625 volt = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_VOLT); 2626 2627 delta = (int8_t)MS(AR_READ(sc, AR_PHY_TPC_11_B(chain)), 2628 AR_PHY_TPC_11_OLPC_GAIN_DELTA); 2629 2630 /* Compute temperature and voltage correction. */ 2631 tempcorr = (atemp * (temp - tempcal) + 128) / 256; 2632 voltcorr = (avolt * (volt - voltcal) + 64) / 128; 2633 2634 /* Compute desired Tx gain. */ 2635 return pow - delta - tempcorr - voltcorr + scale; 2636 } 2637 2638 Static void 2639 ar9003_force_txgain(struct athn_softc *sc, uint32_t txgain) 2640 { 2641 uint32_t reg; 2642 2643 reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN); 2644 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN, 2645 MS(txgain, AR_PHY_TXGAIN_TXBB1DBGAIN)); 2646 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN, 2647 MS(txgain, AR_PHY_TXGAIN_TXBB6DBGAIN)); 2648 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN, 2649 MS(txgain, AR_PHY_TXGAIN_TXMXRGAIN)); 2650 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA, 2651 MS(txgain, AR_PHY_TXGAIN_PADRVGNA)); 2652 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB, 2653 MS(txgain, AR_PHY_TXGAIN_PADRVGNB)); 2654 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC, 2655 MS(txgain, AR_PHY_TXGAIN_PADRVGNC)); 2656 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND, 2657 MS(txgain, AR_PHY_TXGAIN_PADRVGND)); 2658 reg &= ~AR_PHY_TX_FORCED_GAIN_ENABLE_PAL; 2659 reg &= ~AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN; 2660 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg); 2661 2662 reg = AR_READ(sc, AR_PHY_TPC_1); 2663 reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0); 2664 reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN; 2665 AR_WRITE(sc, AR_PHY_TPC_1, reg); 2666 AR_WRITE_BARRIER(sc); 2667 } 2668 2669 Static void 2670 ar9003_set_training_gain(struct athn_softc *sc, int chain) 2671 { 2672 size_t i; 2673 int gain; 2674 2675 /* 2676 * Get desired gain for training signal power (take into account 2677 * current temperature/voltage). 2678 */ 2679 gain = ar9003_get_desired_txgain(sc, chain, sc->sc_trainpow); 2680 /* Find entry in table. */ 2681 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE - 1; i++) 2682 if ((int)MS(sc->sc_txgain[i], AR_PHY_TXGAIN_INDEX) >= gain) 2683 break; 2684 ar9003_force_txgain(sc, sc->sc_txgain[i]); 2685 } 2686 2687 Static int 2688 ar9003_paprd_tx_tone(struct athn_softc *sc) 2689 { 2690 #define TONE_LEN 1800 2691 struct ieee80211com *ic = &sc->sc_ic; 2692 struct ieee80211_frame *wh; 2693 struct ieee80211_node *ni; 2694 struct mbuf *m; 2695 int error; 2696 2697 /* Build a Null (no data) frame of TONE_LEN bytes. */ 2698 m = MCLGETI(NULL, M_DONTWAIT, NULL, TONE_LEN); 2699 if (m == NULL) 2700 return ENOBUFS; 2701 memset(mtod(m, void *), 0, TONE_LEN); 2702 wh = mtod(m, struct ieee80211_frame *); 2703 wh->i_fc[0] = IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_NODATA; 2704 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 2705 *(uint16_t *)wh->i_dur = htole16(10); /* XXX */ 2706 IEEE80211_ADDR_COPY(wh->i_addr1, ic->ic_myaddr); 2707 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 2708 IEEE80211_ADDR_COPY(wh->i_addr3, ic->ic_myaddr); 2709 m->m_pkthdr.len = m->m_len = TONE_LEN; 2710 2711 /* Set gain of training signal. */ 2712 ar9003_set_training_gain(sc, sc->sc_paprd_curchain); 2713 2714 /* Transmit training signal. */ 2715 ni = ieee80211_ref_node(ic->ic_bss); 2716 if ((error = ar9003_tx(sc, m, ni, ATHN_TXFLAG_PAPRD)) != 0) 2717 ieee80211_free_node(ni); 2718 return error; 2719 #undef TONE_LEN 2720 } 2721 2722 static __inline int 2723 get_scale(int val) 2724 { 2725 int log = 0; 2726 2727 /* Find the log base 2 (position of highest bit set). */ 2728 while (val >>= 1) 2729 log++; 2730 2731 return (log > 10) ? log - 10 : 0; 2732 } 2733 2734 /* 2735 * Compute predistortion function to linearize power amplifier output based 2736 * on feedback from training signal. 2737 */ 2738 Static int 2739 ar9003_compute_predistortion(struct athn_softc *sc, const uint32_t *lo, 2740 const uint32_t *hi) 2741 { 2742 #define NBINS 23 2743 int chain = sc->sc_paprd_curchain; 2744 int x[NBINS + 1], y[NBINS + 1], t[NBINS + 1]; 2745 int b1[NBINS + 1], b2[NBINS + 1], xtilde[NBINS + 1]; 2746 int nsamples, txsum, rxsum, rosum, maxidx; 2747 int order, order5x, order5xrem, order3x, order3xrem, y5, y3; 2748 int icept, G, I, L, M, angle, xnonlin, y2, y4, sumy2, sumy4; 2749 int alpha, beta, scale, Qalpha, Qbeta, Qscale, Qx, Qb1, Qb2; 2750 int tavg, ttilde, maxb1abs, maxb2abs, maxxtildeabs, in; 2751 int tmp, i; 2752 2753 /* Set values at origin. */ 2754 x[0] = y[0] = t[0] = 0; 2755 2756 #define SCALE 32 2757 maxidx = 0; 2758 for (i = 0; i < NBINS; i++) { 2759 nsamples = lo[i] & 0xffff; 2760 /* Skip bins that contain 16 or less samples. */ 2761 if (nsamples <= 16) { 2762 x[i + 1] = y[i + 1] = t[i + 1] = 0; 2763 continue; 2764 } 2765 txsum = (hi[i] & 0x7ff) << 16 | lo[i] >> 16; 2766 rxsum = (lo[i + NBINS] & 0xffff) << 5 | 2767 ((hi[i] >> 11) & 0x1f); 2768 rosum = (hi[i + NBINS] & 0x7ff) << 16 | hi[i + NBINS] >> 16; 2769 /* Sign-extend 27-bit value. */ 2770 rosum = (rosum ^ 0x4000000) - 0x4000000; 2771 2772 txsum *= SCALE; 2773 rxsum *= SCALE; 2774 rosum *= SCALE; 2775 2776 x[i + 1] = ((txsum + nsamples) / nsamples + SCALE) / SCALE; 2777 y[i + 1] = ((rxsum + nsamples) / nsamples + SCALE) / SCALE + 2778 SCALE * maxidx + SCALE / 2; 2779 t[i + 1] = (rosum + nsamples) / nsamples; 2780 maxidx++; 2781 } 2782 #undef SCALE 2783 2784 #define SCALE_LOG 8 2785 #define SCALE (1 << SCALE_LOG) 2786 if (x[6] == x[3]) 2787 return 1; /* Prevent division by 0. */ 2788 G = ((y[6] - y[3]) * SCALE + (x[6] - x[3])) / (x[6] - x[3]); 2789 if (G == 0) 2790 return 1; /* Prevent division by 0. */ 2791 2792 sc->sc_gain1[chain] = G; /* Save low signal gain. */ 2793 2794 /* Find interception point. */ 2795 icept = (G * (x[0] - x[3]) + SCALE) / SCALE + y[3]; 2796 for (i = 0; i <= 3; i++) { 2797 y[i] = i * 32; 2798 x[i] = (y[i] * SCALE + G) / G; 2799 } 2800 for (i = 4; i <= maxidx; i++) 2801 y[i] -= icept; 2802 2803 xnonlin = x[maxidx] - (y[maxidx] * SCALE + G) / G; 2804 order = (xnonlin + y[maxidx]) / y[maxidx]; 2805 if (order == 0) 2806 M = 10; 2807 else if (order == 1) 2808 M = 9; 2809 else 2810 M = 8; 2811 2812 I = (maxidx >= 16) ? 7 : maxidx / 2; 2813 L = maxidx - I; 2814 2815 sumy2 = sumy4 = y2 = y4 = 0; 2816 for (i = 0; i <= L; i++) { 2817 if (y[i + I] == 0) 2818 return 1; /* Prevent division by 0. */ 2819 2820 xnonlin = x[i + I] - ((y[i + I] * SCALE) + G) / G; 2821 xtilde[i] = ((xnonlin << M) + y[i + I]) / y[i + I]; 2822 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2823 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2824 2825 y2 = (y[i + I] * y[i + I] + SCALE * SCALE) / (SCALE * SCALE); 2826 2827 sumy2 += y2; 2828 sumy4 += y2 * y2; 2829 2830 b1[i] = y2 * (L + 1); 2831 b2[i] = y2; 2832 } 2833 for (i = 0; i <= L; i++) { 2834 b1[i] -= sumy2; 2835 b2[i] = sumy4 - sumy2 * b2[i]; 2836 } 2837 2838 maxxtildeabs = maxb1abs = maxb2abs = 0; 2839 for (i = 0; i <= L; i++) { 2840 tmp = abs(xtilde[i]); 2841 if (tmp > maxxtildeabs) 2842 maxxtildeabs = tmp; 2843 2844 tmp = abs(b1[i]); 2845 if (tmp > maxb1abs) 2846 maxb1abs = tmp; 2847 2848 tmp = abs(b2[i]); 2849 if (tmp > maxb2abs) 2850 maxb2abs = tmp; 2851 } 2852 Qx = get_scale(maxxtildeabs); 2853 Qb1 = get_scale(maxb1abs); 2854 Qb2 = get_scale(maxb2abs); 2855 for (i = 0; i <= L; i++) { 2856 xtilde[i] /= 1 << Qx; 2857 b1[i] /= 1 << Qb1; 2858 b2[i] /= 1 << Qb2; 2859 } 2860 2861 alpha = beta = 0; 2862 for (i = 0; i <= L; i++) { 2863 alpha += b1[i] * xtilde[i]; 2864 beta += b2[i] * xtilde[i]; 2865 } 2866 2867 scale = ((y4 / SCALE_LOG) * (L + 1) - 2868 (y2 / SCALE_LOG) * sumy2) * SCALE_LOG; 2869 2870 Qscale = get_scale(abs(scale)); 2871 scale /= 1 << Qscale; 2872 Qalpha = get_scale(abs(alpha)); 2873 alpha /= 1 << Qalpha; 2874 Qbeta = get_scale(abs(beta)); 2875 beta /= 1 << Qbeta; 2876 2877 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale; 2878 order5x = 1 << (order / 5); 2879 order5xrem = 1 << (order % 5); 2880 2881 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale; 2882 order3x = 1 << (order / 3); 2883 order3xrem = 1 << (order % 3); 2884 2885 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2886 tmp = i * 32; 2887 2888 /* Fifth order. */ 2889 y5 = ((beta * tmp) / 64) / order5x; 2890 y5 = (y5 * tmp) / order5x; 2891 y5 = (y5 * tmp) / order5x; 2892 y5 = (y5 * tmp) / order5x; 2893 y5 = (y5 * tmp) / order5x; 2894 y5 = y5 / order5xrem; 2895 2896 /* Third oder. */ 2897 y3 = (alpha * tmp) / order3x; 2898 y3 = (y3 * tmp) / order3x; 2899 y3 = (y3 * tmp) / order3x; 2900 y3 = y3 / order3xrem; 2901 2902 in = y5 + y3 + (SCALE * tmp) / G; 2903 if (i >= 2 && in < sc->sc_pa_in[chain][i - 1]) { 2904 in = sc->sc_pa_in[chain][i - 1] + 2905 (sc->sc_pa_in[chain][i - 1] - 2906 sc->sc_pa_in[chain][i - 2]); 2907 } 2908 if (in > 1400) 2909 in = 1400; 2910 sc->sc_pa_in[chain][i] = in; 2911 } 2912 2913 /* Compute average theta of first 5 bins (linear region). */ 2914 tavg = 0; 2915 for (i = 1; i <= 5; i++) 2916 tavg += t[i]; 2917 tavg /= 5; 2918 for (i = 1; i <= 5; i++) 2919 t[i] = 0; 2920 for (i = 6; i <= maxidx; i++) 2921 t[i] -= tavg; 2922 2923 alpha = beta = 0; 2924 for (i = 0; i <= L; i++) { 2925 ttilde = ((t[i + I] << M) + y[i + I]) / y[i + I]; 2926 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2927 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2928 2929 alpha += b2[i] * ttilde; 2930 beta += b1[i] * ttilde; 2931 } 2932 2933 Qalpha = get_scale(abs(alpha)); 2934 alpha /= 1 << Qalpha; 2935 Qbeta = get_scale(abs(beta)); 2936 beta /= 1 << Qbeta; 2937 2938 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale + 5; 2939 order5x = 1 << (order / 5); 2940 order5xrem = 1 << (order % 5); 2941 2942 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale + 5; 2943 order3x = 1 << (order / 3); 2944 order3xrem = 1 << (order % 3); 2945 2946 for (i = 0; i <= 4; i++) 2947 sc->sc_angle[chain][i] = 0; /* Linear at that range. */ 2948 for (i = 5; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2949 tmp = i * 32; 2950 2951 /* Fifth order. */ 2952 if (beta > 0) 2953 y5 = (((beta * tmp - 64) / 64) - order5x) / order5x; 2954 else 2955 y5 = (((beta * tmp - 64) / 64) + order5x) / order5x; 2956 y5 = (y5 * tmp) / order5x; 2957 y5 = (y5 * tmp) / order5x; 2958 y5 = (y5 * tmp) / order5x; 2959 y5 = (y5 * tmp) / order5x; 2960 y5 = y5 / order5xrem; 2961 2962 /* Third oder. */ 2963 if (beta > 0) /* XXX alpha? */ 2964 y3 = (alpha * tmp - order3x) / order3x; 2965 else 2966 y3 = (alpha * tmp + order3x) / order3x; 2967 y3 = (y3 * tmp) / order3x; 2968 y3 = (y3 * tmp) / order3x; 2969 y3 = y3 / order3xrem; 2970 2971 angle = y5 + y3; 2972 if (angle < -150) 2973 angle = -150; 2974 else if (angle > 150) 2975 angle = 150; 2976 sc->sc_angle[chain][i] = angle; 2977 } 2978 /* Angle for entry 4 is derived from angle for entry 5. */ 2979 sc->sc_angle[chain][4] = (sc->sc_angle[chain][5] + 2) / 2; 2980 2981 return 0; 2982 #undef SCALE 2983 #undef SCALE_LOG 2984 #undef NBINS 2985 } 2986 2987 Static void 2988 ar9003_enable_predistorter(struct athn_softc *sc, int chain) 2989 { 2990 uint32_t reg; 2991 int i; 2992 2993 /* Write digital predistorter lookup table. */ 2994 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2995 AR_WRITE(sc, AR_PHY_PAPRD_MEM_TAB_B(chain, i), 2996 SM(AR_PHY_PAPRD_PA_IN, sc->sc_pa_in[chain][i]) | 2997 SM(AR_PHY_PAPRD_ANGLE, sc->sc_angle[chain][i])); 2998 } 2999 3000 reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain)); 3001 reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->sc_gain1[chain]); 3002 AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg); 3003 3004 /* Indicate Tx power used for calibration (training signal). */ 3005 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain)); 3006 reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->sc_trainpow); 3007 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg); 3008 3009 /* Enable digital predistorter for this chain. */ 3010 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(chain), 3011 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 3012 AR_WRITE_BARRIER(sc); 3013 } 3014 3015 Static void 3016 ar9003_paprd_enable(struct athn_softc *sc) 3017 { 3018 int i; 3019 3020 /* Enable digital predistorters for all Tx chains. */ 3021 for (i = 0; i < AR9003_MAX_CHAINS; i++) 3022 if (sc->sc_txchainmask & (1 << i)) 3023 ar9003_enable_predistorter(sc, i); 3024 } 3025 3026 /* 3027 * This function is called when our training signal has been sent. 3028 */ 3029 Static void 3030 ar9003_paprd_tx_tone_done(struct athn_softc *sc) 3031 { 3032 uint32_t lo[48], hi[48]; 3033 size_t i; 3034 3035 /* Make sure training is complete. */ 3036 if (!(AR_READ(sc, AR_PHY_PAPRD_TRAINER_STAT1) & 3037 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE)) 3038 return; 3039 3040 /* Read feedback from training signal. */ 3041 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 3042 for (i = 0; i < __arraycount(lo); i++) 3043 lo[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 3044 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 3045 for (i = 0; i < __arraycount(hi); i++) 3046 hi[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 3047 3048 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 3049 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 3050 3051 /* Compute predistortion function based on this feedback. */ 3052 if (ar9003_compute_predistortion(sc, lo, hi) != 0) 3053 return; 3054 3055 /* Get next available Tx chain. */ 3056 while (++sc->sc_paprd_curchain < AR9003_MAX_CHAINS) 3057 if (sc->sc_txchainmask & (1 << sc->sc_paprd_curchain)) 3058 break; 3059 if (sc->sc_paprd_curchain == AR9003_MAX_CHAINS) { 3060 /* All Tx chains measured; enable digital predistortion. */ 3061 ar9003_paprd_enable(sc); 3062 } 3063 else /* Measure next Tx chain. */ 3064 ar9003_paprd_tx_tone(sc); 3065 } 3066 3067 PUBLIC void 3068 ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT]) 3069 { 3070 3071 /* Make sure forced gain is disabled. */ 3072 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, 0); 3073 3074 AR_WRITE(sc, AR_PHY_PWRTX_RATE1, 3075 (power[ATHN_POWER_OFDM18 ] & 0x3f) << 24 | 3076 (power[ATHN_POWER_OFDM12 ] & 0x3f) << 16 | 3077 (power[ATHN_POWER_OFDM9 ] & 0x3f) << 8 | 3078 (power[ATHN_POWER_OFDM6 ] & 0x3f)); 3079 AR_WRITE(sc, AR_PHY_PWRTX_RATE2, 3080 (power[ATHN_POWER_OFDM54 ] & 0x3f) << 24 | 3081 (power[ATHN_POWER_OFDM48 ] & 0x3f) << 16 | 3082 (power[ATHN_POWER_OFDM36 ] & 0x3f) << 8 | 3083 (power[ATHN_POWER_OFDM24 ] & 0x3f)); 3084 AR_WRITE(sc, AR_PHY_PWRTX_RATE3, 3085 (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 | 3086 (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 | 3087 /* NB: No eXtended Range for AR9003. */ 3088 (power[ATHN_POWER_CCK1_LP ] & 0x3f)); 3089 AR_WRITE(sc, AR_PHY_PWRTX_RATE4, 3090 (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 | 3091 (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 | 3092 (power[ATHN_POWER_CCK55_SP] & 0x3f) << 8 | 3093 (power[ATHN_POWER_CCK55_LP] & 0x3f)); 3094 /* 3095 * NB: AR_PHY_PWRTX_RATE5 needs to be written even if HT is disabled 3096 * because it is read by PA predistortion functions. 3097 */ 3098 AR_WRITE(sc, AR_PHY_PWRTX_RATE5, 3099 (power[ATHN_POWER_HT20( 5)] & 0x3f) << 24 | 3100 (power[ATHN_POWER_HT20( 4)] & 0x3f) << 16 | 3101 (power[ATHN_POWER_HT20( 1)] & 0x3f) << 8 | 3102 (power[ATHN_POWER_HT20( 0)] & 0x3f)); 3103 #ifndef IEEE80211_NO_HT 3104 AR_WRITE(sc, AR_PHY_PWRTX_RATE6, 3105 (power[ATHN_POWER_HT20(13)] & 0x3f) << 24 | 3106 (power[ATHN_POWER_HT20(12)] & 0x3f) << 16 | 3107 (power[ATHN_POWER_HT20( 7)] & 0x3f) << 8 | 3108 (power[ATHN_POWER_HT20( 6)] & 0x3f)); 3109 AR_WRITE(sc, AR_PHY_PWRTX_RATE7, 3110 (power[ATHN_POWER_HT40( 5)] & 0x3f) << 24 | 3111 (power[ATHN_POWER_HT40( 4)] & 0x3f) << 16 | 3112 (power[ATHN_POWER_HT40( 1)] & 0x3f) << 8 | 3113 (power[ATHN_POWER_HT40( 0)] & 0x3f)); 3114 AR_WRITE(sc, AR_PHY_PWRTX_RATE8, 3115 (power[ATHN_POWER_HT40(13)] & 0x3f) << 24 | 3116 (power[ATHN_POWER_HT40(12)] & 0x3f) << 16 | 3117 (power[ATHN_POWER_HT40( 7)] & 0x3f) << 8 | 3118 (power[ATHN_POWER_HT40( 6)] & 0x3f)); 3119 AR_WRITE(sc, AR_PHY_PWRTX_RATE10, 3120 (power[ATHN_POWER_HT20(21)] & 0x3f) << 24 | 3121 (power[ATHN_POWER_HT20(20)] & 0x3f) << 16 | 3122 (power[ATHN_POWER_HT20(15)] & 0x3f) << 8 | 3123 (power[ATHN_POWER_HT20(14)] & 0x3f)); 3124 AR_WRITE(sc, AR_PHY_PWRTX_RATE11, 3125 (power[ATHN_POWER_HT40(23)] & 0x3f) << 24 | 3126 (power[ATHN_POWER_HT40(22)] & 0x3f) << 16 | 3127 (power[ATHN_POWER_HT20(23)] & 0x3f) << 8 | 3128 (power[ATHN_POWER_HT20(22)] & 0x3f)); 3129 AR_WRITE(sc, AR_PHY_PWRTX_RATE12, 3130 (power[ATHN_POWER_HT40(21)] & 0x3f) << 24 | 3131 (power[ATHN_POWER_HT40(20)] & 0x3f) << 16 | 3132 (power[ATHN_POWER_HT40(15)] & 0x3f) << 8 | 3133 (power[ATHN_POWER_HT40(14)] & 0x3f)); 3134 #endif 3135 AR_WRITE_BARRIER(sc); 3136 } 3137 3138 Static void 3139 ar9003_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3140 { 3141 #define X(x) ((uint32_t)(x) << 2) 3142 const struct athn_gain *prog = sc->sc_rx_gain; 3143 const uint32_t *pvals; 3144 int i; 3145 3146 if (IEEE80211_IS_CHAN_2GHZ(c)) 3147 pvals = prog->vals_2g; 3148 else 3149 pvals = prog->vals_5g; 3150 for (i = 0; i < prog->nregs; i++) 3151 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3152 AR_WRITE_BARRIER(sc); 3153 #undef X 3154 } 3155 3156 Static void 3157 ar9003_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3158 { 3159 #define X(x) ((uint32_t)(x) << 2) 3160 const struct athn_gain *prog = sc->sc_tx_gain; 3161 const uint32_t *pvals; 3162 int i; 3163 3164 if (IEEE80211_IS_CHAN_2GHZ(c)) 3165 pvals = prog->vals_2g; 3166 else 3167 pvals = prog->vals_5g; 3168 for (i = 0; i < prog->nregs; i++) 3169 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3170 AR_WRITE_BARRIER(sc); 3171 #undef X 3172 } 3173 3174 Static void 3175 ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c, 3176 struct ieee80211_channel *extc) 3177 { 3178 #define X(x) ((uint32_t)(x) << 2) 3179 struct athn_ops *ops = &sc->sc_ops; 3180 const struct athn_ini *ini = sc->sc_ini; 3181 const uint32_t *pvals; 3182 uint32_t reg; 3183 int i; 3184 3185 /* 3186 * The common init values include the pre and core phases for the 3187 * SoC, MAC, BB and Radio subsystems. 3188 */ 3189 DPRINTFN(DBG_INIT, sc, "writing pre and core init vals\n"); 3190 for (i = 0; i < ini->ncmregs; i++) { 3191 AR_WRITE(sc, X(ini->cmregs[i]), ini->cmvals[i]); 3192 if (AR_IS_ANALOG_REG(X(ini->cmregs[i]))) 3193 DELAY(100); 3194 if ((i & 0x1f) == 0) 3195 DELAY(1); 3196 } 3197 3198 /* 3199 * The modal init values include the post phase for the SoC, MAC, 3200 * BB and Radio subsystems. 3201 */ 3202 #ifndef IEEE80211_NO_HT 3203 if (extc != NULL) { 3204 if (IEEE80211_IS_CHAN_2GHZ(c)) 3205 pvals = ini->vals_2g40; 3206 else 3207 pvals = ini->vals_5g40; 3208 } 3209 else 3210 #endif 3211 { 3212 if (IEEE80211_IS_CHAN_2GHZ(c)) 3213 pvals = ini->vals_2g20; 3214 else 3215 pvals = ini->vals_5g20; 3216 } 3217 DPRINTFN(DBG_INIT, sc, "writing post init vals\n"); 3218 for (i = 0; i < ini->nregs; i++) { 3219 AR_WRITE(sc, X(ini->regs[i]), pvals[i]); 3220 if (AR_IS_ANALOG_REG(X(ini->regs[i]))) 3221 DELAY(100); 3222 if ((i & 0x1f) == 0) 3223 DELAY(1); 3224 } 3225 3226 if (sc->sc_rx_gain != NULL) 3227 ar9003_reset_rx_gain(sc, c); 3228 if (sc->sc_tx_gain != NULL) 3229 ar9003_reset_tx_gain(sc, c); 3230 3231 if (IEEE80211_IS_CHAN_5GHZ(c) && 3232 (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 3233 /* Update modal values for fast PLL clock. */ 3234 #ifndef IEEE80211_NO_HT 3235 if (extc != NULL) 3236 pvals = ini->fastvals_5g40; 3237 else 3238 #endif 3239 pvals = ini->fastvals_5g20; 3240 DPRINTFN(DBG_INIT, sc, "writing fast pll clock init vals\n"); 3241 for (i = 0; i < ini->nfastregs; i++) { 3242 AR_WRITE(sc, X(ini->fastregs[i]), pvals[i]); 3243 if (AR_IS_ANALOG_REG(X(ini->fastregs[i]))) 3244 DELAY(100); 3245 if ((i & 0x1f) == 0) 3246 DELAY(1); 3247 } 3248 } 3249 3250 /* 3251 * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted 3252 * descriptor status. 3253 */ 3254 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 3255 3256 reg = AR_READ(sc, AR_PCU_MISC_MODE2); 3257 reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE; 3258 reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX; 3259 reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP; 3260 AR_WRITE(sc, AR_PCU_MISC_MODE2, reg); 3261 AR_WRITE_BARRIER(sc); 3262 3263 ar9003_set_phy(sc, c, extc); 3264 ar9003_init_chains(sc); 3265 3266 ops->set_txpower(sc, c, extc); 3267 #undef X 3268 } 3269 3270 PUBLIC void 3271 ar9003_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3272 uint8_t ctl, const uint8_t *fbins, 3273 const struct ar_cal_target_power_leg *tgt, int nchans, uint8_t tpow[4]) 3274 { 3275 uint8_t fbin; 3276 int i, delta, lo, hi; 3277 3278 lo = hi = -1; 3279 fbin = athn_chan2fbin(c); 3280 for (i = 0; i < nchans; i++) { 3281 delta = fbin - fbins[i]; 3282 /* Find the largest sample that is <= our frequency. */ 3283 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3284 lo = i; 3285 /* Find the smallest sample that is >= our frequency. */ 3286 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3287 hi = i; 3288 } 3289 if (lo == -1) 3290 lo = hi; 3291 else if (hi == -1) 3292 hi = lo; 3293 /* Interpolate values. */ 3294 for (i = 0; i < 4; i++) { 3295 tpow[i] = athn_interpolate(fbin, 3296 fbins[lo], tgt[lo].tPow2x[i], 3297 fbins[hi], tgt[hi].tPow2x[i]); 3298 } 3299 /* XXX Apply conformance test limit. */ 3300 } 3301 3302 PUBLIC void 3303 ar9003_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3304 uint8_t ctl, const uint8_t *fbins, 3305 const struct ar_cal_target_power_ht *tgt, int nchans, uint8_t tpow[14]) 3306 { 3307 uint8_t fbin; 3308 int i, delta, lo, hi; 3309 3310 lo = hi = -1; 3311 fbin = athn_chan2fbin(c); 3312 for (i = 0; i < nchans; i++) { 3313 delta = fbin - fbins[i]; 3314 /* Find the largest sample that is <= our frequency. */ 3315 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3316 lo = i; 3317 /* Find the smallest sample that is >= our frequency. */ 3318 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3319 hi = i; 3320 } 3321 if (lo == -1) 3322 lo = hi; 3323 else if (hi == -1) 3324 hi = lo; 3325 /* Interpolate values. */ 3326 for (i = 0; i < 14; i++) { 3327 tpow[i] = athn_interpolate(fbin, 3328 fbins[lo], tgt[lo].tPow2x[i], 3329 fbins[hi], tgt[hi].tPow2x[i]); 3330 } 3331 /* XXX Apply conformance test limit. */ 3332 } 3333 3334 /* 3335 * Adaptive noise immunity. 3336 */ 3337 Static void 3338 ar9003_set_noise_immunity_level(struct athn_softc *sc, int level) 3339 { 3340 int high = level == 4; 3341 uint32_t reg; 3342 3343 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 3344 reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55); 3345 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 3346 3347 reg = AR_READ(sc, AR_PHY_AGC); 3348 reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64); 3349 reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14); 3350 AR_WRITE(sc, AR_PHY_AGC, reg); 3351 3352 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3353 reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78); 3354 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3355 AR_WRITE_BARRIER(sc); 3356 } 3357 3358 Static void 3359 ar9003_enable_ofdm_weak_signal(struct athn_softc *sc) 3360 { 3361 uint32_t reg; 3362 3363 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3364 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50); 3365 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40); 3366 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48); 3367 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3368 3369 reg = AR_READ(sc, AR_PHY_SFCORR); 3370 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77); 3371 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64); 3372 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16); 3373 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3374 3375 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3376 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50); 3377 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40); 3378 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77); 3379 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64); 3380 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3381 3382 AR_SETBITS(sc, AR_PHY_SFCORR_LOW, 3383 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3384 AR_WRITE_BARRIER(sc); 3385 } 3386 3387 Static void 3388 ar9003_disable_ofdm_weak_signal(struct athn_softc *sc) 3389 { 3390 uint32_t reg; 3391 3392 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3393 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127); 3394 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127); 3395 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63); 3396 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3397 3398 reg = AR_READ(sc, AR_PHY_SFCORR); 3399 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127); 3400 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127); 3401 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31); 3402 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3403 3404 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3405 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127); 3406 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127); 3407 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127); 3408 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127); 3409 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3410 3411 AR_CLRBITS(sc, AR_PHY_SFCORR_LOW, 3412 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3413 AR_WRITE_BARRIER(sc); 3414 } 3415 3416 Static void 3417 ar9003_set_cck_weak_signal(struct athn_softc *sc, int high) 3418 { 3419 uint32_t reg; 3420 3421 reg = AR_READ(sc, AR_PHY_CCK_DETECT); 3422 reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8); 3423 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); 3424 AR_WRITE_BARRIER(sc); 3425 } 3426 3427 Static void 3428 ar9003_set_firstep_level(struct athn_softc *sc, int level) 3429 { 3430 uint32_t reg; 3431 3432 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3433 reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4); 3434 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3435 AR_WRITE_BARRIER(sc); 3436 } 3437 3438 Static void 3439 ar9003_set_spur_immunity_level(struct athn_softc *sc, int level) 3440 { 3441 uint32_t reg; 3442 3443 reg = AR_READ(sc, AR_PHY_TIMING5); 3444 reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2); 3445 AR_WRITE(sc, AR_PHY_TIMING5, reg); 3446 AR_WRITE_BARRIER(sc); 3447 } 3448
Indexes created Thu Oct 23 22:10:10 GMT 2025