arn9003.c revision 1.14.2.1
1 /* $NetBSD: arn9003.c,v 1.14.2.1 2020/02/29 20:19:08 ad Exp $ */ 2 /* $OpenBSD: ar9003.c,v 1.25 2012/10/20 09:53:32 stsp Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 * Routines for AR9003 family. 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: arn9003.c,v 1.14.2.1 2020/02/29 20:19:08 ad Exp $"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/queue.h> 37 #include <sys/callout.h> 38 #include <sys/conf.h> 39 #include <sys/device.h> 40 41 #include <sys/bus.h> 42 #include <sys/endian.h> 43 #include <sys/intr.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_ether.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/in_var.h> 56 #include <netinet/ip.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_amrr.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <dev/ic/athnreg.h> 63 #include <dev/ic/athnvar.h> 64 #include <dev/ic/arn9003reg.h> 65 #include <dev/ic/arn9003.h> 66 67 #define Static static 68 69 Static void ar9003_calib_iq(struct athn_softc *); 70 Static int ar9003_calib_tx_iq(struct athn_softc *); 71 Static int ar9003_compute_predistortion(struct athn_softc *, 72 const uint32_t *, const uint32_t *); 73 Static void ar9003_disable_ofdm_weak_signal(struct athn_softc *); 74 Static void ar9003_disable_phy(struct athn_softc *); 75 Static int ar9003_dma_alloc(struct athn_softc *); 76 Static void ar9003_dma_free(struct athn_softc *); 77 Static void ar9003_do_calib(struct athn_softc *); 78 Static void ar9003_do_noisefloor_calib(struct athn_softc *); 79 Static void ar9003_enable_antenna_diversity(struct athn_softc *); 80 Static void ar9003_enable_ofdm_weak_signal(struct athn_softc *); 81 Static void ar9003_enable_predistorter(struct athn_softc *, int); 82 Static int ar9003_find_rom(struct athn_softc *); 83 Static void ar9003_force_txgain(struct athn_softc *, uint32_t); 84 Static int ar9003_get_desired_txgain(struct athn_softc *, int, int); 85 Static int ar9003_get_iq_corr(struct athn_softc *, int32_t[], int32_t[]); 86 Static void ar9003_gpio_config_input(struct athn_softc *, int); 87 Static void ar9003_gpio_config_output(struct athn_softc *, int, int); 88 Static int ar9003_gpio_read(struct athn_softc *, int); 89 Static void ar9003_gpio_write(struct athn_softc *, int, int); 90 Static void ar9003_hw_init(struct athn_softc *, struct ieee80211_channel *, 91 struct ieee80211_channel *); 92 Static void ar9003_init_baseband(struct athn_softc *); 93 Static void ar9003_init_chains(struct athn_softc *); 94 Static int ar9003_intr_status(struct athn_softc *); 95 Static int ar9003_intr(struct athn_softc *); 96 Static void ar9003_next_calib(struct athn_softc *); 97 Static void ar9003_paprd_enable(struct athn_softc *); 98 Static int ar9003_paprd_tx_tone(struct athn_softc *); 99 Static void ar9003_paprd_tx_tone_done(struct athn_softc *); 100 Static int ar9003_read_eep_data(struct athn_softc *, uint32_t, void *, 101 int); 102 Static int ar9003_read_eep_word(struct athn_softc *, uint32_t, 103 uint16_t *); 104 Static int ar9003_read_otp_data(struct athn_softc *, uint32_t, void *, 105 int); 106 Static int ar9003_read_otp_word(struct athn_softc *, uint32_t, 107 uint32_t *); 108 Static int ar9003_read_rom(struct athn_softc *); 109 Static void ar9003_reset_rx_gain(struct athn_softc *, 110 struct ieee80211_channel *); 111 Static void ar9003_reset_tx_gain(struct athn_softc *, 112 struct ieee80211_channel *); 113 Static int ar9003_restore_rom_block(struct athn_softc *, uint8_t, 114 uint8_t, const uint8_t *, size_t); 115 Static void ar9003_rf_bus_release(struct athn_softc *); 116 Static int ar9003_rf_bus_request(struct athn_softc *); 117 Static void ar9003_rfsilent_init(struct athn_softc *); 118 Static int ar9003_rx_alloc(struct athn_softc *, int, int); 119 Static void ar9003_rx_enable(struct athn_softc *); 120 Static void ar9003_rx_free(struct athn_softc *, int); 121 Static void ar9003_rx_intr(struct athn_softc *, int); 122 Static int ar9003_rx_process(struct athn_softc *, int); 123 Static void ar9003_rx_radiotap(struct athn_softc *, struct mbuf *, 124 struct ar_rx_status *); 125 Static void ar9003_set_cck_weak_signal(struct athn_softc *, int); 126 Static void ar9003_set_delta_slope(struct athn_softc *, 127 struct ieee80211_channel *, struct ieee80211_channel *); 128 Static void ar9003_set_firstep_level(struct athn_softc *, int); 129 Static void ar9003_set_noise_immunity_level(struct athn_softc *, int); 130 Static void ar9003_set_phy(struct athn_softc *, struct ieee80211_channel *, 131 struct ieee80211_channel *); 132 Static void ar9003_set_rf_mode(struct athn_softc *, 133 struct ieee80211_channel *); 134 Static void ar9003_set_rxchains(struct athn_softc *); 135 Static void ar9003_set_spur_immunity_level(struct athn_softc *, int); 136 Static void ar9003_set_training_gain(struct athn_softc *, int); 137 Static int ar9003_swba_intr(struct athn_softc *); 138 Static int ar9003_tx(struct athn_softc *, struct mbuf *, 139 struct ieee80211_node *, int); 140 Static int ar9003_tx_alloc(struct athn_softc *); 141 Static void ar9003_tx_free(struct athn_softc *); 142 Static void ar9003_tx_intr(struct athn_softc *); 143 Static int ar9003_tx_process(struct athn_softc *); 144 145 #ifdef notused 146 Static void ar9003_bb_load_noisefloor(struct athn_softc *); 147 Static void ar9003_get_noisefloor(struct athn_softc *, 148 struct ieee80211_channel *); 149 Static void ar9003_paprd_calib(struct athn_softc *, 150 struct ieee80211_channel *); 151 Static void ar9003_read_noisefloor(struct athn_softc *, int16_t *, 152 int16_t *); 153 Static void ar9003_write_noisefloor(struct athn_softc *, int16_t *, 154 int16_t *); 155 Static void ar9300_noisefloor_calib(struct athn_softc *); 156 #endif /* notused */ 157 158 /* 159 * XXX: See if_iwn.c:MCLGETIalt() for a better solution. 160 * XXX: Put this in a header or in athn.c so it can be shared between 161 * ar5008.c and ar9003.c? 162 */ 163 static struct mbuf * 164 MCLGETI(struct athn_softc *sc __unused, int how, 165 struct ifnet *ifp __unused, u_int size) 166 { 167 struct mbuf *m; 168 169 MGETHDR(m, how, MT_DATA); 170 if (m == NULL) 171 return NULL; 172 173 MEXTMALLOC(m, size, how); 174 if ((m->m_flags & M_EXT) == 0) { 175 m_freem(m); 176 return NULL; 177 } 178 return m; 179 } 180 181 PUBLIC int 182 ar9003_attach(struct athn_softc *sc) 183 { 184 struct athn_ops *ops = &sc->sc_ops; 185 int error; 186 187 /* Set callbacks for AR9003 family. */ 188 ops->gpio_read = ar9003_gpio_read; 189 ops->gpio_write = ar9003_gpio_write; 190 ops->gpio_config_input = ar9003_gpio_config_input; 191 ops->gpio_config_output = ar9003_gpio_config_output; 192 ops->rfsilent_init = ar9003_rfsilent_init; 193 194 ops->dma_alloc = ar9003_dma_alloc; 195 ops->dma_free = ar9003_dma_free; 196 ops->rx_enable = ar9003_rx_enable; 197 ops->intr_status = ar9003_intr_status; 198 ops->intr = ar9003_intr; 199 ops->tx = ar9003_tx; 200 201 ops->set_rf_mode = ar9003_set_rf_mode; 202 ops->rf_bus_request = ar9003_rf_bus_request; 203 ops->rf_bus_release = ar9003_rf_bus_release; 204 ops->set_phy = ar9003_set_phy; 205 ops->set_delta_slope = ar9003_set_delta_slope; 206 ops->enable_antenna_diversity = ar9003_enable_antenna_diversity; 207 ops->init_baseband = ar9003_init_baseband; 208 ops->disable_phy = ar9003_disable_phy; 209 ops->set_rxchains = ar9003_set_rxchains; 210 ops->noisefloor_calib = ar9003_do_noisefloor_calib; 211 ops->do_calib = ar9003_do_calib; 212 ops->next_calib = ar9003_next_calib; 213 ops->hw_init = ar9003_hw_init; 214 215 ops->set_noise_immunity_level = ar9003_set_noise_immunity_level; 216 ops->enable_ofdm_weak_signal = ar9003_enable_ofdm_weak_signal; 217 ops->disable_ofdm_weak_signal = ar9003_disable_ofdm_weak_signal; 218 ops->set_cck_weak_signal = ar9003_set_cck_weak_signal; 219 ops->set_firstep_level = ar9003_set_firstep_level; 220 ops->set_spur_immunity_level = ar9003_set_spur_immunity_level; 221 222 /* Set MAC registers offsets. */ 223 sc->sc_obs_off = AR_OBS; 224 sc->sc_gpio_input_en_off = AR_GPIO_INPUT_EN_VAL; 225 226 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 227 athn_config_nonpcie(sc); 228 else 229 athn_config_pcie(sc); 230 231 /* Determine ROM type and location. */ 232 if ((error = ar9003_find_rom(sc)) != 0) { 233 aprint_error_dev(sc->sc_dev, "could not find ROM\n"); 234 return error; 235 } 236 /* Read entire ROM content in memory. */ 237 if ((error = ar9003_read_rom(sc)) != 0) { 238 aprint_error_dev(sc->sc_dev, "could not read ROM\n"); 239 return error; 240 } 241 242 /* Determine if it is a non-enterprise AR9003 card. */ 243 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_MPSD) 244 sc->sc_flags |= ATHN_FLAG_NON_ENTERPRISE; 245 246 ops->setup(sc); 247 return 0; 248 } 249 250 /* 251 * Read 16-bit word from EEPROM. 252 */ 253 Static int 254 ar9003_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val) 255 { 256 uint32_t reg; 257 int ntries; 258 259 reg = AR_READ(sc, AR_EEPROM_OFFSET(addr)); 260 for (ntries = 0; ntries < 1000; ntries++) { 261 reg = AR_READ(sc, AR_EEPROM_STATUS_DATA); 262 if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY | 263 AR_EEPROM_STATUS_DATA_PROT_ACCESS))) { 264 *val = MS(reg, AR_EEPROM_STATUS_DATA_VAL); 265 return 0; 266 } 267 DELAY(10); 268 } 269 *val = 0xffff; 270 return ETIMEDOUT; 271 } 272 273 /* 274 * Read an arbitrary number of bytes at a specified address in EEPROM. 275 * NB: The address may not be 16-bit aligned. 276 */ 277 Static int 278 ar9003_read_eep_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 279 { 280 uint8_t *dst = buf; 281 uint16_t val; 282 int error; 283 284 if (len > 0 && (addr & 1)) { 285 /* Deal with non-aligned reads. */ 286 addr >>= 1; 287 error = ar9003_read_eep_word(sc, addr, &val); 288 if (error != 0) 289 return error; 290 *dst++ = val & 0xff; 291 addr--; 292 len--; 293 } 294 else 295 addr >>= 1; 296 for (; len >= 2; addr--, len -= 2) { 297 error = ar9003_read_eep_word(sc, addr, &val); 298 if (error != 0) 299 return error; 300 *dst++ = val >> 8; 301 *dst++ = val & 0xff; 302 } 303 if (len > 0) { 304 error = ar9003_read_eep_word(sc, addr, &val); 305 if (error != 0) 306 return error; 307 *dst++ = val >> 8; 308 } 309 return 0; 310 } 311 312 /* 313 * Read 32-bit word from OTPROM. 314 */ 315 Static int 316 ar9003_read_otp_word(struct athn_softc *sc, uint32_t addr, uint32_t *val) 317 { 318 uint32_t reg; 319 int ntries; 320 321 reg = AR_READ(sc, AR_OTP_BASE(addr)); 322 for (ntries = 0; ntries < 1000; ntries++) { 323 reg = AR_READ(sc, AR_OTP_STATUS); 324 if (MS(reg, AR_OTP_STATUS_TYPE) == AR_OTP_STATUS_VALID) { 325 *val = AR_READ(sc, AR_OTP_READ_DATA); 326 return 0; 327 } 328 DELAY(10); 329 } 330 return ETIMEDOUT; 331 } 332 333 /* 334 * Read an arbitrary number of bytes at a specified address in OTPROM. 335 * NB: The address may not be 32-bit aligned. 336 */ 337 Static int 338 ar9003_read_otp_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 339 { 340 uint8_t *dst = buf; 341 uint32_t val; 342 int error; 343 344 /* NB: not optimal for non-aligned reads, but correct. */ 345 for (; len > 0; addr--, len--) { 346 error = ar9003_read_otp_word(sc, addr >> 2, &val); 347 if (error != 0) 348 return error; 349 *dst++ = (val >> ((addr & 3) * 8)) & 0xff; 350 } 351 return 0; 352 } 353 354 /* 355 * Determine if the chip has an external EEPROM or an OTPROM and its size. 356 */ 357 Static int 358 ar9003_find_rom(struct athn_softc *sc) 359 { 360 struct athn_ops *ops = &sc->sc_ops; 361 uint32_t hdr; 362 int error; 363 364 /* Try EEPROM. */ 365 ops->read_rom_data = ar9003_read_eep_data; 366 367 sc->sc_eep_size = AR_SREV_9485(sc) ? 4096 : 1024; 368 sc->sc_eep_base = sc->sc_eep_size - 1; 369 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 370 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 371 return 0; 372 373 sc->sc_eep_size = 512; 374 sc->sc_eep_base = sc->sc_eep_size - 1; 375 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 376 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 377 return 0; 378 379 /* Try OTPROM. */ 380 ops->read_rom_data = ar9003_read_otp_data; 381 382 sc->sc_eep_size = 1024; 383 sc->sc_eep_base = sc->sc_eep_size - 1; 384 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 385 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 386 return 0; 387 388 sc->sc_eep_size = 512; 389 sc->sc_eep_base = sc->sc_eep_size - 1; 390 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 391 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 392 return 0; 393 394 return EIO; /* Not found. */ 395 } 396 397 Static int 398 ar9003_restore_rom_block(struct athn_softc *sc, uint8_t alg, uint8_t ref, 399 const uint8_t *buf, size_t len) 400 { 401 const uint8_t *def, *ptr, *end; 402 uint8_t *eep = sc->sc_eep; 403 size_t off, clen; 404 405 if (alg == AR_EEP_COMPRESS_BLOCK) { 406 /* Block contains chunks that shadow ROM template. */ 407 def = sc->sc_ops.get_rom_template(sc, ref); 408 if (def == NULL) { 409 DPRINTFN(DBG_INIT, sc, "unknown template image %d\n", 410 ref); 411 return EINVAL; 412 } 413 /* Start with template. */ 414 memcpy(eep, def, sc->sc_eep_size); 415 /* Shadow template with chunks. */ 416 off = 0; /* Offset in ROM image. */ 417 ptr = buf; /* Offset in block. */ 418 end = buf + len; 419 /* Process chunks. */ 420 while (ptr + 2 <= end) { 421 off += *ptr++; /* Gap with previous chunk. */ 422 clen = *ptr++; /* Chunk length. */ 423 /* Make sure block is large enough. */ 424 if (ptr + clen > end) 425 return EINVAL; 426 /* Make sure chunk fits in ROM image. */ 427 if (off + clen > sc->sc_eep_size) 428 return EINVAL; 429 /* Restore chunk. */ 430 DPRINTFN(DBG_INIT, sc, "ROM chunk @%zd/%zd\n", 431 off, clen); 432 memcpy(&eep[off], ptr, clen); 433 ptr += clen; 434 off += clen; 435 } 436 } 437 else if (alg == AR_EEP_COMPRESS_NONE) { 438 /* Block contains full ROM image. */ 439 if (len != sc->sc_eep_size) { 440 DPRINTFN(DBG_INIT, sc, "block length mismatch %zd\n", 441 len); 442 return EINVAL; 443 } 444 memcpy(eep, buf, len); 445 } 446 return 0; 447 } 448 449 Static int 450 ar9003_read_rom(struct athn_softc *sc) 451 { 452 struct athn_ops *ops = &sc->sc_ops; 453 uint8_t *buf, *ptr, alg, ref; 454 uint16_t sum, rsum; 455 uint32_t hdr; 456 int error, addr; 457 size_t len, i, j; 458 459 /* Allocate space to store ROM in host memory. */ 460 sc->sc_eep = malloc(sc->sc_eep_size, M_DEVBUF, M_WAITOK); 461 462 /* Allocate temporary buffer to store ROM blocks. */ 463 buf = malloc(2048, M_DEVBUF, M_WAITOK); 464 465 /* Restore vendor-specified ROM blocks. */ 466 addr = sc->sc_eep_base; 467 for (i = 0; i < 100; i++) { 468 /* Read block header. */ 469 error = ops->read_rom_data(sc, addr, &hdr, sizeof(hdr)); 470 if (error != 0) 471 break; 472 if (hdr == 0 || hdr == 0xffffffff) 473 break; 474 addr -= sizeof(hdr); 475 476 /* Extract bits from header. */ 477 ptr = (uint8_t *)&hdr; 478 alg = (ptr[0] & 0xe0) >> 5; 479 ref = (ptr[1] & 0x80) >> 2 | (ptr[0] & 0x1f); 480 len = (ptr[1] & 0x7f) << 4 | (ptr[2] & 0xf0) >> 4; 481 DPRINTFN(DBG_INIT, sc, 482 "ROM block %zd: alg=%d ref=%d len=%zd\n", 483 i, alg, ref, len); 484 485 /* Read block data (len <= 0x7ff). */ 486 error = ops->read_rom_data(sc, addr, buf, len); 487 if (error != 0) 488 break; 489 addr -= len; 490 491 /* Read block checksum. */ 492 error = ops->read_rom_data(sc, addr, &sum, sizeof(sum)); 493 if (error != 0) 494 break; 495 addr -= sizeof(sum); 496 497 /* Compute block checksum. */ 498 rsum = 0; 499 for (j = 0; j < len; j++) 500 rsum += buf[j]; 501 /* Compare to that in ROM. */ 502 if (le16toh(sum) != rsum) { 503 DPRINTFN(DBG_INIT, sc, 504 "bad block checksum 0x%x/0x%x\n", 505 le16toh(sum), rsum); 506 continue; /* Skip bad block. */ 507 } 508 /* Checksum is correct, restore block. */ 509 ar9003_restore_rom_block(sc, alg, ref, buf, len); 510 } 511 #if BYTE_ORDER == BIG_ENDIAN 512 /* NB: ROM is always little endian. */ 513 if (error == 0) 514 ops->swap_rom(sc); 515 #endif 516 free(buf, M_DEVBUF); 517 return error; 518 } 519 520 /* 521 * Access to General Purpose Input/Output ports. 522 */ 523 Static int 524 ar9003_gpio_read(struct athn_softc *sc, int pin) 525 { 526 527 KASSERT(pin < sc->sc_ngpiopins); 528 return ((AR_READ(sc, AR_GPIO_IN) & AR9300_GPIO_IN_VAL) & 529 (1 << pin)) != 0; 530 } 531 532 Static void 533 ar9003_gpio_write(struct athn_softc *sc, int pin, int set) 534 { 535 uint32_t reg; 536 537 KASSERT(pin < sc->sc_ngpiopins); 538 reg = AR_READ(sc, AR_GPIO_IN_OUT); 539 if (set) 540 reg |= 1 << pin; 541 else 542 reg &= ~(1 << pin); 543 AR_WRITE(sc, AR_GPIO_IN_OUT, reg); 544 AR_WRITE_BARRIER(sc); 545 } 546 547 Static void 548 ar9003_gpio_config_input(struct athn_softc *sc, int pin) 549 { 550 uint32_t reg; 551 552 reg = AR_READ(sc, AR_GPIO_OE_OUT); 553 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 554 reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2); 555 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 556 AR_WRITE_BARRIER(sc); 557 } 558 559 Static void 560 ar9003_gpio_config_output(struct athn_softc *sc, int pin, int type) 561 { 562 uint32_t reg; 563 int mux, off; 564 565 mux = pin / 6; 566 off = pin % 6; 567 568 reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux)); 569 reg &= ~(0x1f << (off * 5)); 570 reg |= (type & 0x1f) << (off * 5); 571 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg); 572 573 reg = AR_READ(sc, AR_GPIO_OE_OUT); 574 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 575 reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2); 576 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 577 AR_WRITE_BARRIER(sc); 578 } 579 580 Static void 581 ar9003_rfsilent_init(struct athn_softc *sc) 582 { 583 uint32_t reg; 584 585 /* Configure hardware radio switch. */ 586 AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 587 reg = AR_READ(sc, AR_GPIO_INPUT_MUX2); 588 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); 589 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg); 590 ar9003_gpio_config_input(sc, sc->sc_rfsilent_pin); 591 AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB); 592 if (!(sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED)) { 593 AR_SETBITS(sc, AR_GPIO_INTR_POL, 594 AR_GPIO_INTR_POL_PIN(sc->sc_rfsilent_pin)); 595 } 596 AR_WRITE_BARRIER(sc); 597 } 598 599 Static int 600 ar9003_dma_alloc(struct athn_softc *sc) 601 { 602 int error; 603 604 error = ar9003_tx_alloc(sc); 605 if (error != 0) 606 return error; 607 608 error = ar9003_rx_alloc(sc, ATHN_QID_LP, AR9003_RX_LP_QDEPTH); 609 if (error != 0) 610 return error; 611 612 error = ar9003_rx_alloc(sc, ATHN_QID_HP, AR9003_RX_HP_QDEPTH); 613 if (error != 0) 614 return error; 615 616 return 0; 617 } 618 619 Static void 620 ar9003_dma_free(struct athn_softc *sc) 621 { 622 623 ar9003_tx_free(sc); 624 ar9003_rx_free(sc, ATHN_QID_LP); 625 ar9003_rx_free(sc, ATHN_QID_HP); 626 } 627 628 Static int 629 ar9003_tx_alloc(struct athn_softc *sc) 630 { 631 struct athn_tx_buf *bf; 632 bus_size_t size; 633 int error, nsegs, i; 634 635 /* 636 * Allocate Tx status ring. 637 */ 638 size = AR9003_NTXSTATUS * sizeof(struct ar_tx_status); 639 640 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 641 BUS_DMA_NOWAIT, &sc->sc_txsmap); 642 if (error != 0) 643 goto fail; 644 645 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_txsseg, 1, 646 // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 647 &nsegs, BUS_DMA_NOWAIT); 648 if (error != 0) 649 goto fail; 650 651 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_txsseg, 1, size, 652 (void **)&sc->sc_txsring, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 653 if (error != 0) 654 goto fail; 655 656 error = bus_dmamap_load(sc->sc_dmat, sc->sc_txsmap, sc->sc_txsring, 657 size, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 658 if (error != 0) 659 goto fail; 660 661 /* 662 * Allocate a pool of Tx descriptors shared between all Tx queues. 663 */ 664 size = ATHN_NTXBUFS * sizeof(struct ar_tx_desc); 665 666 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 667 BUS_DMA_NOWAIT, &sc->sc_map); 668 if (error != 0) 669 goto fail; 670 671 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_seg, 1, 672 // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 673 &nsegs, BUS_DMA_NOWAIT); 674 if (error != 0) 675 goto fail; 676 677 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, 1, size, 678 (void **)&sc->sc_descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 679 if (error != 0) 680 goto fail; 681 682 error = bus_dmamap_load(sc->sc_dmat, sc->sc_map, sc->sc_descs, size, 683 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 684 if (error != 0) 685 goto fail; 686 687 SIMPLEQ_INIT(&sc->sc_txbufs); 688 for (i = 0; i < ATHN_NTXBUFS; i++) { 689 bf = &sc->sc_txpool[i]; 690 691 error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ, 692 AR9003_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT, 693 &bf->bf_map); 694 if (error != 0) { 695 aprint_error_dev(sc->sc_dev, 696 "could not create Tx buf DMA map\n"); 697 goto fail; 698 } 699 700 bf->bf_descs = &((struct ar_tx_desc *)sc->sc_descs)[i]; 701 bf->bf_daddr = sc->sc_map->dm_segs[0].ds_addr + 702 i * sizeof(struct ar_tx_desc); 703 704 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 705 } 706 return 0; 707 fail: 708 ar9003_tx_free(sc); 709 return error; 710 } 711 712 Static void 713 ar9003_tx_free(struct athn_softc *sc) 714 { 715 struct athn_tx_buf *bf; 716 int i; 717 718 for (i = 0; i < ATHN_NTXBUFS; i++) { 719 bf = &sc->sc_txpool[i]; 720 721 if (bf->bf_map != NULL) 722 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 723 } 724 /* Free Tx descriptors. */ 725 if (sc->sc_map != NULL) { 726 if (sc->sc_descs != NULL) { 727 bus_dmamap_unload(sc->sc_dmat, sc->sc_map); 728 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 729 ATHN_NTXBUFS * sizeof(struct ar_tx_desc)); 730 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 731 } 732 bus_dmamap_destroy(sc->sc_dmat, sc->sc_map); 733 } 734 /* Free Tx status ring. */ 735 if (sc->sc_txsmap != NULL) { 736 if (sc->sc_txsring != NULL) { 737 bus_dmamap_unload(sc->sc_dmat, sc->sc_txsmap); 738 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_txsring, 739 AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 740 bus_dmamem_free(sc->sc_dmat, &sc->sc_txsseg, 1); 741 } 742 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsmap); 743 } 744 } 745 746 Static int 747 ar9003_rx_alloc(struct athn_softc *sc, int qid, int count) 748 { 749 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 750 struct athn_rx_buf *bf; 751 struct ar_rx_status *ds; 752 int error, i; 753 754 rxq->bf = malloc(count * sizeof(*bf), M_DEVBUF, M_WAITOK | M_ZERO); 755 rxq->count = count; 756 757 for (i = 0; i < rxq->count; i++) { 758 bf = &rxq->bf[i]; 759 760 error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1, 761 ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 762 &bf->bf_map); 763 if (error != 0) { 764 aprint_error_dev(sc->sc_dev, 765 "could not create Rx buf DMA map\n"); 766 goto fail; 767 } 768 /* 769 * Assumes MCLGETI returns cache-line-size aligned buffers. 770 */ 771 bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 772 if (bf->bf_m == NULL) { 773 aprint_error_dev(sc->sc_dev, 774 "could not allocate Rx mbuf\n"); 775 error = ENOBUFS; 776 goto fail; 777 } 778 779 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 780 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 781 BUS_DMA_NOWAIT); 782 if (error != 0) { 783 aprint_error_dev(sc->sc_dev, 784 "could not DMA map Rx buffer\n"); 785 goto fail; 786 } 787 788 ds = mtod(bf->bf_m, struct ar_rx_status *); 789 memset(ds, 0, sizeof(*ds)); 790 bf->bf_desc = ds; 791 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 792 793 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 794 BUS_DMASYNC_PREREAD); 795 } 796 return 0; 797 fail: 798 ar9003_rx_free(sc, qid); 799 return error; 800 } 801 802 Static void 803 ar9003_rx_free(struct athn_softc *sc, int qid) 804 { 805 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 806 struct athn_rx_buf *bf; 807 int i; 808 809 if (rxq->bf == NULL) 810 return; 811 for (i = 0; i < rxq->count; i++) { 812 bf = &rxq->bf[i]; 813 814 if (bf->bf_map != NULL) 815 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 816 if (bf->bf_m != NULL) 817 m_freem(bf->bf_m); 818 } 819 free(rxq->bf, M_DEVBUF); 820 } 821 822 PUBLIC void 823 ar9003_reset_txsring(struct athn_softc *sc) 824 { 825 826 sc->sc_txscur = 0; 827 memset(sc->sc_txsring, 0, AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 828 AR_WRITE(sc, AR_Q_STATUS_RING_START, 829 sc->sc_txsmap->dm_segs[0].ds_addr); 830 AR_WRITE(sc, AR_Q_STATUS_RING_END, 831 sc->sc_txsmap->dm_segs[0].ds_addr + sc->sc_txsmap->dm_segs[0].ds_len); 832 AR_WRITE_BARRIER(sc); 833 } 834 835 Static void 836 ar9003_rx_enable(struct athn_softc *sc) 837 { 838 struct athn_rxq *rxq; 839 struct athn_rx_buf *bf; 840 struct ar_rx_status *ds; 841 uint32_t reg; 842 int qid, i; 843 844 reg = AR_READ(sc, AR_RXBP_THRESH); 845 reg = RW(reg, AR_RXBP_THRESH_HP, 1); 846 reg = RW(reg, AR_RXBP_THRESH_LP, 1); 847 AR_WRITE(sc, AR_RXBP_THRESH, reg); 848 849 /* Set Rx buffer size. */ 850 AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds)); 851 852 for (qid = 0; qid < 2; qid++) { 853 rxq = &sc->sc_rxq[qid]; 854 855 /* Setup Rx status descriptors. */ 856 SIMPLEQ_INIT(&rxq->head); 857 for (i = 0; i < rxq->count; i++) { 858 bf = &rxq->bf[i]; 859 ds = bf->bf_desc; 860 861 memset(ds, 0, sizeof(*ds)); 862 if (qid == ATHN_QID_LP) 863 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 864 else 865 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 866 AR_WRITE_BARRIER(sc); 867 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 868 } 869 } 870 /* Enable Rx. */ 871 AR_WRITE(sc, AR_CR, 0); 872 AR_WRITE_BARRIER(sc); 873 } 874 875 Static void 876 ar9003_rx_radiotap(struct athn_softc *sc, struct mbuf *m, 877 struct ar_rx_status *ds) 878 { 879 struct athn_rx_radiotap_header *tap = &sc->sc_rxtap; 880 struct ieee80211com *ic = &sc->sc_ic; 881 uint64_t tsf; 882 uint32_t tstamp; 883 uint8_t rate; 884 885 /* Extend the 15-bit timestamp from Rx status to 64-bit TSF. */ 886 tstamp = ds->ds_status3; 887 tsf = AR_READ(sc, AR_TSF_U32); 888 tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32); 889 if ((tsf & 0x7fff) < tstamp) 890 tsf -= 0x8000; 891 tsf = (tsf & ~0x7fff) | tstamp; 892 893 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 894 tap->wr_tsft = htole64(tsf); 895 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 896 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 897 tap->wr_dbm_antsignal = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 898 /* XXX noise. */ 899 tap->wr_antenna = MS(ds->ds_status4, AR_RXS4_ANTENNA); 900 tap->wr_rate = 0; /* In case it can't be found below. */ 901 rate = MS(ds->ds_status1, AR_RXS1_RATE); 902 if (rate & 0x80) { /* HT. */ 903 /* Bit 7 set means HT MCS instead of rate. */ 904 tap->wr_rate = rate; 905 if (!(ds->ds_status4 & AR_RXS4_GI)) 906 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 907 908 } 909 else if (rate & 0x10) { /* CCK. */ 910 if (rate & 0x04) 911 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 912 switch (rate & ~0x14) { 913 case 0xb: tap->wr_rate = 2; break; 914 case 0xa: tap->wr_rate = 4; break; 915 case 0x9: tap->wr_rate = 11; break; 916 case 0x8: tap->wr_rate = 22; break; 917 } 918 } 919 else { /* OFDM. */ 920 switch (rate) { 921 case 0xb: tap->wr_rate = 12; break; 922 case 0xf: tap->wr_rate = 18; break; 923 case 0xa: tap->wr_rate = 24; break; 924 case 0xe: tap->wr_rate = 36; break; 925 case 0x9: tap->wr_rate = 48; break; 926 case 0xd: tap->wr_rate = 72; break; 927 case 0x8: tap->wr_rate = 96; break; 928 case 0xc: tap->wr_rate = 108; break; 929 } 930 } 931 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 932 } 933 934 Static int 935 ar9003_rx_process(struct athn_softc *sc, int qid) 936 { 937 struct ieee80211com *ic = &sc->sc_ic; 938 struct ifnet *ifp = &sc->sc_if; 939 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 940 struct athn_rx_buf *bf; 941 struct ar_rx_status *ds; 942 struct ieee80211_frame *wh; 943 struct ieee80211_node *ni; 944 struct mbuf *m, *m1; 945 size_t len; 946 u_int32_t rstamp; 947 int error, rssi, s; 948 949 bf = SIMPLEQ_FIRST(&rxq->head); 950 if (__predict_false(bf == NULL)) { /* Should not happen. */ 951 aprint_error_dev(sc->sc_dev, "Rx queue is empty!\n"); 952 return ENOENT; 953 } 954 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 955 BUS_DMASYNC_POSTREAD); 956 957 ds = mtod(bf->bf_m, struct ar_rx_status *); 958 if (!(ds->ds_status1 & AR_RXS1_DONE)) 959 return EBUSY; 960 961 /* Check that it is a valid Rx status descriptor. */ 962 if ((ds->ds_info & (AR_RXI_DESC_ID_M | AR_RXI_DESC_TX | 963 AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS)) 964 goto skip; 965 966 if (!(ds->ds_status11 & AR_RXS11_FRAME_OK)) { 967 if (ds->ds_status11 & AR_RXS11_CRC_ERR) 968 DPRINTFN(DBG_RX, sc, "CRC error\n"); 969 else if (ds->ds_status11 & AR_RXS11_PHY_ERR) 970 DPRINTFN(DBG_RX, sc, "PHY error=0x%x\n", 971 MS(ds->ds_status11, AR_RXS11_PHY_ERR_CODE)); 972 else if (ds->ds_status11 & AR_RXS11_DECRYPT_CRC_ERR) 973 DPRINTFN(DBG_RX, sc, "Decryption CRC error\n"); 974 else if (ds->ds_status11 & AR_RXS11_MICHAEL_ERR) { 975 DPRINTFN(DBG_RX, sc, "Michael MIC failure\n"); 976 /* Report Michael MIC failures to net80211. */ 977 978 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 979 m = bf->bf_m; 980 m_set_rcvif(m, ifp); 981 m->m_data = (void *)&ds[1]; 982 m->m_pkthdr.len = m->m_len = len; 983 wh = mtod(m, struct ieee80211_frame *); 984 985 ieee80211_notify_michael_failure(ic, wh, 986 0 /* XXX: keyix */); 987 } 988 if_statinc(ifp, if_ierrors); 989 goto skip; 990 } 991 992 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 993 if (__predict_false(len < IEEE80211_MIN_LEN || 994 len > ATHN_RXBUFSZ - sizeof(*ds))) { 995 DPRINTFN(DBG_RX, sc, "corrupted descriptor length=%zd\n", 996 len); 997 if_statinc(ifp, if_ierrors); 998 goto skip; 999 } 1000 1001 /* Allocate a new Rx buffer. */ 1002 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 1003 if (__predict_false(m1 == NULL)) { 1004 ic->ic_stats.is_rx_nobuf++; 1005 if_statinc(ifp, if_ierrors); 1006 goto skip; 1007 } 1008 1009 /* Unmap the old Rx buffer. */ 1010 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1011 1012 /* Map the new Rx buffer. */ 1013 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *), 1014 ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1015 if (__predict_false(error != 0)) { 1016 m_freem(m1); 1017 1018 /* Remap the old Rx buffer or panic. */ 1019 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 1020 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 1021 BUS_DMA_NOWAIT | BUS_DMA_READ); 1022 KASSERT(error != 0); 1023 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1024 if_statinc(ifp, if_ierrors); 1025 goto skip; 1026 } 1027 bf->bf_desc = mtod(m1, struct ar_rx_status *); 1028 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1029 1030 m = bf->bf_m; 1031 bf->bf_m = m1; 1032 1033 /* Finalize mbuf. */ 1034 m_set_rcvif(m, ifp); 1035 /* Strip Rx status descriptor from head. */ 1036 m->m_data = (void *)&ds[1]; 1037 m->m_pkthdr.len = m->m_len = len; 1038 1039 s = splnet(); 1040 1041 /* Grab a reference to the source node. */ 1042 wh = mtod(m, struct ieee80211_frame *); 1043 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1044 1045 /* Remove any HW padding after the 802.11 header. */ 1046 if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) { 1047 u_int hdrlen = ieee80211_anyhdrsize(wh); 1048 if (hdrlen & 3) { 1049 memmove((uint8_t *)wh + 2, wh, hdrlen); 1050 m_adj(m, 2); 1051 } 1052 } 1053 if (__predict_false(sc->sc_drvbpf != NULL)) 1054 ar9003_rx_radiotap(sc, m, ds); 1055 /* Trim 802.11 FCS after radiotap. */ 1056 m_adj(m, -IEEE80211_CRC_LEN); 1057 1058 /* Send the frame to the 802.11 layer. */ 1059 rssi = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 1060 rstamp = ds->ds_status3; 1061 ieee80211_input(ic, m, ni, rssi, rstamp); 1062 1063 /* Node is no longer needed. */ 1064 ieee80211_free_node(ni); 1065 1066 splx(s); 1067 1068 skip: 1069 /* Unlink this descriptor from head. */ 1070 SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list); 1071 memset(bf->bf_desc, 0, sizeof(*ds)); 1072 1073 /* Re-use this descriptor and link it to tail. */ 1074 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 1075 BUS_DMASYNC_PREREAD); 1076 1077 if (qid == ATHN_QID_LP) 1078 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 1079 else 1080 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 1081 AR_WRITE_BARRIER(sc); 1082 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 1083 1084 /* Re-enable Rx. */ 1085 AR_WRITE(sc, AR_CR, 0); 1086 AR_WRITE_BARRIER(sc); 1087 return 0; 1088 } 1089 1090 Static void 1091 ar9003_rx_intr(struct athn_softc *sc, int qid) 1092 { 1093 1094 while (ar9003_rx_process(sc, qid) == 0) 1095 continue; 1096 } 1097 1098 Static int 1099 ar9003_tx_process(struct athn_softc *sc) 1100 { 1101 struct ifnet *ifp = &sc->sc_if; 1102 struct athn_txq *txq; 1103 struct athn_node *an; 1104 struct athn_tx_buf *bf; 1105 struct ar_tx_status *ds; 1106 uint8_t qid, failcnt; 1107 1108 ds = &((struct ar_tx_status *)sc->sc_txsring)[sc->sc_txscur]; 1109 if (!(ds->ds_status8 & AR_TXS8_DONE)) 1110 return EBUSY; 1111 1112 sc->sc_txscur = (sc->sc_txscur + 1) % AR9003_NTXSTATUS; 1113 1114 /* Check that it is a valid Tx status descriptor. */ 1115 if ((ds->ds_info & (AR_TXI_DESC_ID_M | AR_TXI_DESC_TX)) != 1116 (SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX)) { 1117 memset(ds, 0, sizeof(*ds)); 1118 return 0; 1119 } 1120 /* Retrieve the queue that was used to send this PDU. */ 1121 qid = MS(ds->ds_info, AR_TXI_QCU_NUM); 1122 txq = &sc->sc_txq[qid]; 1123 1124 bf = SIMPLEQ_FIRST(&txq->head); 1125 if (bf == NULL || bf == txq->wait) { 1126 memset(ds, 0, sizeof(*ds)); 1127 return 0; 1128 } 1129 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1130 if_statinc(ifp, if_opackets); 1131 1132 sc->sc_tx_timer = 0; 1133 1134 if (ds->ds_status3 & AR_TXS3_EXCESSIVE_RETRIES) 1135 if_statinc(ifp, if_oerrors); 1136 1137 if (ds->ds_status3 & AR_TXS3_UNDERRUN) 1138 athn_inc_tx_trigger_level(sc); 1139 1140 /* Wakeup PA predistortion state machine. */ 1141 if (bf->bf_txflags & ATHN_TXFLAG_PAPRD) 1142 ar9003_paprd_tx_tone_done(sc); 1143 1144 an = (struct athn_node *)bf->bf_ni; 1145 /* 1146 * NB: the data fail count contains the number of un-acked tries 1147 * for the final series used. We must add the number of tries for 1148 * each series that was fully processed. 1149 */ 1150 failcnt = MS(ds->ds_status3, AR_TXS3_DATA_FAIL_CNT); 1151 /* NB: Assume two tries per series. */ 1152 failcnt += MS(ds->ds_status8, AR_TXS8_FINAL_IDX) * 2; 1153 1154 /* Update rate control statistics. */ 1155 an->amn.amn_txcnt++; 1156 if (failcnt > 0) 1157 an->amn.amn_retrycnt++; 1158 1159 DPRINTFN(DBG_TX, sc, "Tx done qid=%d status3=%d fail count=%d\n", 1160 qid, ds->ds_status3, failcnt); 1161 1162 /* Reset Tx status descriptor. */ 1163 memset(ds, 0, sizeof(*ds)); 1164 1165 /* Unmap Tx buffer. */ 1166 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1167 BUS_DMASYNC_POSTWRITE); 1168 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1169 1170 m_freem(bf->bf_m); 1171 bf->bf_m = NULL; 1172 ieee80211_free_node(bf->bf_ni); 1173 bf->bf_ni = NULL; 1174 1175 /* Link Tx buffer back to global free list. */ 1176 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1177 1178 /* Queue buffers that are waiting if there is new room. */ 1179 if (--txq->queued < AR9003_TX_QDEPTH && txq->wait != NULL) { 1180 AR_WRITE(sc, AR_QTXDP(qid), txq->wait->bf_daddr); 1181 AR_WRITE_BARRIER(sc); 1182 txq->wait = SIMPLEQ_NEXT(txq->wait, bf_list); 1183 } 1184 return 0; 1185 } 1186 1187 Static void 1188 ar9003_tx_intr(struct athn_softc *sc) 1189 { 1190 struct ifnet *ifp = &sc->sc_if; 1191 int s; 1192 1193 s = splnet(); 1194 1195 while (ar9003_tx_process(sc) == 0) 1196 continue; 1197 1198 if (!SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 1199 ifp->if_flags &= ~IFF_OACTIVE; 1200 ifp->if_start(ifp); /* in softint */ 1201 } 1202 1203 splx(s); 1204 } 1205 1206 #ifndef IEEE80211_STA_ONLY 1207 /* 1208 * Process Software Beacon Alert interrupts. 1209 */ 1210 Static int 1211 ar9003_swba_intr(struct athn_softc *sc) 1212 { 1213 struct ieee80211com *ic = &sc->sc_ic; 1214 struct ifnet *ifp = &sc->sc_if; 1215 struct ieee80211_node *ni = ic->ic_bss; 1216 struct athn_tx_buf *bf = sc->sc_bcnbuf; 1217 struct ieee80211_frame *wh; 1218 struct ieee80211_beacon_offsets bo; 1219 struct ar_tx_desc *ds; 1220 struct mbuf *m; 1221 uint32_t sum; 1222 uint8_t ridx, hwrate; 1223 int error, totlen; 1224 1225 #if notyet 1226 if (ic->ic_tim_mcast_pending && 1227 IF_IS_EMPTY(&ni->ni_savedq) && 1228 SIMPLEQ_EMPTY(&sc->sc_txq[ATHN_QID_CAB].head)) 1229 ic->ic_tim_mcast_pending = 0; 1230 #endif 1231 if (ic->ic_dtim_count == 0) 1232 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1233 else 1234 ic->ic_dtim_count--; 1235 1236 /* Make sure previous beacon has been sent. */ 1237 if (athn_tx_pending(sc, ATHN_QID_BEACON)) { 1238 DPRINTFN(DBG_INTR, sc, "beacon stuck\n"); 1239 return EBUSY; 1240 } 1241 /* Get new beacon. */ 1242 m = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 1243 if (__predict_false(m == NULL)) 1244 return ENOBUFS; 1245 /* Assign sequence number. */ 1246 /* XXX: use non-QoS tid? */ 1247 wh = mtod(m, struct ieee80211_frame *); 1248 *(uint16_t *)&wh->i_seq[0] = 1249 htole16(ic->ic_bss->ni_txseqs[0] << IEEE80211_SEQ_SEQ_SHIFT); 1250 ic->ic_bss->ni_txseqs[0]++; 1251 1252 /* Unmap and free old beacon if any. */ 1253 if (__predict_true(bf->bf_m != NULL)) { 1254 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1255 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1256 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1257 m_freem(bf->bf_m); 1258 bf->bf_m = NULL; 1259 } 1260 /* DMA map new beacon. */ 1261 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1262 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1263 if (__predict_false(error != 0)) { 1264 m_freem(m); 1265 return error; 1266 } 1267 bf->bf_m = m; 1268 1269 /* Setup Tx descriptor (simplified ar9003_tx()). */ 1270 ds = bf->bf_descs; 1271 memset(ds, 0, sizeof(*ds)); 1272 1273 ds->ds_info = 1274 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1275 SM(AR_TXI_DESC_NDWORDS, 23) | 1276 SM(AR_TXI_QCU_NUM, ATHN_QID_BEACON) | 1277 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1278 1279 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1280 ds->ds_ctl11 = SM(AR_TXC11_FRAME_LEN, totlen); 1281 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, AR_MAX_RATE_POWER); 1282 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, AR_FRAME_TYPE_BEACON); 1283 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1284 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, AR_ENCR_TYPE_CLEAR); 1285 1286 /* Write number of tries. */ 1287 ds->ds_ctl13 = SM(AR_TXC13_XMIT_DATA_TRIES0, 1); 1288 1289 /* Write Tx rate. */ 1290 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1291 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1292 hwrate = athn_rates[ridx].hwrate; 1293 ds->ds_ctl14 = SM(AR_TXC14_XMIT_RATE0, hwrate); 1294 1295 /* Write Tx chains. */ 1296 ds->ds_ctl18 = SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask); 1297 1298 ds->ds_segs[0].ds_data = bf->bf_map->dm_segs[0].ds_addr; 1299 /* Segment length must be a multiple of 4. */ 1300 ds->ds_segs[0].ds_ctl |= SM(AR_TXC_BUF_LEN, 1301 (bf->bf_map->dm_segs[0].ds_len + 3) & ~3); 1302 /* Compute Tx descriptor checksum. */ 1303 sum = ds->ds_info; 1304 sum += ds->ds_segs[0].ds_data; 1305 sum += ds->ds_segs[0].ds_ctl; 1306 sum = (sum >> 16) + (sum & 0xffff); 1307 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1308 1309 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1310 BUS_DMASYNC_PREWRITE); 1311 1312 /* Stop Tx DMA before putting the new beacon on the queue. */ 1313 athn_stop_tx_dma(sc, ATHN_QID_BEACON); 1314 1315 AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr); 1316 1317 for(;;) { 1318 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) 1319 break; 1320 1321 IF_DEQUEUE(&ni->ni_savedq, m); 1322 if (m == NULL) 1323 break; 1324 if (!IF_IS_EMPTY(&ni->ni_savedq)) { 1325 /* more queued frames, set the more data bit */ 1326 wh = mtod(m, struct ieee80211_frame *); 1327 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 1328 } 1329 1330 if (sc->sc_ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) { 1331 ieee80211_free_node(ni); 1332 if_statinc(ifp, if_oerrors); 1333 break; 1334 } 1335 } 1336 1337 /* Kick Tx. */ 1338 AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON); 1339 AR_WRITE_BARRIER(sc); 1340 return 0; 1341 } 1342 #endif 1343 1344 static int 1345 ar9003_get_intr_status(struct athn_softc *sc, uint32_t *intrp, uint32_t *syncp) 1346 { 1347 uint32_t intr, sync; 1348 1349 /* Get pending interrupts. */ 1350 intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE); 1351 if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) { 1352 intr = AR_READ(sc, AR_INTR_SYNC_CAUSE); 1353 if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0) 1354 return 0; /* Not for us. */ 1355 } 1356 1357 if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 1358 (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 1359 intr = AR_READ(sc, AR_ISR); 1360 else 1361 intr = 0; 1362 sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync; 1363 if (intr == 0 && sync == 0) 1364 return 0; /* Not for us. */ 1365 1366 *intrp = intr; 1367 *syncp = sync; 1368 return 1; 1369 } 1370 1371 Static int 1372 ar9003_intr_status(struct athn_softc *sc) 1373 { 1374 uint32_t intr, sync; 1375 1376 return ar9003_get_intr_status(sc, &intr, &sync); 1377 } 1378 1379 Static int 1380 ar9003_intr(struct athn_softc *sc) 1381 { 1382 uint32_t intr, sync; 1383 #ifndef IEEE80211_STA_ONLY 1384 int s; 1385 #endif 1386 1387 if (!ar9003_get_intr_status(sc, &intr, &sync)) 1388 return 0; 1389 1390 if (intr != 0) { 1391 if (intr & AR_ISR_BCNMISC) { 1392 uint32_t intr2 = AR_READ(sc, AR_ISR_S2); 1393 #ifdef notyet 1394 if (intr2 & AR_ISR_S2_TIM) 1395 /* TBD */; 1396 if (intr2 & AR_ISR_S2_TSFOOR) 1397 /* TBD */; 1398 if (intr2 & AR_ISR_S2_BB_WATCHDOG) 1399 /* TBD */; 1400 #else 1401 __USE(intr2); 1402 #endif 1403 } 1404 intr = AR_READ(sc, AR_ISR_RAC); 1405 if (intr == AR_INTR_SPURIOUS) 1406 return 1; 1407 1408 #ifndef IEEE80211_STA_ONLY 1409 if (intr & AR_ISR_SWBA) { 1410 s = splnet(); 1411 ar9003_swba_intr(sc); 1412 splx(s); 1413 } 1414 #endif 1415 if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 1416 ar9003_rx_intr(sc, ATHN_QID_LP); 1417 if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 1418 ar9003_rx_intr(sc, ATHN_QID_LP); 1419 if (intr & AR_ISR_HP_RXOK) 1420 ar9003_rx_intr(sc, ATHN_QID_HP); 1421 1422 if (intr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 1423 ar9003_tx_intr(sc); 1424 if (intr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) 1425 ar9003_tx_intr(sc); 1426 1427 if (intr & AR_ISR_GENTMR) { 1428 uint32_t intr5 = AR_READ(sc, AR_ISR_S5_S); 1429 #ifdef ATHN_DEBUG 1430 DPRINTFN(DBG_INTR, sc, 1431 "GENTMR trigger=%d thresh=%d\n", 1432 MS(intr5, AR_ISR_S5_GENTIMER_TRIG), 1433 MS(intr5, AR_ISR_S5_GENTIMER_THRESH)); 1434 #else 1435 __USE(intr5); 1436 #endif 1437 } 1438 } 1439 if (sync != 0) { 1440 if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 1441 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF); 1442 AR_WRITE(sc, AR_RC, 0); 1443 } 1444 1445 if ((sc->sc_flags & ATHN_FLAG_RFSILENT) && 1446 (sync & AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin))) { 1447 pmf_event_inject(sc->sc_dev, PMFE_RADIO_OFF); 1448 return 1; 1449 } 1450 1451 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync); 1452 (void)AR_READ(sc, AR_INTR_SYNC_CAUSE); 1453 } 1454 return 1; 1455 } 1456 1457 Static int 1458 ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 1459 int txflags) 1460 { 1461 struct ieee80211com *ic = &sc->sc_ic; 1462 struct ieee80211_key *k = NULL; 1463 struct ieee80211_frame *wh; 1464 struct athn_series series[4]; 1465 struct ar_tx_desc *ds; 1466 struct athn_txq *txq; 1467 struct athn_tx_buf *bf; 1468 struct athn_node *an = (void *)ni; 1469 struct mbuf *m1; 1470 uint32_t sum; 1471 uint16_t qos; 1472 uint8_t txpower, type, encrtype, ridx[4]; 1473 int i, error, totlen, hasqos, qid; 1474 1475 /* Grab a Tx buffer from our global free list. */ 1476 bf = SIMPLEQ_FIRST(&sc->sc_txbufs); 1477 KASSERT(bf != NULL); 1478 1479 /* Map 802.11 frame type to hardware frame type. */ 1480 wh = mtod(m, struct ieee80211_frame *); 1481 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1482 IEEE80211_FC0_TYPE_MGT) { 1483 /* NB: Beacons do not use ar9003_tx(). */ 1484 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1485 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1486 type = AR_FRAME_TYPE_PROBE_RESP; 1487 else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1488 IEEE80211_FC0_SUBTYPE_ATIM) 1489 type = AR_FRAME_TYPE_ATIM; 1490 else 1491 type = AR_FRAME_TYPE_NORMAL; 1492 } 1493 else if ((wh->i_fc[0] & 1494 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1495 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_PS_POLL)) { 1496 type = AR_FRAME_TYPE_PSPOLL; 1497 } 1498 else 1499 type = AR_FRAME_TYPE_NORMAL; 1500 1501 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1502 k = ieee80211_crypto_encap(ic, ni, m); 1503 if (k == NULL) 1504 return ENOBUFS; 1505 1506 /* packet header may have moved, reset our local pointer */ 1507 wh = mtod(m, struct ieee80211_frame *); 1508 } 1509 1510 /* XXX 2-byte padding for QoS and 4-addr headers. */ 1511 1512 /* Select the HW Tx queue to use for this frame. */ 1513 if ((hasqos = ieee80211_has_qos(wh))) { 1514 #ifdef notyet_edca 1515 uint8_t tid; 1516 1517 qos = ieee80211_get_qos(wh); 1518 tid = qos & IEEE80211_QOS_TID; 1519 qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)]; 1520 #else 1521 qos = ieee80211_get_qos(wh); 1522 qid = ATHN_QID_AC_BE; 1523 #endif /* notyet_edca */ 1524 } 1525 else if (type == AR_FRAME_TYPE_PSPOLL) { 1526 qos = 0; 1527 qid = ATHN_QID_PSPOLL; 1528 } 1529 else if (txflags & ATHN_TXFLAG_CAB) { 1530 qos = 0; 1531 qid = ATHN_QID_CAB; 1532 } 1533 else { 1534 qos = 0; 1535 qid = ATHN_QID_AC_BE; 1536 } 1537 txq = &sc->sc_txq[qid]; 1538 1539 /* Select the transmit rates to use for this frame. */ 1540 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1541 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 1542 IEEE80211_FC0_TYPE_DATA) { 1543 /* Use lowest rate for all tries. */ 1544 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1545 (ic->ic_curmode == IEEE80211_MODE_11A) ? 1546 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1547 } 1548 else if (ic->ic_fixed_rate != -1) { 1549 /* Use same fixed rate for all tries. */ 1550 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1551 sc->sc_fixed_ridx; 1552 } 1553 else { 1554 int txrate = ni->ni_txrate; 1555 /* Use fallback table of the node. */ 1556 for (i = 0; i < 4; i++) { 1557 ridx[i] = an->ridx[txrate]; 1558 txrate = an->fallback[txrate]; 1559 } 1560 } 1561 1562 if (__predict_false(sc->sc_drvbpf != NULL)) { 1563 struct athn_tx_radiotap_header *tap = &sc->sc_txtap; 1564 1565 tap->wt_flags = 0; 1566 /* Use initial transmit rate. */ 1567 tap->wt_rate = athn_rates[ridx[0]].rate; 1568 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1569 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1570 // XXX tap->wt_hwqueue = qid; 1571 if (ridx[0] != ATHN_RIDX_CCK1 && 1572 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1573 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1574 1575 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 1576 } 1577 1578 /* DMA map mbuf. */ 1579 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1580 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1581 if (__predict_false(error != 0)) { 1582 if (error != EFBIG) { 1583 aprint_error_dev(sc->sc_dev, 1584 "can't map mbuf (error %d)\n", error); 1585 m_freem(m); 1586 return error; 1587 } 1588 /* 1589 * DMA mapping requires too many DMA segments; linearize 1590 * mbuf in kernel virtual address space and retry. 1591 */ 1592 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1593 if (m1 == NULL) { 1594 m_freem(m); 1595 return ENOBUFS; 1596 } 1597 if (m->m_pkthdr.len > (int)MHLEN) { 1598 MCLGET(m1, M_DONTWAIT); 1599 if (!(m1->m_flags & M_EXT)) { 1600 m_freem(m); 1601 m_freem(m1); 1602 return ENOBUFS; 1603 } 1604 } 1605 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 1606 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1607 m_freem(m); 1608 m = m1; 1609 1610 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1611 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1612 if (error != 0) { 1613 aprint_error_dev(sc->sc_dev, 1614 "can't map mbuf (error %d)\n", error); 1615 m_freem(m); 1616 return error; 1617 } 1618 } 1619 bf->bf_m = m; 1620 bf->bf_ni = ni; 1621 bf->bf_txflags = txflags; 1622 1623 wh = mtod(m, struct ieee80211_frame *); 1624 1625 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1626 1627 /* Setup Tx descriptor. */ 1628 ds = bf->bf_descs; 1629 memset(ds, 0, sizeof(*ds)); 1630 1631 ds->ds_info = 1632 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1633 SM(AR_TXI_DESC_NDWORDS, 23) | 1634 SM(AR_TXI_QCU_NUM, qid) | 1635 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1636 1637 ds->ds_ctl11 = AR_TXC11_CLR_DEST_MASK; 1638 txpower = AR_MAX_RATE_POWER; /* Get from per-rate registers. */ 1639 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, txpower); 1640 1641 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, type); 1642 1643 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1644 (hasqos && (qos & IEEE80211_QOS_ACKPOLICY_MASK) == 1645 IEEE80211_QOS_ACKPOLICY_NOACK)) 1646 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1647 1648 #if notyet 1649 if (0 && k != NULL) { 1650 uintptr_t entry; 1651 1652 /* 1653 * Map 802.11 cipher to hardware encryption type and 1654 * compute MIC+ICV overhead. 1655 */ 1656 switch (k->k_cipher) { 1657 case IEEE80211_CIPHER_WEP40: 1658 case IEEE80211_CIPHER_WEP104: 1659 encrtype = AR_ENCR_TYPE_WEP; 1660 totlen += 4; 1661 break; 1662 case IEEE80211_CIPHER_TKIP: 1663 encrtype = AR_ENCR_TYPE_TKIP; 1664 totlen += 12; 1665 break; 1666 case IEEE80211_CIPHER_CCMP: 1667 encrtype = AR_ENCR_TYPE_AES; 1668 totlen += 8; 1669 break; 1670 default: 1671 panic("unsupported cipher"); 1672 } 1673 /* 1674 * NB: The key cache entry index is stored in the key 1675 * private field when the key is installed. 1676 */ 1677 entry = (uintptr_t)k->k_priv; 1678 ds->ds_ctl12 |= SM(AR_TXC12_DEST_IDX, entry); 1679 ds->ds_ctl11 |= AR_TXC11_DEST_IDX_VALID; 1680 } 1681 else 1682 #endif 1683 encrtype = AR_ENCR_TYPE_CLEAR; 1684 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, encrtype); 1685 1686 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 1687 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1688 /* NB: Group frames are sent using CCK in 802.11b/g. */ 1689 if (totlen > ic->ic_rtsthreshold) { 1690 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1691 } 1692 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1693 athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) { 1694 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1695 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1696 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1697 ds->ds_ctl11 |= AR_TXC11_CTS_ENABLE; 1698 } 1699 } 1700 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1701 /* Disable multi-rate retries when protection is used. */ 1702 ridx[1] = ridx[2] = ridx[3] = ridx[0]; 1703 } 1704 /* Setup multi-rate retries. */ 1705 for (i = 0; i < 4; i++) { 1706 series[i].hwrate = athn_rates[ridx[i]].hwrate; 1707 if (athn_rates[ridx[i]].phy == IEEE80211_T_DS && 1708 ridx[i] != ATHN_RIDX_CCK1 && 1709 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1710 series[i].hwrate |= 0x04; 1711 series[i].dur = 0; 1712 } 1713 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1714 /* Compute duration for each series. */ 1715 for (i = 0; i < 4; i++) { 1716 series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN, 1717 athn_rates[ridx[i]].rspridx, ic->ic_flags); 1718 } 1719 } 1720 /* If this is a PA training frame, select the Tx chain to use. */ 1721 if (__predict_false(txflags & ATHN_TXFLAG_PAPRD)) { 1722 ds->ds_ctl12 |= SM(AR_TXC12_PAPRD_CHAIN_MASK, 1723 1 << sc->sc_paprd_curchain); 1724 } 1725 1726 /* Write number of tries for each series. */ 1727 ds->ds_ctl13 = 1728 SM(AR_TXC13_XMIT_DATA_TRIES0, 2) | 1729 SM(AR_TXC13_XMIT_DATA_TRIES1, 2) | 1730 SM(AR_TXC13_XMIT_DATA_TRIES2, 2) | 1731 SM(AR_TXC13_XMIT_DATA_TRIES3, 4); 1732 1733 /* Tell HW to update duration field in 802.11 header. */ 1734 if (type != AR_FRAME_TYPE_PSPOLL) 1735 ds->ds_ctl13 |= AR_TXC13_DUR_UPDATE_ENA; 1736 1737 /* Write Tx rate for each series. */ 1738 ds->ds_ctl14 = 1739 SM(AR_TXC14_XMIT_RATE0, series[0].hwrate) | 1740 SM(AR_TXC14_XMIT_RATE1, series[1].hwrate) | 1741 SM(AR_TXC14_XMIT_RATE2, series[2].hwrate) | 1742 SM(AR_TXC14_XMIT_RATE3, series[3].hwrate); 1743 1744 /* Write duration for each series. */ 1745 ds->ds_ctl15 = 1746 SM(AR_TXC15_PACKET_DUR0, series[0].dur) | 1747 SM(AR_TXC15_PACKET_DUR1, series[1].dur); 1748 ds->ds_ctl16 = 1749 SM(AR_TXC16_PACKET_DUR2, series[2].dur) | 1750 SM(AR_TXC16_PACKET_DUR3, series[3].dur); 1751 1752 if ((sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) && 1753 ic->ic_curmode == IEEE80211_MODE_11A) { 1754 /* 1755 * In order to not exceed PCIe power requirements, we only 1756 * use two Tx chains for MCS0~15 on 5GHz band on these chips. 1757 */ 1758 ds->ds_ctl18 = 1759 SM(AR_TXC18_CHAIN_SEL0, 1760 (ridx[0] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1761 SM(AR_TXC18_CHAIN_SEL1, 1762 (ridx[1] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1763 SM(AR_TXC18_CHAIN_SEL2, 1764 (ridx[2] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1765 SM(AR_TXC18_CHAIN_SEL3, 1766 (ridx[3] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask); 1767 } 1768 else { 1769 /* Use the same Tx chains for all tries. */ 1770 ds->ds_ctl18 = 1771 SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask) | 1772 SM(AR_TXC18_CHAIN_SEL1, sc->sc_txchainmask) | 1773 SM(AR_TXC18_CHAIN_SEL2, sc->sc_txchainmask) | 1774 SM(AR_TXC18_CHAIN_SEL3, sc->sc_txchainmask); 1775 } 1776 #ifdef notyet 1777 #ifndef IEEE80211_NO_HT 1778 /* Use the same short GI setting for all tries. */ 1779 if (ic->ic_flags & IEEE80211_F_SHGI) 1780 ds->ds_ctl18 |= AR_TXC18_GI0123; 1781 /* Use the same channel width for all tries. */ 1782 if (ic->ic_flags & IEEE80211_F_CBW40) 1783 ds->ds_ctl18 |= AR_TXC18_2040_0123; 1784 #endif 1785 #endif 1786 1787 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1788 uint8_t protridx, hwrate; 1789 uint16_t dur = 0; 1790 1791 /* Use the same protection mode for all tries. */ 1792 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1793 ds->ds_ctl15 |= AR_TXC15_RTSCTS_QUAL01; 1794 ds->ds_ctl16 |= AR_TXC16_RTSCTS_QUAL23; 1795 } 1796 /* Select protection rate (suboptimal but ok). */ 1797 protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1798 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2; 1799 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1800 /* Account for CTS duration. */ 1801 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1802 athn_rates[protridx].rspridx, ic->ic_flags); 1803 } 1804 dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags); 1805 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1806 /* Account for ACK duration. */ 1807 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1808 athn_rates[ridx[0]].rspridx, ic->ic_flags); 1809 } 1810 /* Write protection frame duration and rate. */ 1811 ds->ds_ctl13 |= SM(AR_TXC13_BURST_DUR, dur); 1812 hwrate = athn_rates[protridx].hwrate; 1813 if (protridx == ATHN_RIDX_CCK2 && 1814 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1815 hwrate |= 0x04; 1816 ds->ds_ctl18 |= SM(AR_TXC18_RTSCTS_RATE, hwrate); 1817 } 1818 1819 ds->ds_ctl11 |= SM(AR_TXC11_FRAME_LEN, totlen); 1820 ds->ds_ctl19 = AR_TXC19_NOT_SOUNDING; 1821 1822 for (i = 0; i < bf->bf_map->dm_nsegs; i++) { 1823 ds->ds_segs[i].ds_data = bf->bf_map->dm_segs[i].ds_addr; 1824 ds->ds_segs[i].ds_ctl = SM(AR_TXC_BUF_LEN, 1825 bf->bf_map->dm_segs[i].ds_len); 1826 } 1827 /* Compute Tx descriptor checksum. */ 1828 sum = ds->ds_info + ds->ds_link; 1829 for (i = 0; i < 4; i++) { 1830 sum += ds->ds_segs[i].ds_data; 1831 sum += ds->ds_segs[i].ds_ctl; 1832 } 1833 sum = (sum >> 16) + (sum & 0xffff); 1834 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1835 1836 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1837 BUS_DMASYNC_PREWRITE); 1838 1839 DPRINTFN(DBG_TX, sc, 1840 "Tx qid=%d nsegs=%d ctl11=0x%x ctl12=0x%x ctl14=0x%x\n", 1841 qid, bf->bf_map->dm_nsegs, ds->ds_ctl11, ds->ds_ctl12, 1842 ds->ds_ctl14); 1843 1844 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 1845 SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list); 1846 1847 /* Queue buffer unless hardware FIFO is already full. */ 1848 if (++txq->queued <= AR9003_TX_QDEPTH) { 1849 AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr); 1850 AR_WRITE_BARRIER(sc); 1851 } 1852 else if (txq->wait == NULL) 1853 txq->wait = bf; 1854 return 0; 1855 } 1856 1857 Static void 1858 ar9003_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c) 1859 { 1860 uint32_t reg; 1861 1862 reg = IEEE80211_IS_CHAN_2GHZ(c) ? 1863 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 1864 if (IEEE80211_IS_CHAN_5GHZ(c) && 1865 (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 1866 reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE; 1867 } 1868 AR_WRITE(sc, AR_PHY_MODE, reg); 1869 AR_WRITE_BARRIER(sc); 1870 } 1871 1872 static __inline uint32_t 1873 ar9003_synth_delay(struct athn_softc *sc) 1874 { 1875 uint32_t synth_delay; 1876 1877 synth_delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY); 1878 if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B) 1879 synth_delay = (synth_delay * 4) / 22; 1880 else 1881 synth_delay = synth_delay / 10; /* in 100ns steps */ 1882 return synth_delay; 1883 } 1884 1885 Static int 1886 ar9003_rf_bus_request(struct athn_softc *sc) 1887 { 1888 int ntries; 1889 1890 /* Request RF Bus grant. */ 1891 AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1892 for (ntries = 0; ntries < 10000; ntries++) { 1893 if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN) 1894 return 0; 1895 DELAY(10); 1896 } 1897 DPRINTFN(DBG_RF, sc, "could not kill baseband Rx"); 1898 return ETIMEDOUT; 1899 } 1900 1901 Static void 1902 ar9003_rf_bus_release(struct athn_softc *sc) 1903 { 1904 /* Wait for the synthesizer to settle. */ 1905 DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar9003_synth_delay(sc)); 1906 1907 /* Release the RF Bus grant. */ 1908 AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0); 1909 AR_WRITE_BARRIER(sc); 1910 } 1911 1912 Static void 1913 ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c, 1914 struct ieee80211_channel *extc) 1915 { 1916 uint32_t phy; 1917 1918 phy = AR_READ(sc, AR_PHY_GEN_CTRL); 1919 phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | 1920 AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH; 1921 #ifndef IEEE80211_NO_HT 1922 if (extc != NULL) { 1923 phy |= AR_PHY_GC_DYN2040_EN; 1924 if (extc > c) /* XXX */ 1925 phy |= AR_PHY_GC_DYN2040_PRI_CH; 1926 } 1927 #endif 1928 /* Turn off Green Field detection for now. */ 1929 phy &= ~AR_PHY_GC_GF_DETECT_EN; 1930 AR_WRITE(sc, AR_PHY_GEN_CTRL, phy); 1931 1932 AR_WRITE(sc, AR_2040_MODE, 1933 (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0); 1934 1935 /* Set global transmit timeout. */ 1936 AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25)); 1937 /* Set carrier sense timeout. */ 1938 AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15)); 1939 AR_WRITE_BARRIER(sc); 1940 } 1941 1942 Static void 1943 ar9003_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c, 1944 struct ieee80211_channel *extc) 1945 { 1946 uint32_t coeff, exp, man, reg; 1947 1948 /* Set Delta Slope (exponent and mantissa). */ 1949 coeff = (100 << 24) / c->ic_freq; 1950 athn_get_delta_slope(coeff, &exp, &man); 1951 DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man); 1952 1953 reg = AR_READ(sc, AR_PHY_TIMING3); 1954 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); 1955 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); 1956 AR_WRITE(sc, AR_PHY_TIMING3, reg); 1957 1958 /* For Short GI, coeff is 9/10 that of normal coeff. */ 1959 coeff = (9 * coeff) / 10; 1960 athn_get_delta_slope(coeff, &exp, &man); 1961 DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man); 1962 1963 reg = AR_READ(sc, AR_PHY_SGI_DELTA); 1964 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); 1965 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); 1966 AR_WRITE(sc, AR_PHY_SGI_DELTA, reg); 1967 AR_WRITE_BARRIER(sc); 1968 } 1969 1970 Static void 1971 ar9003_enable_antenna_diversity(struct athn_softc *sc) 1972 { 1973 AR_SETBITS(sc, AR_PHY_CCK_DETECT, 1974 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1975 AR_WRITE_BARRIER(sc); 1976 } 1977 1978 Static void 1979 ar9003_init_baseband(struct athn_softc *sc) 1980 { 1981 uint32_t synth_delay; 1982 1983 synth_delay = ar9003_synth_delay(sc); 1984 /* Activate the PHY (includes baseband activate and synthesizer on). */ 1985 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 1986 AR_WRITE_BARRIER(sc); 1987 DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay); 1988 } 1989 1990 Static void 1991 ar9003_disable_phy(struct athn_softc *sc) 1992 { 1993 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1994 AR_WRITE_BARRIER(sc); 1995 } 1996 1997 Static void 1998 ar9003_init_chains(struct athn_softc *sc) 1999 { 2000 if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5) 2001 AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 2002 2003 /* Setup chain masks. */ 2004 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); 2005 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); 2006 2007 if (sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) { 2008 /* 2009 * All self-generated frames are sent using two Tx chains 2010 * on these chips to not exceed PCIe power requirements. 2011 */ 2012 AR_WRITE(sc, AR_SELFGEN_MASK, 0x3); 2013 } 2014 else 2015 AR_WRITE(sc, AR_SELFGEN_MASK, sc->sc_txchainmask); 2016 AR_WRITE_BARRIER(sc); 2017 } 2018 2019 Static void 2020 ar9003_set_rxchains(struct athn_softc *sc) 2021 { 2022 if (sc->sc_rxchainmask == 0x3 || sc->sc_rxchainmask == 0x5) { 2023 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); 2024 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); 2025 AR_WRITE_BARRIER(sc); 2026 } 2027 } 2028 2029 #ifdef notused 2030 Static void 2031 ar9003_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 2032 { 2033 /* Sign-extends 9-bit value (assumes upper bits are zeroes). */ 2034 #define SIGN_EXT(v) (((v) ^ 0x100) - 0x100) 2035 uint32_t reg; 2036 int i; 2037 2038 for (i = 0; i < sc->sc_nrxchains; i++) { 2039 reg = AR_READ(sc, AR_PHY_CCA(i)); 2040 nf[i] = MS(reg, AR_PHY_MINCCA_PWR); 2041 nf[i] = SIGN_EXT(nf[i]); 2042 2043 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 2044 nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR); 2045 nf_ext[i] = SIGN_EXT(nf_ext[i]); 2046 } 2047 #undef SIGN_EXT 2048 } 2049 #endif /* notused */ 2050 2051 #ifdef notused 2052 Static void 2053 ar9003_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 2054 { 2055 uint32_t reg; 2056 int i; 2057 2058 for (i = 0; i < sc->sc_nrxchains; i++) { 2059 reg = AR_READ(sc, AR_PHY_CCA(i)); 2060 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); 2061 AR_WRITE(sc, AR_PHY_CCA(i), reg); 2062 2063 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 2064 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); 2065 AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg); 2066 } 2067 AR_WRITE_BARRIER(sc); 2068 } 2069 #endif /* notused */ 2070 2071 #ifdef notused 2072 Static void 2073 ar9003_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c) 2074 { 2075 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2076 int16_t cca_min, cca_max; 2077 int i; 2078 2079 if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 2080 /* Noisefloor calibration not finished. */ 2081 return; 2082 } 2083 /* Noisefloor calibration is finished. */ 2084 ar9003_read_noisefloor(sc, nf, nf_ext); 2085 2086 if (IEEE80211_IS_CHAN_2GHZ(c)) { 2087 cca_min = sc->sc_cca_min_2g; 2088 cca_max = sc->sc_cca_max_2g; 2089 } 2090 else { 2091 cca_min = sc->sc_cca_min_5g; 2092 cca_max = sc->sc_cca_max_5g; 2093 } 2094 /* Update noisefloor history. */ 2095 for (i = 0; i < sc->sc_nrxchains; i++) { 2096 if (nf[i] < cca_min) 2097 nf[i] = cca_min; 2098 else if (nf[i] > cca_max) 2099 nf[i] = cca_max; 2100 if (nf_ext[i] < cca_min) 2101 nf_ext[i] = cca_min; 2102 else if (nf_ext[i] > cca_max) 2103 nf_ext[i] = cca_max; 2104 2105 sc->sc_nf_hist[sc->sc_nf_hist_cur].nf[i] = nf[i]; 2106 sc->sc_nf_hist[sc->sc_nf_hist_cur].nf_ext[i] = nf_ext[i]; 2107 } 2108 if (++sc->sc_nf_hist_cur >= ATHN_NF_CAL_HIST_MAX) 2109 sc->sc_nf_hist_cur = 0; 2110 } 2111 #endif /* notused */ 2112 2113 #ifdef notused 2114 Static void 2115 ar9003_bb_load_noisefloor(struct athn_softc *sc) 2116 { 2117 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2118 int i, ntries; 2119 2120 /* Write filtered noisefloor values. */ 2121 for (i = 0; i < sc->sc_nrxchains; i++) { 2122 nf[i] = sc->sc_nf_priv[i] * 2; 2123 nf_ext[i] = sc->sc_nf_ext_priv[i] * 2; 2124 } 2125 ar9003_write_noisefloor(sc, nf, nf_ext); 2126 2127 /* Load filtered noisefloor values into baseband. */ 2128 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2129 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2130 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2131 /* Wait for load to complete. */ 2132 for (ntries = 0; ntries < 1000; ntries++) { 2133 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) 2134 break; 2135 DELAY(10); 2136 } 2137 if (ntries == 1000) { 2138 DPRINTFN(DBG_RF, sc, "failed to load noisefloor values\n"); 2139 return; 2140 } 2141 2142 /* Restore noisefloor values to initial (max) values. */ 2143 for (i = 0; i < AR_MAX_CHAINS; i++) 2144 nf[i] = nf_ext[i] = -50 * 2; 2145 ar9003_write_noisefloor(sc, nf, nf_ext); 2146 } 2147 #endif /* notused */ 2148 2149 #ifdef notused 2150 Static void 2151 ar9300_noisefloor_calib(struct athn_softc *sc) 2152 { 2153 2154 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2155 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2156 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2157 } 2158 #endif /* notused */ 2159 2160 Static void 2161 ar9003_do_noisefloor_calib(struct athn_softc *sc) 2162 { 2163 2164 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2165 } 2166 2167 PUBLIC int 2168 ar9003_init_calib(struct athn_softc *sc) 2169 { 2170 uint8_t txchainmask, rxchainmask; 2171 uint32_t reg; 2172 int ntries; 2173 2174 /* Save chains masks. */ 2175 txchainmask = sc->sc_txchainmask; 2176 rxchainmask = sc->sc_rxchainmask; 2177 /* Configure hardware before calibration. */ 2178 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE) 2179 txchainmask = rxchainmask = 0x3; 2180 else 2181 txchainmask = rxchainmask = 0x7; 2182 ar9003_init_chains(sc); 2183 2184 /* Perform Tx IQ calibration. */ 2185 ar9003_calib_tx_iq(sc); 2186 /* Disable and re-enable the PHY chips. */ 2187 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2188 AR_WRITE_BARRIER(sc); 2189 DELAY(5); 2190 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 2191 2192 /* Calibrate the AGC. */ 2193 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 2194 /* Poll for offset calibration completion. */ 2195 for (ntries = 0; ntries < 10000; ntries++) { 2196 reg = AR_READ(sc, AR_PHY_AGC_CONTROL); 2197 if (!(reg & AR_PHY_AGC_CONTROL_CAL)) 2198 break; 2199 DELAY(10); 2200 } 2201 if (ntries == 10000) 2202 return ETIMEDOUT; 2203 2204 /* Restore chains masks. */ 2205 sc->sc_txchainmask = txchainmask; 2206 sc->sc_rxchainmask = rxchainmask; 2207 ar9003_init_chains(sc); 2208 2209 return 0; 2210 } 2211 2212 Static void 2213 ar9003_do_calib(struct athn_softc *sc) 2214 { 2215 uint32_t reg; 2216 2217 if (sc->sc_cur_calib_mask & ATHN_CAL_IQ) { 2218 reg = AR_READ(sc, AR_PHY_TIMING4); 2219 reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10); 2220 AR_WRITE(sc, AR_PHY_TIMING4, reg); 2221 AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 2222 AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); 2223 AR_WRITE_BARRIER(sc); 2224 } 2225 else if (sc->sc_cur_calib_mask & ATHN_CAL_TEMP) { 2226 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2227 AR_PHY_65NM_CH0_THERM_LOCAL); 2228 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2229 AR_PHY_65NM_CH0_THERM_START); 2230 AR_WRITE_BARRIER(sc); 2231 } 2232 } 2233 2234 Static void 2235 ar9003_next_calib(struct athn_softc *sc) 2236 { 2237 /* Check if we have any calibration in progress. */ 2238 if (sc->sc_cur_calib_mask != 0) { 2239 if (!(AR_READ(sc, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { 2240 /* Calibration completed for current sample. */ 2241 ar9003_calib_iq(sc); 2242 } 2243 } 2244 } 2245 2246 Static void 2247 ar9003_calib_iq(struct athn_softc *sc) 2248 { 2249 struct athn_iq_cal *cal; 2250 uint32_t reg, i_coff_denom, q_coff_denom; 2251 int32_t i_coff, q_coff; 2252 int i, iq_corr_neg; 2253 2254 for (i = 0; i < AR_MAX_CHAINS; i++) { 2255 cal = &sc->sc_calib.iq[i]; 2256 2257 /* Read IQ calibration measures (clear on read). */ 2258 cal->pwr_meas_i = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_0_B(i)); 2259 cal->pwr_meas_q = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_1_B(i)); 2260 cal->iq_corr_meas = 2261 (int32_t)AR_READ(sc, AR_PHY_IQ_ADC_MEAS_2_B(i)); 2262 } 2263 2264 for (i = 0; i < sc->sc_nrxchains; i++) { 2265 cal = &sc->sc_calib.iq[i]; 2266 2267 if (cal->pwr_meas_q == 0) 2268 continue; 2269 2270 if ((iq_corr_neg = cal->iq_corr_meas) < 0) 2271 cal->iq_corr_meas = -cal->iq_corr_meas; 2272 2273 i_coff_denom = 2274 (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 256; 2275 q_coff_denom = cal->pwr_meas_q / 64; 2276 2277 if (i_coff_denom == 0 || q_coff_denom == 0) 2278 continue; /* Prevents division by zero. */ 2279 2280 i_coff = cal->iq_corr_meas / i_coff_denom; 2281 q_coff = (cal->pwr_meas_i / q_coff_denom) - 64; 2282 2283 if (i_coff > 63) 2284 i_coff = 63; 2285 else if (i_coff < -63) 2286 i_coff = -63; 2287 /* Negate i_coff if iq_corr_meas is positive. */ 2288 if (!iq_corr_neg) 2289 i_coff = -i_coff; 2290 if (q_coff > 63) 2291 q_coff = 63; 2292 else if (q_coff < -63) 2293 q_coff = -63; 2294 2295 DPRINTFN(DBG_RF, sc, "IQ calibration for chain %d\n", i); 2296 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2297 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff); 2298 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff); 2299 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2300 } 2301 2302 /* Apply new settings. */ 2303 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2304 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); 2305 AR_WRITE_BARRIER(sc); 2306 2307 /* IQ calibration done. */ 2308 sc->sc_cur_calib_mask &= ~ATHN_CAL_IQ; 2309 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2310 } 2311 2312 #define DELPT 32 2313 Static int 2314 ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2]) 2315 { 2316 /* Sign-extends 12-bit value (assumes upper bits are zeroes). */ 2317 #define SIGN_EXT(v) (((v) ^ 0x800) - 0x800) 2318 #define SCALE (1 << 15) 2319 #define SHIFT (1 << 8) 2320 struct { 2321 int32_t m, p, c; 2322 } val[2][2]; 2323 int32_t mag[2][2], phs[2][2], cos[2], sin[2]; 2324 int32_t div, f1, f2, f3, m, p, c; 2325 int32_t txmag, txphs, rxmag, rxphs; 2326 int32_t q_coff, i_coff; 2327 int i, j; 2328 2329 /* Extract our twelve signed 12-bit values from res[] array. */ 2330 val[0][0].m = res[0] & 0xfff; 2331 val[0][0].p = (res[0] >> 12) & 0xfff; 2332 val[0][0].c = ((res[0] >> 24) & 0xff) | (res[1] & 0xf) << 8; 2333 2334 val[0][1].m = (res[1] >> 4) & 0xfff; 2335 val[0][1].p = res[2] & 0xfff; 2336 val[0][1].c = (res[2] >> 12) & 0xfff; 2337 2338 val[1][0].m = ((res[2] >> 24) & 0xff) | (res[3] & 0xf) << 8; 2339 val[1][0].p = (res[3] >> 4) & 0xfff; 2340 val[1][0].c = res[4] & 0xfff; 2341 2342 val[1][1].m = (res[4] >> 12) & 0xfff; 2343 val[1][1].p = ((res[4] >> 24) & 0xff) | (res[5] & 0xf) << 8; 2344 val[1][1].c = (res[5] >> 4) & 0xfff; 2345 2346 for (i = 0; i < 2; i++) { 2347 int32_t ymin, ymax; 2348 for (j = 0; j < 2; j++) { 2349 m = SIGN_EXT(val[i][j].m); 2350 p = SIGN_EXT(val[i][j].p); 2351 c = SIGN_EXT(val[i][j].c); 2352 2353 if (p == 0) 2354 return 1; /* Prevent division by 0. */ 2355 2356 mag[i][j] = (m * SCALE) / p; 2357 phs[i][j] = (c * SCALE) / p; 2358 } 2359 sin[i] = ((mag[i][0] - mag[i][1]) * SHIFT) / DELPT; 2360 cos[i] = ((phs[i][0] - phs[i][1]) * SHIFT) / DELPT; 2361 /* Find magnitude by approximation. */ 2362 ymin = MIN(abs(sin[i]), abs(cos[i])); 2363 ymax = MAX(abs(sin[i]), abs(cos[i])); 2364 div = ymax - (ymax / 32) + (ymin / 8) + (ymin / 4); 2365 if (div == 0) 2366 return 1; /* Prevent division by 0. */ 2367 /* Normalize sin and cos by magnitude. */ 2368 sin[i] = (sin[i] * SCALE) / div; 2369 cos[i] = (cos[i] * SCALE) / div; 2370 } 2371 2372 /* Compute IQ mismatch (solve 4x4 linear equation). */ 2373 f1 = cos[0] - cos[1]; 2374 f3 = sin[0] - sin[1]; 2375 f2 = (f1 * f1 + f3 * f3) / SCALE; 2376 if (f2 == 0) 2377 return 1; /* Prevent division by 0. */ 2378 2379 /* Compute Tx magnitude mismatch. */ 2380 txmag = (f1 * ( mag[0][0] - mag[1][0]) + 2381 f3 * ( phs[0][0] - phs[1][0])) / f2; 2382 /* Compute Tx phase mismatch. */ 2383 txphs = (f3 * (-mag[0][0] + mag[1][0]) + 2384 f1 * ( phs[0][0] - phs[1][0])) / f2; 2385 2386 if (txmag == SCALE) 2387 return 1; /* Prevent division by 0. */ 2388 2389 /* Compute Rx magnitude mismatch. */ 2390 rxmag = mag[0][0] - (cos[0] * txmag + sin[0] * txphs) / SCALE; 2391 /* Compute Rx phase mismatch. */ 2392 rxphs = phs[0][0] + (sin[0] * txmag - cos[0] * txphs) / SCALE; 2393 2394 if (-rxmag == SCALE) 2395 return 1; /* Prevent division by 0. */ 2396 2397 txmag = (txmag * SCALE) / (SCALE - txmag); 2398 txphs = -txphs; 2399 2400 q_coff = (txmag * 128) / SCALE; 2401 if (q_coff < -63) 2402 q_coff = -63; 2403 else if (q_coff > 63) 2404 q_coff = 63; 2405 i_coff = (txphs * 256) / SCALE; 2406 if (i_coff < -63) 2407 i_coff = -63; 2408 else if (i_coff > 63) 2409 i_coff = 63; 2410 coeff[0] = q_coff * 128 + i_coff; 2411 2412 rxmag = (-rxmag * SCALE) / (SCALE + rxmag); 2413 rxphs = -rxphs; 2414 2415 q_coff = (rxmag * 128) / SCALE; 2416 if (q_coff < -63) 2417 q_coff = -63; 2418 else if (q_coff > 63) 2419 q_coff = 63; 2420 i_coff = (rxphs * 256) / SCALE; 2421 if (i_coff < -63) 2422 i_coff = -63; 2423 else if (i_coff > 63) 2424 i_coff = 63; 2425 coeff[1] = q_coff * 128 + i_coff; 2426 2427 return 0; 2428 #undef SHIFT 2429 #undef SCALE 2430 #undef SIGN_EXT 2431 } 2432 2433 Static int 2434 ar9003_calib_tx_iq(struct athn_softc *sc) 2435 { 2436 uint32_t reg; 2437 int32_t res[6], coeff[2]; 2438 int i, j, ntries; 2439 2440 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1); 2441 reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT); 2442 AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg); 2443 2444 /* Start Tx IQ calibration. */ 2445 AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL); 2446 /* Wait for completion. */ 2447 for (ntries = 0; ntries < 10000; ntries++) { 2448 reg = AR_READ(sc, AR_PHY_TX_IQCAL_START); 2449 if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL)) 2450 break; 2451 DELAY(10); 2452 } 2453 if (ntries == 10000) 2454 return ETIMEDOUT; 2455 2456 for (i = 0; i < sc->sc_ntxchains; i++) { 2457 /* Read Tx IQ calibration status for this chain. */ 2458 reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i)); 2459 if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED) 2460 return EIO; 2461 /* 2462 * Read Tx IQ calibration results for this chain. 2463 * This consists in twelve signed 12-bit values. 2464 */ 2465 for (j = 0; j < 3; j++) { 2466 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2467 AR_PHY_CHAN_INFO_TAB_S2_READ); 2468 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2469 res[j * 2 + 0] = reg; 2470 2471 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2472 AR_PHY_CHAN_INFO_TAB_S2_READ); 2473 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2474 res[j * 2 + 1] = reg & 0xffff; 2475 } 2476 2477 /* Compute Tx IQ correction. */ 2478 if (ar9003_get_iq_corr(sc, res, coeff) != 0) 2479 return EIO; 2480 2481 /* Write Tx IQ correction coefficients. */ 2482 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)); 2483 reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, 2484 coeff[0]); 2485 AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg); 2486 2487 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2488 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF, 2489 coeff[1] >> 7); 2490 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF, 2491 coeff[1]); 2492 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2493 AR_WRITE_BARRIER(sc); 2494 } 2495 2496 /* Enable Tx IQ correction. */ 2497 AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_3, 2498 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN); 2499 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2500 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN); 2501 AR_WRITE_BARRIER(sc); 2502 return 0; 2503 } 2504 #undef DELPT 2505 2506 /*- 2507 * The power amplifier predistortion state machine works as follows: 2508 * 1) Disable digital predistorters for all Tx chains 2509 * 2) Repeat steps 3~7 for all Tx chains 2510 * 3) Force Tx gain to that of training signal 2511 * 4) Send training signal (asynchronous) 2512 * 5) Wait for training signal to complete (asynchronous) 2513 * 6) Read PA measurements (input power, output power, output phase) 2514 * 7) Compute the predistortion function that linearizes PA output 2515 * 8) Write predistortion functions to hardware tables for all Tx chains 2516 * 9) Enable digital predistorters for all Tx chains 2517 */ 2518 #ifdef notused 2519 Static void 2520 ar9003_paprd_calib(struct athn_softc *sc, struct ieee80211_channel *c) 2521 { 2522 static const int scaling[] = { 2523 261376, 248079, 233759, 220464, 2524 208194, 196949, 185706, 175487 2525 }; 2526 struct athn_ops *ops = &sc->sc_ops; 2527 uint32_t reg, ht20mask, ht40mask; 2528 int i; 2529 2530 /* Read PA predistortion masks from ROM. */ 2531 ops->get_paprd_masks(sc, c, &ht20mask, &ht40mask); 2532 2533 /* AM-to-AM: amplifier's amplitude characteristic. */ 2534 reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM); 2535 reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask); 2536 AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg); 2537 2538 /* AM-to-PM: amplifier's phase transfer characteristic. */ 2539 reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM); 2540 reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask); 2541 AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg); 2542 2543 reg = AR_READ(sc, AR_PHY_PAPRD_HT40); 2544 reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask); 2545 AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg); 2546 2547 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2548 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2549 AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE); 2550 2551 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i)); 2552 reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181); 2553 reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361); 2554 reg &= ~AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA; 2555 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA; 2556 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA; 2557 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg); 2558 2559 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i)); 2560 reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3); 2561 AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg); 2562 } 2563 2564 /* Disable all digital predistorters during calibration. */ 2565 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2566 AR_CLRBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2567 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 2568 } 2569 AR_WRITE_BARRIER(sc); 2570 2571 /* 2572 * Configure training signal. 2573 */ 2574 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1); 2575 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28); 2576 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30); 2577 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE; 2578 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE; 2579 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE; 2580 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE; 2581 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE; 2582 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg); 2583 2584 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL2, 147); 2585 2586 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3); 2587 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4); 2588 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4); 2589 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7); 2590 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1); 2591 if (AR_SREV_9485(sc)) 2592 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3); 2593 else 2594 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6); 2595 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15); 2596 reg |= AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE; 2597 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg); 2598 2599 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4); 2600 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0); 2601 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400); 2602 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100); 2603 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg); 2604 2605 for (i = 0; i < __arraycount(scaling); i++) { 2606 reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i)); 2607 reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]); 2608 AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg); 2609 } 2610 2611 /* Save Tx gain table. */ 2612 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE; i++) 2613 sc->sc_txgain[i] = AR_READ(sc, AR_PHY_TXGAIN_TABLE(i)); 2614 2615 /* Set Tx power of training signal (use setting for MCS0). */ 2616 sc->sc_trainpow = MS(AR_READ(sc, AR_PHY_PWRTX_RATE5), 2617 AR_PHY_PWRTX_RATE5_POWERTXHT20_0) - 4; 2618 2619 /* 2620 * Start PA predistortion calibration state machine. 2621 */ 2622 /* Find first available Tx chain. */ 2623 sc->sc_paprd_curchain = 0; 2624 while (!(sc->sc_txchainmask & (1 << sc->sc_paprd_curchain))) 2625 sc->sc_paprd_curchain++; 2626 2627 /* Make sure training done bit is clear. */ 2628 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 2629 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 2630 AR_WRITE_BARRIER(sc); 2631 2632 /* Transmit training signal. */ 2633 ar9003_paprd_tx_tone(sc); 2634 } 2635 #endif /* notused */ 2636 2637 Static int 2638 ar9003_get_desired_txgain(struct athn_softc *sc, int chain, int pow) 2639 { 2640 int32_t scale, atemp, avolt, tempcal, voltcal, temp, volt; 2641 int32_t tempcorr, voltcorr; 2642 uint32_t reg; 2643 int8_t delta; 2644 2645 scale = MS(AR_READ(sc, AR_PHY_TPC_12), 2646 AR_PHY_TPC_12_DESIRED_SCALE_HT40_5); 2647 2648 reg = AR_READ(sc, AR_PHY_TPC_19); 2649 atemp = MS(reg, AR_PHY_TPC_19_ALPHA_THERM); 2650 avolt = MS(reg, AR_PHY_TPC_19_ALPHA_VOLT); 2651 2652 reg = AR_READ(sc, AR_PHY_TPC_18); 2653 tempcal = MS(reg, AR_PHY_TPC_18_THERM_CAL); 2654 voltcal = MS(reg, AR_PHY_TPC_18_VOLT_CAL); 2655 2656 reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4); 2657 temp = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_THERM); 2658 volt = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_VOLT); 2659 2660 delta = (int8_t)MS(AR_READ(sc, AR_PHY_TPC_11_B(chain)), 2661 AR_PHY_TPC_11_OLPC_GAIN_DELTA); 2662 2663 /* Compute temperature and voltage correction. */ 2664 tempcorr = (atemp * (temp - tempcal) + 128) / 256; 2665 voltcorr = (avolt * (volt - voltcal) + 64) / 128; 2666 2667 /* Compute desired Tx gain. */ 2668 return pow - delta - tempcorr - voltcorr + scale; 2669 } 2670 2671 Static void 2672 ar9003_force_txgain(struct athn_softc *sc, uint32_t txgain) 2673 { 2674 uint32_t reg; 2675 2676 reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN); 2677 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN, 2678 MS(txgain, AR_PHY_TXGAIN_TXBB1DBGAIN)); 2679 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN, 2680 MS(txgain, AR_PHY_TXGAIN_TXBB6DBGAIN)); 2681 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN, 2682 MS(txgain, AR_PHY_TXGAIN_TXMXRGAIN)); 2683 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA, 2684 MS(txgain, AR_PHY_TXGAIN_PADRVGNA)); 2685 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB, 2686 MS(txgain, AR_PHY_TXGAIN_PADRVGNB)); 2687 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC, 2688 MS(txgain, AR_PHY_TXGAIN_PADRVGNC)); 2689 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND, 2690 MS(txgain, AR_PHY_TXGAIN_PADRVGND)); 2691 reg &= ~AR_PHY_TX_FORCED_GAIN_ENABLE_PAL; 2692 reg &= ~AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN; 2693 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg); 2694 2695 reg = AR_READ(sc, AR_PHY_TPC_1); 2696 reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0); 2697 reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN; 2698 AR_WRITE(sc, AR_PHY_TPC_1, reg); 2699 AR_WRITE_BARRIER(sc); 2700 } 2701 2702 Static void 2703 ar9003_set_training_gain(struct athn_softc *sc, int chain) 2704 { 2705 size_t i; 2706 int gain; 2707 2708 /* 2709 * Get desired gain for training signal power (take into account 2710 * current temperature/voltage). 2711 */ 2712 gain = ar9003_get_desired_txgain(sc, chain, sc->sc_trainpow); 2713 /* Find entry in table. */ 2714 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE - 1; i++) 2715 if ((int)MS(sc->sc_txgain[i], AR_PHY_TXGAIN_INDEX) >= gain) 2716 break; 2717 ar9003_force_txgain(sc, sc->sc_txgain[i]); 2718 } 2719 2720 Static int 2721 ar9003_paprd_tx_tone(struct athn_softc *sc) 2722 { 2723 #define TONE_LEN 1800 2724 struct ieee80211com *ic = &sc->sc_ic; 2725 struct ieee80211_frame *wh; 2726 struct ieee80211_node *ni; 2727 struct mbuf *m; 2728 int error; 2729 2730 /* Build a Null (no data) frame of TONE_LEN bytes. */ 2731 m = MCLGETI(NULL, M_DONTWAIT, NULL, TONE_LEN); 2732 if (m == NULL) 2733 return ENOBUFS; 2734 memset(mtod(m, void *), 0, TONE_LEN); 2735 wh = mtod(m, struct ieee80211_frame *); 2736 wh->i_fc[0] = IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_NODATA; 2737 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 2738 *(uint16_t *)wh->i_dur = htole16(10); /* XXX */ 2739 IEEE80211_ADDR_COPY(wh->i_addr1, ic->ic_myaddr); 2740 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 2741 IEEE80211_ADDR_COPY(wh->i_addr3, ic->ic_myaddr); 2742 m->m_pkthdr.len = m->m_len = TONE_LEN; 2743 2744 /* Set gain of training signal. */ 2745 ar9003_set_training_gain(sc, sc->sc_paprd_curchain); 2746 2747 /* Transmit training signal. */ 2748 ni = ieee80211_ref_node(ic->ic_bss); 2749 if ((error = ar9003_tx(sc, m, ni, ATHN_TXFLAG_PAPRD)) != 0) 2750 ieee80211_free_node(ni); 2751 return error; 2752 #undef TONE_LEN 2753 } 2754 2755 static __inline int 2756 get_scale(int val) 2757 { 2758 int log = 0; 2759 2760 /* Find the log base 2 (position of highest bit set). */ 2761 while (val >>= 1) 2762 log++; 2763 2764 return (log > 10) ? log - 10 : 0; 2765 } 2766 2767 /* 2768 * Compute predistortion function to linearize power amplifier output based 2769 * on feedback from training signal. 2770 */ 2771 Static int 2772 ar9003_compute_predistortion(struct athn_softc *sc, const uint32_t *lo, 2773 const uint32_t *hi) 2774 { 2775 #define NBINS 23 2776 int chain = sc->sc_paprd_curchain; 2777 int x[NBINS + 1], y[NBINS + 1], t[NBINS + 1]; 2778 int b1[NBINS + 1], b2[NBINS + 1], xtilde[NBINS + 1]; 2779 int nsamples, txsum, rxsum, rosum, maxidx; 2780 int order, order5x, order5xrem, order3x, order3xrem, y5, y3; 2781 int icept, G, I, L, M, angle, xnonlin, y2, y4, sumy2, sumy4; 2782 int alpha, beta, scale, Qalpha, Qbeta, Qscale, Qx, Qb1, Qb2; 2783 int tavg, ttilde, maxb1abs, maxb2abs, maxxtildeabs, in; 2784 int tmp, i; 2785 2786 /* Set values at origin. */ 2787 x[0] = y[0] = t[0] = 0; 2788 2789 #define SCALE 32 2790 maxidx = 0; 2791 for (i = 0; i < NBINS; i++) { 2792 nsamples = lo[i] & 0xffff; 2793 /* Skip bins that contain 16 or less samples. */ 2794 if (nsamples <= 16) { 2795 x[i + 1] = y[i + 1] = t[i + 1] = 0; 2796 continue; 2797 } 2798 txsum = (hi[i] & 0x7ff) << 16 | lo[i] >> 16; 2799 rxsum = (lo[i + NBINS] & 0xffff) << 5 | 2800 ((hi[i] >> 11) & 0x1f); 2801 rosum = (hi[i + NBINS] & 0x7ff) << 16 | hi[i + NBINS] >> 16; 2802 /* Sign-extend 27-bit value. */ 2803 rosum = (rosum ^ 0x4000000) - 0x4000000; 2804 2805 txsum *= SCALE; 2806 rxsum *= SCALE; 2807 rosum *= SCALE; 2808 2809 x[i + 1] = ((txsum + nsamples) / nsamples + SCALE) / SCALE; 2810 y[i + 1] = ((rxsum + nsamples) / nsamples + SCALE) / SCALE + 2811 SCALE * maxidx + SCALE / 2; 2812 t[i + 1] = (rosum + nsamples) / nsamples; 2813 maxidx++; 2814 } 2815 #undef SCALE 2816 2817 #define SCALE_LOG 8 2818 #define SCALE (1 << SCALE_LOG) 2819 if (x[6] == x[3]) 2820 return 1; /* Prevent division by 0. */ 2821 G = ((y[6] - y[3]) * SCALE + (x[6] - x[3])) / (x[6] - x[3]); 2822 if (G == 0) 2823 return 1; /* Prevent division by 0. */ 2824 2825 sc->sc_gain1[chain] = G; /* Save low signal gain. */ 2826 2827 /* Find interception point. */ 2828 icept = (G * (x[0] - x[3]) + SCALE) / SCALE + y[3]; 2829 for (i = 0; i <= 3; i++) { 2830 y[i] = i * 32; 2831 x[i] = (y[i] * SCALE + G) / G; 2832 } 2833 for (i = 4; i <= maxidx; i++) 2834 y[i] -= icept; 2835 2836 xnonlin = x[maxidx] - (y[maxidx] * SCALE + G) / G; 2837 order = (xnonlin + y[maxidx]) / y[maxidx]; 2838 if (order == 0) 2839 M = 10; 2840 else if (order == 1) 2841 M = 9; 2842 else 2843 M = 8; 2844 2845 I = (maxidx >= 16) ? 7 : maxidx / 2; 2846 L = maxidx - I; 2847 2848 sumy2 = sumy4 = y2 = y4 = 0; 2849 for (i = 0; i <= L; i++) { 2850 if (y[i + I] == 0) 2851 return 1; /* Prevent division by 0. */ 2852 2853 xnonlin = x[i + I] - ((y[i + I] * SCALE) + G) / G; 2854 xtilde[i] = ((xnonlin << M) + y[i + I]) / y[i + I]; 2855 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2856 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2857 2858 y2 = (y[i + I] * y[i + I] + SCALE * SCALE) / (SCALE * SCALE); 2859 2860 sumy2 += y2; 2861 sumy4 += y2 * y2; 2862 2863 b1[i] = y2 * (L + 1); 2864 b2[i] = y2; 2865 } 2866 for (i = 0; i <= L; i++) { 2867 b1[i] -= sumy2; 2868 b2[i] = sumy4 - sumy2 * b2[i]; 2869 } 2870 2871 maxxtildeabs = maxb1abs = maxb2abs = 0; 2872 for (i = 0; i <= L; i++) { 2873 tmp = abs(xtilde[i]); 2874 if (tmp > maxxtildeabs) 2875 maxxtildeabs = tmp; 2876 2877 tmp = abs(b1[i]); 2878 if (tmp > maxb1abs) 2879 maxb1abs = tmp; 2880 2881 tmp = abs(b2[i]); 2882 if (tmp > maxb2abs) 2883 maxb2abs = tmp; 2884 } 2885 Qx = get_scale(maxxtildeabs); 2886 Qb1 = get_scale(maxb1abs); 2887 Qb2 = get_scale(maxb2abs); 2888 for (i = 0; i <= L; i++) { 2889 xtilde[i] /= 1 << Qx; 2890 b1[i] /= 1 << Qb1; 2891 b2[i] /= 1 << Qb2; 2892 } 2893 2894 alpha = beta = 0; 2895 for (i = 0; i <= L; i++) { 2896 alpha += b1[i] * xtilde[i]; 2897 beta += b2[i] * xtilde[i]; 2898 } 2899 2900 scale = ((y4 / SCALE_LOG) * (L + 1) - 2901 (y2 / SCALE_LOG) * sumy2) * SCALE_LOG; 2902 2903 Qscale = get_scale(abs(scale)); 2904 scale /= 1 << Qscale; 2905 Qalpha = get_scale(abs(alpha)); 2906 alpha /= 1 << Qalpha; 2907 Qbeta = get_scale(abs(beta)); 2908 beta /= 1 << Qbeta; 2909 2910 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale; 2911 order5x = 1 << (order / 5); 2912 order5xrem = 1 << (order % 5); 2913 2914 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale; 2915 order3x = 1 << (order / 3); 2916 order3xrem = 1 << (order % 3); 2917 2918 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2919 tmp = i * 32; 2920 2921 /* Fifth order. */ 2922 y5 = ((beta * tmp) / 64) / order5x; 2923 y5 = (y5 * tmp) / order5x; 2924 y5 = (y5 * tmp) / order5x; 2925 y5 = (y5 * tmp) / order5x; 2926 y5 = (y5 * tmp) / order5x; 2927 y5 = y5 / order5xrem; 2928 2929 /* Third oder. */ 2930 y3 = (alpha * tmp) / order3x; 2931 y3 = (y3 * tmp) / order3x; 2932 y3 = (y3 * tmp) / order3x; 2933 y3 = y3 / order3xrem; 2934 2935 in = y5 + y3 + (SCALE * tmp) / G; 2936 if (i >= 2 && in < sc->sc_pa_in[chain][i - 1]) { 2937 in = sc->sc_pa_in[chain][i - 1] + 2938 (sc->sc_pa_in[chain][i - 1] - 2939 sc->sc_pa_in[chain][i - 2]); 2940 } 2941 if (in > 1400) 2942 in = 1400; 2943 sc->sc_pa_in[chain][i] = in; 2944 } 2945 2946 /* Compute average theta of first 5 bins (linear region). */ 2947 tavg = 0; 2948 for (i = 1; i <= 5; i++) 2949 tavg += t[i]; 2950 tavg /= 5; 2951 for (i = 1; i <= 5; i++) 2952 t[i] = 0; 2953 for (i = 6; i <= maxidx; i++) 2954 t[i] -= tavg; 2955 2956 alpha = beta = 0; 2957 for (i = 0; i <= L; i++) { 2958 ttilde = ((t[i + I] << M) + y[i + I]) / y[i + I]; 2959 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2960 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2961 2962 alpha += b2[i] * ttilde; 2963 beta += b1[i] * ttilde; 2964 } 2965 2966 Qalpha = get_scale(abs(alpha)); 2967 alpha /= 1 << Qalpha; 2968 Qbeta = get_scale(abs(beta)); 2969 beta /= 1 << Qbeta; 2970 2971 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale + 5; 2972 order5x = 1 << (order / 5); 2973 order5xrem = 1 << (order % 5); 2974 2975 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale + 5; 2976 order3x = 1 << (order / 3); 2977 order3xrem = 1 << (order % 3); 2978 2979 for (i = 0; i <= 4; i++) 2980 sc->sc_angle[chain][i] = 0; /* Linear at that range. */ 2981 for (i = 5; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2982 tmp = i * 32; 2983 2984 /* Fifth order. */ 2985 if (beta > 0) 2986 y5 = (((beta * tmp - 64) / 64) - order5x) / order5x; 2987 else 2988 y5 = (((beta * tmp - 64) / 64) + order5x) / order5x; 2989 y5 = (y5 * tmp) / order5x; 2990 y5 = (y5 * tmp) / order5x; 2991 y5 = (y5 * tmp) / order5x; 2992 y5 = (y5 * tmp) / order5x; 2993 y5 = y5 / order5xrem; 2994 2995 /* Third oder. */ 2996 if (beta > 0) /* XXX alpha? */ 2997 y3 = (alpha * tmp - order3x) / order3x; 2998 else 2999 y3 = (alpha * tmp + order3x) / order3x; 3000 y3 = (y3 * tmp) / order3x; 3001 y3 = (y3 * tmp) / order3x; 3002 y3 = y3 / order3xrem; 3003 3004 angle = y5 + y3; 3005 if (angle < -150) 3006 angle = -150; 3007 else if (angle > 150) 3008 angle = 150; 3009 sc->sc_angle[chain][i] = angle; 3010 } 3011 /* Angle for entry 4 is derived from angle for entry 5. */ 3012 sc->sc_angle[chain][4] = (sc->sc_angle[chain][5] + 2) / 2; 3013 3014 return 0; 3015 #undef SCALE 3016 #undef SCALE_LOG 3017 #undef NBINS 3018 } 3019 3020 Static void 3021 ar9003_enable_predistorter(struct athn_softc *sc, int chain) 3022 { 3023 uint32_t reg; 3024 int i; 3025 3026 /* Write digital predistorter lookup table. */ 3027 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 3028 AR_WRITE(sc, AR_PHY_PAPRD_MEM_TAB_B(chain, i), 3029 SM(AR_PHY_PAPRD_PA_IN, sc->sc_pa_in[chain][i]) | 3030 SM(AR_PHY_PAPRD_ANGLE, sc->sc_angle[chain][i])); 3031 } 3032 3033 reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain)); 3034 reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->sc_gain1[chain]); 3035 AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg); 3036 3037 /* Indicate Tx power used for calibration (training signal). */ 3038 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain)); 3039 reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->sc_trainpow); 3040 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg); 3041 3042 /* Enable digital predistorter for this chain. */ 3043 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(chain), 3044 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 3045 AR_WRITE_BARRIER(sc); 3046 } 3047 3048 Static void 3049 ar9003_paprd_enable(struct athn_softc *sc) 3050 { 3051 int i; 3052 3053 /* Enable digital predistorters for all Tx chains. */ 3054 for (i = 0; i < AR9003_MAX_CHAINS; i++) 3055 if (sc->sc_txchainmask & (1 << i)) 3056 ar9003_enable_predistorter(sc, i); 3057 } 3058 3059 /* 3060 * This function is called when our training signal has been sent. 3061 */ 3062 Static void 3063 ar9003_paprd_tx_tone_done(struct athn_softc *sc) 3064 { 3065 uint32_t lo[48], hi[48]; 3066 size_t i; 3067 3068 /* Make sure training is complete. */ 3069 if (!(AR_READ(sc, AR_PHY_PAPRD_TRAINER_STAT1) & 3070 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE)) 3071 return; 3072 3073 /* Read feedback from training signal. */ 3074 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 3075 for (i = 0; i < __arraycount(lo); i++) 3076 lo[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 3077 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 3078 for (i = 0; i < __arraycount(hi); i++) 3079 hi[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 3080 3081 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 3082 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 3083 3084 /* Compute predistortion function based on this feedback. */ 3085 if (ar9003_compute_predistortion(sc, lo, hi) != 0) 3086 return; 3087 3088 /* Get next available Tx chain. */ 3089 while (++sc->sc_paprd_curchain < AR9003_MAX_CHAINS) 3090 if (sc->sc_txchainmask & (1 << sc->sc_paprd_curchain)) 3091 break; 3092 if (sc->sc_paprd_curchain == AR9003_MAX_CHAINS) { 3093 /* All Tx chains measured; enable digital predistortion. */ 3094 ar9003_paprd_enable(sc); 3095 } 3096 else /* Measure next Tx chain. */ 3097 ar9003_paprd_tx_tone(sc); 3098 } 3099 3100 PUBLIC void 3101 ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT]) 3102 { 3103 3104 /* Make sure forced gain is disabled. */ 3105 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, 0); 3106 3107 AR_WRITE(sc, AR_PHY_PWRTX_RATE1, 3108 (power[ATHN_POWER_OFDM18 ] & 0x3f) << 24 | 3109 (power[ATHN_POWER_OFDM12 ] & 0x3f) << 16 | 3110 (power[ATHN_POWER_OFDM9 ] & 0x3f) << 8 | 3111 (power[ATHN_POWER_OFDM6 ] & 0x3f)); 3112 AR_WRITE(sc, AR_PHY_PWRTX_RATE2, 3113 (power[ATHN_POWER_OFDM54 ] & 0x3f) << 24 | 3114 (power[ATHN_POWER_OFDM48 ] & 0x3f) << 16 | 3115 (power[ATHN_POWER_OFDM36 ] & 0x3f) << 8 | 3116 (power[ATHN_POWER_OFDM24 ] & 0x3f)); 3117 AR_WRITE(sc, AR_PHY_PWRTX_RATE3, 3118 (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 | 3119 (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 | 3120 /* NB: No eXtended Range for AR9003. */ 3121 (power[ATHN_POWER_CCK1_LP ] & 0x3f)); 3122 AR_WRITE(sc, AR_PHY_PWRTX_RATE4, 3123 (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 | 3124 (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 | 3125 (power[ATHN_POWER_CCK55_SP] & 0x3f) << 8 | 3126 (power[ATHN_POWER_CCK55_LP] & 0x3f)); 3127 /* 3128 * NB: AR_PHY_PWRTX_RATE5 needs to be written even if HT is disabled 3129 * because it is read by PA predistortion functions. 3130 */ 3131 AR_WRITE(sc, AR_PHY_PWRTX_RATE5, 3132 (power[ATHN_POWER_HT20( 5)] & 0x3f) << 24 | 3133 (power[ATHN_POWER_HT20( 4)] & 0x3f) << 16 | 3134 (power[ATHN_POWER_HT20( 1)] & 0x3f) << 8 | 3135 (power[ATHN_POWER_HT20( 0)] & 0x3f)); 3136 #ifndef IEEE80211_NO_HT 3137 AR_WRITE(sc, AR_PHY_PWRTX_RATE6, 3138 (power[ATHN_POWER_HT20(13)] & 0x3f) << 24 | 3139 (power[ATHN_POWER_HT20(12)] & 0x3f) << 16 | 3140 (power[ATHN_POWER_HT20( 7)] & 0x3f) << 8 | 3141 (power[ATHN_POWER_HT20( 6)] & 0x3f)); 3142 AR_WRITE(sc, AR_PHY_PWRTX_RATE7, 3143 (power[ATHN_POWER_HT40( 5)] & 0x3f) << 24 | 3144 (power[ATHN_POWER_HT40( 4)] & 0x3f) << 16 | 3145 (power[ATHN_POWER_HT40( 1)] & 0x3f) << 8 | 3146 (power[ATHN_POWER_HT40( 0)] & 0x3f)); 3147 AR_WRITE(sc, AR_PHY_PWRTX_RATE8, 3148 (power[ATHN_POWER_HT40(13)] & 0x3f) << 24 | 3149 (power[ATHN_POWER_HT40(12)] & 0x3f) << 16 | 3150 (power[ATHN_POWER_HT40( 7)] & 0x3f) << 8 | 3151 (power[ATHN_POWER_HT40( 6)] & 0x3f)); 3152 AR_WRITE(sc, AR_PHY_PWRTX_RATE10, 3153 (power[ATHN_POWER_HT20(21)] & 0x3f) << 24 | 3154 (power[ATHN_POWER_HT20(20)] & 0x3f) << 16 | 3155 (power[ATHN_POWER_HT20(15)] & 0x3f) << 8 | 3156 (power[ATHN_POWER_HT20(14)] & 0x3f)); 3157 AR_WRITE(sc, AR_PHY_PWRTX_RATE11, 3158 (power[ATHN_POWER_HT40(23)] & 0x3f) << 24 | 3159 (power[ATHN_POWER_HT40(22)] & 0x3f) << 16 | 3160 (power[ATHN_POWER_HT20(23)] & 0x3f) << 8 | 3161 (power[ATHN_POWER_HT20(22)] & 0x3f)); 3162 AR_WRITE(sc, AR_PHY_PWRTX_RATE12, 3163 (power[ATHN_POWER_HT40(21)] & 0x3f) << 24 | 3164 (power[ATHN_POWER_HT40(20)] & 0x3f) << 16 | 3165 (power[ATHN_POWER_HT40(15)] & 0x3f) << 8 | 3166 (power[ATHN_POWER_HT40(14)] & 0x3f)); 3167 #endif 3168 AR_WRITE_BARRIER(sc); 3169 } 3170 3171 Static void 3172 ar9003_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3173 { 3174 #define X(x) ((uint32_t)(x) << 2) 3175 const struct athn_gain *prog = sc->sc_rx_gain; 3176 const uint32_t *pvals; 3177 int i; 3178 3179 if (IEEE80211_IS_CHAN_2GHZ(c)) 3180 pvals = prog->vals_2g; 3181 else 3182 pvals = prog->vals_5g; 3183 for (i = 0; i < prog->nregs; i++) 3184 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3185 AR_WRITE_BARRIER(sc); 3186 #undef X 3187 } 3188 3189 Static void 3190 ar9003_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3191 { 3192 #define X(x) ((uint32_t)(x) << 2) 3193 const struct athn_gain *prog = sc->sc_tx_gain; 3194 const uint32_t *pvals; 3195 int i; 3196 3197 if (IEEE80211_IS_CHAN_2GHZ(c)) 3198 pvals = prog->vals_2g; 3199 else 3200 pvals = prog->vals_5g; 3201 for (i = 0; i < prog->nregs; i++) 3202 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3203 AR_WRITE_BARRIER(sc); 3204 #undef X 3205 } 3206 3207 Static void 3208 ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c, 3209 struct ieee80211_channel *extc) 3210 { 3211 #define X(x) ((uint32_t)(x) << 2) 3212 struct athn_ops *ops = &sc->sc_ops; 3213 const struct athn_ini *ini = sc->sc_ini; 3214 const uint32_t *pvals; 3215 uint32_t reg; 3216 int i; 3217 3218 /* 3219 * The common init values include the pre and core phases for the 3220 * SoC, MAC, BB and Radio subsystems. 3221 */ 3222 DPRINTFN(DBG_INIT, sc, "writing pre and core init vals\n"); 3223 for (i = 0; i < ini->ncmregs; i++) { 3224 AR_WRITE(sc, X(ini->cmregs[i]), ini->cmvals[i]); 3225 if (AR_IS_ANALOG_REG(X(ini->cmregs[i]))) 3226 DELAY(100); 3227 if ((i & 0x1f) == 0) 3228 DELAY(1); 3229 } 3230 3231 /* 3232 * The modal init values include the post phase for the SoC, MAC, 3233 * BB and Radio subsystems. 3234 */ 3235 #ifndef IEEE80211_NO_HT 3236 if (extc != NULL) { 3237 if (IEEE80211_IS_CHAN_2GHZ(c)) 3238 pvals = ini->vals_2g40; 3239 else 3240 pvals = ini->vals_5g40; 3241 } 3242 else 3243 #endif 3244 { 3245 if (IEEE80211_IS_CHAN_2GHZ(c)) 3246 pvals = ini->vals_2g20; 3247 else 3248 pvals = ini->vals_5g20; 3249 } 3250 DPRINTFN(DBG_INIT, sc, "writing post init vals\n"); 3251 for (i = 0; i < ini->nregs; i++) { 3252 AR_WRITE(sc, X(ini->regs[i]), pvals[i]); 3253 if (AR_IS_ANALOG_REG(X(ini->regs[i]))) 3254 DELAY(100); 3255 if ((i & 0x1f) == 0) 3256 DELAY(1); 3257 } 3258 3259 if (sc->sc_rx_gain != NULL) 3260 ar9003_reset_rx_gain(sc, c); 3261 if (sc->sc_tx_gain != NULL) 3262 ar9003_reset_tx_gain(sc, c); 3263 3264 if (IEEE80211_IS_CHAN_5GHZ(c) && 3265 (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 3266 /* Update modal values for fast PLL clock. */ 3267 #ifndef IEEE80211_NO_HT 3268 if (extc != NULL) 3269 pvals = ini->fastvals_5g40; 3270 else 3271 #endif 3272 pvals = ini->fastvals_5g20; 3273 DPRINTFN(DBG_INIT, sc, "writing fast pll clock init vals\n"); 3274 for (i = 0; i < ini->nfastregs; i++) { 3275 AR_WRITE(sc, X(ini->fastregs[i]), pvals[i]); 3276 if (AR_IS_ANALOG_REG(X(ini->fastregs[i]))) 3277 DELAY(100); 3278 if ((i & 0x1f) == 0) 3279 DELAY(1); 3280 } 3281 } 3282 3283 /* 3284 * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted 3285 * descriptor status. 3286 */ 3287 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 3288 3289 reg = AR_READ(sc, AR_PCU_MISC_MODE2); 3290 reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE; 3291 reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX; 3292 reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP; 3293 AR_WRITE(sc, AR_PCU_MISC_MODE2, reg); 3294 AR_WRITE_BARRIER(sc); 3295 3296 ar9003_set_phy(sc, c, extc); 3297 ar9003_init_chains(sc); 3298 3299 ops->set_txpower(sc, c, extc); 3300 #undef X 3301 } 3302 3303 PUBLIC void 3304 ar9003_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3305 uint8_t ctl, const uint8_t *fbins, 3306 const struct ar_cal_target_power_leg *tgt, int nchans, uint8_t tpow[4]) 3307 { 3308 uint8_t fbin; 3309 int i, delta, lo, hi; 3310 3311 lo = hi = -1; 3312 fbin = athn_chan2fbin(c); 3313 for (i = 0; i < nchans; i++) { 3314 delta = fbin - fbins[i]; 3315 /* Find the largest sample that is <= our frequency. */ 3316 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3317 lo = i; 3318 /* Find the smallest sample that is >= our frequency. */ 3319 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3320 hi = i; 3321 } 3322 if (lo == -1) 3323 lo = hi; 3324 else if (hi == -1) 3325 hi = lo; 3326 /* Interpolate values. */ 3327 for (i = 0; i < 4; i++) { 3328 tpow[i] = athn_interpolate(fbin, 3329 fbins[lo], tgt[lo].tPow2x[i], 3330 fbins[hi], tgt[hi].tPow2x[i]); 3331 } 3332 /* XXX Apply conformance test limit. */ 3333 } 3334 3335 PUBLIC void 3336 ar9003_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3337 uint8_t ctl, const uint8_t *fbins, 3338 const struct ar_cal_target_power_ht *tgt, int nchans, uint8_t tpow[14]) 3339 { 3340 uint8_t fbin; 3341 int i, delta, lo, hi; 3342 3343 lo = hi = -1; 3344 fbin = athn_chan2fbin(c); 3345 for (i = 0; i < nchans; i++) { 3346 delta = fbin - fbins[i]; 3347 /* Find the largest sample that is <= our frequency. */ 3348 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3349 lo = i; 3350 /* Find the smallest sample that is >= our frequency. */ 3351 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3352 hi = i; 3353 } 3354 if (lo == -1) 3355 lo = hi; 3356 else if (hi == -1) 3357 hi = lo; 3358 /* Interpolate values. */ 3359 for (i = 0; i < 14; i++) { 3360 tpow[i] = athn_interpolate(fbin, 3361 fbins[lo], tgt[lo].tPow2x[i], 3362 fbins[hi], tgt[hi].tPow2x[i]); 3363 } 3364 /* XXX Apply conformance test limit. */ 3365 } 3366 3367 /* 3368 * Adaptive noise immunity. 3369 */ 3370 Static void 3371 ar9003_set_noise_immunity_level(struct athn_softc *sc, int level) 3372 { 3373 int high = level == 4; 3374 uint32_t reg; 3375 3376 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 3377 reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55); 3378 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 3379 3380 reg = AR_READ(sc, AR_PHY_AGC); 3381 reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64); 3382 reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14); 3383 AR_WRITE(sc, AR_PHY_AGC, reg); 3384 3385 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3386 reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78); 3387 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3388 AR_WRITE_BARRIER(sc); 3389 } 3390 3391 Static void 3392 ar9003_enable_ofdm_weak_signal(struct athn_softc *sc) 3393 { 3394 uint32_t reg; 3395 3396 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3397 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50); 3398 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40); 3399 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48); 3400 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3401 3402 reg = AR_READ(sc, AR_PHY_SFCORR); 3403 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77); 3404 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64); 3405 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16); 3406 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3407 3408 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3409 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50); 3410 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40); 3411 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77); 3412 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64); 3413 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3414 3415 AR_SETBITS(sc, AR_PHY_SFCORR_LOW, 3416 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3417 AR_WRITE_BARRIER(sc); 3418 } 3419 3420 Static void 3421 ar9003_disable_ofdm_weak_signal(struct athn_softc *sc) 3422 { 3423 uint32_t reg; 3424 3425 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3426 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127); 3427 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127); 3428 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63); 3429 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3430 3431 reg = AR_READ(sc, AR_PHY_SFCORR); 3432 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127); 3433 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127); 3434 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31); 3435 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3436 3437 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3438 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127); 3439 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127); 3440 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127); 3441 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127); 3442 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3443 3444 AR_CLRBITS(sc, AR_PHY_SFCORR_LOW, 3445 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3446 AR_WRITE_BARRIER(sc); 3447 } 3448 3449 Static void 3450 ar9003_set_cck_weak_signal(struct athn_softc *sc, int high) 3451 { 3452 uint32_t reg; 3453 3454 reg = AR_READ(sc, AR_PHY_CCK_DETECT); 3455 reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8); 3456 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); 3457 AR_WRITE_BARRIER(sc); 3458 } 3459 3460 Static void 3461 ar9003_set_firstep_level(struct athn_softc *sc, int level) 3462 { 3463 uint32_t reg; 3464 3465 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3466 reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4); 3467 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3468 AR_WRITE_BARRIER(sc); 3469 } 3470 3471 Static void 3472 ar9003_set_spur_immunity_level(struct athn_softc *sc, int level) 3473 { 3474 uint32_t reg; 3475 3476 reg = AR_READ(sc, AR_PHY_TIMING5); 3477 reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2); 3478 AR_WRITE(sc, AR_PHY_TIMING5, reg); 3479 AR_WRITE_BARRIER(sc); 3480 } 3481
Indexes created Wed Oct 22 06:10:02 GMT 2025