arn9003.c revision 1.3
1 /* $NetBSD: arn9003.c,v 1.3 2013/04/06 14:57:38 martin Exp $ */ 2 /* $OpenBSD: ar9003.c,v 1.25 2012/10/20 09:53:32 stsp Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 * Routines for AR9003 family. 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: arn9003.c,v 1.3 2013/04/06 14:57:38 martin Exp $"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/queue.h> 37 #include <sys/callout.h> 38 #include <sys/conf.h> 39 #include <sys/device.h> 40 41 #include <sys/bus.h> 42 #include <sys/endian.h> 43 #include <sys/intr.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_ether.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/in_var.h> 56 #include <netinet/ip.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_amrr.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <dev/ic/athnreg.h> 63 #include <dev/ic/athnvar.h> 64 #include <dev/ic/arn9003reg.h> 65 #include <dev/ic/arn9003.h> 66 67 #define Static static 68 69 Static void ar9003_calib_iq(struct athn_softc *); 70 Static int ar9003_calib_tx_iq(struct athn_softc *); 71 Static int ar9003_compute_predistortion(struct athn_softc *, 72 const uint32_t *, const uint32_t *); 73 Static void ar9003_disable_ofdm_weak_signal(struct athn_softc *); 74 Static void ar9003_disable_phy(struct athn_softc *); 75 Static int ar9003_dma_alloc(struct athn_softc *); 76 Static void ar9003_dma_free(struct athn_softc *); 77 Static void ar9003_do_calib(struct athn_softc *); 78 Static void ar9003_do_noisefloor_calib(struct athn_softc *); 79 Static void ar9003_enable_antenna_diversity(struct athn_softc *); 80 Static void ar9003_enable_ofdm_weak_signal(struct athn_softc *); 81 Static void ar9003_enable_predistorter(struct athn_softc *, int); 82 Static int ar9003_find_rom(struct athn_softc *); 83 Static void ar9003_force_txgain(struct athn_softc *, uint32_t); 84 Static int ar9003_get_desired_txgain(struct athn_softc *, int, int); 85 Static int ar9003_get_iq_corr(struct athn_softc *, int32_t[], int32_t[]); 86 Static void ar9003_gpio_config_input(struct athn_softc *, int); 87 Static void ar9003_gpio_config_output(struct athn_softc *, int, int); 88 Static int ar9003_gpio_read(struct athn_softc *, int); 89 Static void ar9003_gpio_write(struct athn_softc *, int, int); 90 Static void ar9003_hw_init(struct athn_softc *, struct ieee80211_channel *, 91 struct ieee80211_channel *); 92 Static void ar9003_init_baseband(struct athn_softc *); 93 Static void ar9003_init_chains(struct athn_softc *); 94 Static int ar9003_intr(struct athn_softc *); 95 Static void ar9003_next_calib(struct athn_softc *); 96 Static void ar9003_paprd_enable(struct athn_softc *); 97 Static int ar9003_paprd_tx_tone(struct athn_softc *); 98 Static void ar9003_paprd_tx_tone_done(struct athn_softc *); 99 Static int ar9003_read_eep_data(struct athn_softc *, uint32_t, void *, 100 int); 101 Static int ar9003_read_eep_word(struct athn_softc *, uint32_t, 102 uint16_t *); 103 Static int ar9003_read_otp_data(struct athn_softc *, uint32_t, void *, 104 int); 105 Static int ar9003_read_otp_word(struct athn_softc *, uint32_t, 106 uint32_t *); 107 Static int ar9003_read_rom(struct athn_softc *); 108 Static void ar9003_reset_rx_gain(struct athn_softc *, 109 struct ieee80211_channel *); 110 Static void ar9003_reset_tx_gain(struct athn_softc *, 111 struct ieee80211_channel *); 112 Static int ar9003_restore_rom_block(struct athn_softc *, uint8_t, 113 uint8_t, const uint8_t *, size_t); 114 Static void ar9003_rf_bus_release(struct athn_softc *); 115 Static int ar9003_rf_bus_request(struct athn_softc *); 116 Static void ar9003_rfsilent_init(struct athn_softc *); 117 Static int ar9003_rx_alloc(struct athn_softc *, int, int); 118 Static void ar9003_rx_enable(struct athn_softc *); 119 Static void ar9003_rx_free(struct athn_softc *, int); 120 Static void ar9003_rx_intr(struct athn_softc *, int); 121 Static int ar9003_rx_process(struct athn_softc *, int); 122 Static void ar9003_rx_radiotap(struct athn_softc *, struct mbuf *, 123 struct ar_rx_status *); 124 Static void ar9003_set_cck_weak_signal(struct athn_softc *, int); 125 Static void ar9003_set_delta_slope(struct athn_softc *, 126 struct ieee80211_channel *, struct ieee80211_channel *); 127 Static void ar9003_set_firstep_level(struct athn_softc *, int); 128 Static void ar9003_set_noise_immunity_level(struct athn_softc *, int); 129 Static void ar9003_set_phy(struct athn_softc *, struct ieee80211_channel *, 130 struct ieee80211_channel *); 131 Static void ar9003_set_rf_mode(struct athn_softc *, 132 struct ieee80211_channel *); 133 Static void ar9003_set_rxchains(struct athn_softc *); 134 Static void ar9003_set_spur_immunity_level(struct athn_softc *, int); 135 Static void ar9003_set_training_gain(struct athn_softc *, int); 136 Static int ar9003_swba_intr(struct athn_softc *); 137 Static int ar9003_tx(struct athn_softc *, struct mbuf *, 138 struct ieee80211_node *, int); 139 Static int ar9003_tx_alloc(struct athn_softc *); 140 Static void ar9003_tx_free(struct athn_softc *); 141 Static void ar9003_tx_intr(struct athn_softc *); 142 Static int ar9003_tx_process(struct athn_softc *); 143 144 #ifdef notused 145 Static void ar9003_bb_load_noisefloor(struct athn_softc *); 146 Static void ar9003_get_noisefloor(struct athn_softc *, 147 struct ieee80211_channel *); 148 Static void ar9003_paprd_calib(struct athn_softc *, 149 struct ieee80211_channel *); 150 Static void ar9003_read_noisefloor(struct athn_softc *, int16_t *, 151 int16_t *); 152 Static void ar9003_write_noisefloor(struct athn_softc *, int16_t *, 153 int16_t *); 154 Static void ar9300_noisefloor_calib(struct athn_softc *); 155 #endif /* notused */ 156 157 /* 158 * XXX: See if_iwn.c:MCLGETIalt() for a better solution. 159 * XXX: Put this in a header or in athn.c so it can be shared between 160 * ar5008.c and ar9003.c? 161 */ 162 static struct mbuf * 163 MCLGETI(struct athn_softc *sc __unused, int how, 164 struct ifnet *ifp __unused, u_int size) 165 { 166 struct mbuf *m; 167 168 MGETHDR(m, how, MT_DATA); 169 if (m == NULL) 170 return NULL; 171 172 MEXTMALLOC(m, size, how); 173 if ((m->m_flags & M_EXT) == 0) { 174 m_freem(m); 175 return NULL; 176 } 177 return m; 178 } 179 180 PUBLIC int 181 ar9003_attach(struct athn_softc *sc) 182 { 183 struct athn_ops *ops = &sc->sc_ops; 184 int error; 185 186 /* Set callbacks for AR9003 family. */ 187 ops->gpio_read = ar9003_gpio_read; 188 ops->gpio_write = ar9003_gpio_write; 189 ops->gpio_config_input = ar9003_gpio_config_input; 190 ops->gpio_config_output = ar9003_gpio_config_output; 191 ops->rfsilent_init = ar9003_rfsilent_init; 192 193 ops->dma_alloc = ar9003_dma_alloc; 194 ops->dma_free = ar9003_dma_free; 195 ops->rx_enable = ar9003_rx_enable; 196 ops->intr = ar9003_intr; 197 ops->tx = ar9003_tx; 198 199 ops->set_rf_mode = ar9003_set_rf_mode; 200 ops->rf_bus_request = ar9003_rf_bus_request; 201 ops->rf_bus_release = ar9003_rf_bus_release; 202 ops->set_phy = ar9003_set_phy; 203 ops->set_delta_slope = ar9003_set_delta_slope; 204 ops->enable_antenna_diversity = ar9003_enable_antenna_diversity; 205 ops->init_baseband = ar9003_init_baseband; 206 ops->disable_phy = ar9003_disable_phy; 207 ops->set_rxchains = ar9003_set_rxchains; 208 ops->noisefloor_calib = ar9003_do_noisefloor_calib; 209 ops->do_calib = ar9003_do_calib; 210 ops->next_calib = ar9003_next_calib; 211 ops->hw_init = ar9003_hw_init; 212 213 ops->set_noise_immunity_level = ar9003_set_noise_immunity_level; 214 ops->enable_ofdm_weak_signal = ar9003_enable_ofdm_weak_signal; 215 ops->disable_ofdm_weak_signal = ar9003_disable_ofdm_weak_signal; 216 ops->set_cck_weak_signal = ar9003_set_cck_weak_signal; 217 ops->set_firstep_level = ar9003_set_firstep_level; 218 ops->set_spur_immunity_level = ar9003_set_spur_immunity_level; 219 220 /* Set MAC registers offsets. */ 221 sc->sc_obs_off = AR_OBS; 222 sc->sc_gpio_input_en_off = AR_GPIO_INPUT_EN_VAL; 223 224 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 225 athn_config_nonpcie(sc); 226 else 227 athn_config_pcie(sc); 228 229 /* Determine ROM type and location. */ 230 if ((error = ar9003_find_rom(sc)) != 0) { 231 printf("%s: could not find ROM\n", device_xname(sc->sc_dev)); 232 return error; 233 } 234 /* Read entire ROM content in memory. */ 235 if ((error = ar9003_read_rom(sc)) != 0) { 236 printf("%s: could not read ROM\n", device_xname(sc->sc_dev)); 237 return error; 238 } 239 240 /* Determine if it is a non-enterprise AR9003 card. */ 241 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_MPSD) 242 sc->sc_flags |= ATHN_FLAG_NON_ENTERPRISE; 243 244 ops->setup(sc); 245 return 0; 246 } 247 248 /* 249 * Read 16-bit word from EEPROM. 250 */ 251 Static int 252 ar9003_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val) 253 { 254 uint32_t reg; 255 int ntries; 256 257 reg = AR_READ(sc, AR_EEPROM_OFFSET(addr)); 258 for (ntries = 0; ntries < 1000; ntries++) { 259 reg = AR_READ(sc, AR_EEPROM_STATUS_DATA); 260 if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY | 261 AR_EEPROM_STATUS_DATA_PROT_ACCESS))) { 262 *val = MS(reg, AR_EEPROM_STATUS_DATA_VAL); 263 return 0; 264 } 265 DELAY(10); 266 } 267 *val = 0xffff; 268 return ETIMEDOUT; 269 } 270 271 /* 272 * Read an arbitrary number of bytes at a specified address in EEPROM. 273 * NB: The address may not be 16-bit aligned. 274 */ 275 Static int 276 ar9003_read_eep_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 277 { 278 uint8_t *dst = buf; 279 uint16_t val; 280 int error; 281 282 if (len > 0 && (addr & 1)) { 283 /* Deal with non-aligned reads. */ 284 addr >>= 1; 285 error = ar9003_read_eep_word(sc, addr, &val); 286 if (error != 0) 287 return error; 288 *dst++ = val & 0xff; 289 addr--; 290 len--; 291 } 292 else 293 addr >>= 1; 294 for (; len >= 2; addr--, len -= 2) { 295 error = ar9003_read_eep_word(sc, addr, &val); 296 if (error != 0) 297 return error; 298 *dst++ = val >> 8; 299 *dst++ = val & 0xff; 300 } 301 if (len > 0) { 302 error = ar9003_read_eep_word(sc, addr, &val); 303 if (error != 0) 304 return error; 305 *dst++ = val >> 8; 306 } 307 return 0; 308 } 309 310 /* 311 * Read 32-bit word from OTPROM. 312 */ 313 Static int 314 ar9003_read_otp_word(struct athn_softc *sc, uint32_t addr, uint32_t *val) 315 { 316 uint32_t reg; 317 int ntries; 318 319 reg = AR_READ(sc, AR_OTP_BASE(addr)); 320 for (ntries = 0; ntries < 1000; ntries++) { 321 reg = AR_READ(sc, AR_OTP_STATUS); 322 if (MS(reg, AR_OTP_STATUS_TYPE) == AR_OTP_STATUS_VALID) { 323 *val = AR_READ(sc, AR_OTP_READ_DATA); 324 return 0; 325 } 326 DELAY(10); 327 } 328 return ETIMEDOUT; 329 } 330 331 /* 332 * Read an arbitrary number of bytes at a specified address in OTPROM. 333 * NB: The address may not be 32-bit aligned. 334 */ 335 Static int 336 ar9003_read_otp_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 337 { 338 uint8_t *dst = buf; 339 uint32_t val; 340 int error; 341 342 /* NB: not optimal for non-aligned reads, but correct. */ 343 for (; len > 0; addr--, len--) { 344 error = ar9003_read_otp_word(sc, addr >> 2, &val); 345 if (error != 0) 346 return error; 347 *dst++ = (val >> ((addr & 3) * 8)) & 0xff; 348 } 349 return 0; 350 } 351 352 /* 353 * Determine if the chip has an external EEPROM or an OTPROM and its size. 354 */ 355 Static int 356 ar9003_find_rom(struct athn_softc *sc) 357 { 358 struct athn_ops *ops = &sc->sc_ops; 359 uint32_t hdr; 360 int error; 361 362 /* Try EEPROM. */ 363 ops->read_rom_data = ar9003_read_eep_data; 364 365 sc->sc_eep_size = AR_SREV_9485(sc) ? 4096 : 1024; 366 sc->sc_eep_base = sc->sc_eep_size - 1; 367 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 368 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 369 return 0; 370 371 sc->sc_eep_size = 512; 372 sc->sc_eep_base = sc->sc_eep_size - 1; 373 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 374 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 375 return 0; 376 377 /* Try OTPROM. */ 378 ops->read_rom_data = ar9003_read_otp_data; 379 380 sc->sc_eep_size = 1024; 381 sc->sc_eep_base = sc->sc_eep_size - 1; 382 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 383 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 384 return 0; 385 386 sc->sc_eep_size = 512; 387 sc->sc_eep_base = sc->sc_eep_size - 1; 388 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 389 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 390 return 0; 391 392 return EIO; /* Not found. */ 393 } 394 395 Static int 396 ar9003_restore_rom_block(struct athn_softc *sc, uint8_t alg, uint8_t ref, 397 const uint8_t *buf, size_t len) 398 { 399 const uint8_t *def, *ptr, *end; 400 uint8_t *eep = sc->sc_eep; 401 size_t off, clen; 402 403 if (alg == AR_EEP_COMPRESS_BLOCK) { 404 /* Block contains chunks that shadow ROM template. */ 405 def = sc->sc_ops.get_rom_template(sc, ref); 406 if (def == NULL) { 407 DPRINTFN(DBG_INIT, sc, "unknown template image %d\n", 408 ref); 409 return EINVAL; 410 } 411 /* Start with template. */ 412 memcpy(eep, def, sc->sc_eep_size); 413 /* Shadow template with chunks. */ 414 off = 0; /* Offset in ROM image. */ 415 ptr = buf; /* Offset in block. */ 416 end = buf + len; 417 /* Process chunks. */ 418 while (ptr + 2 <= end) { 419 off += *ptr++; /* Gap with previous chunk. */ 420 clen = *ptr++; /* Chunk length. */ 421 /* Make sure block is large enough. */ 422 if (ptr + clen > end) 423 return EINVAL; 424 /* Make sure chunk fits in ROM image. */ 425 if (off + clen > sc->sc_eep_size) 426 return EINVAL; 427 /* Restore chunk. */ 428 DPRINTFN(DBG_INIT, sc, "ROM chunk @%zd/%zd\n", 429 off, clen); 430 memcpy(&eep[off], ptr, clen); 431 ptr += clen; 432 off += clen; 433 } 434 } 435 else if (alg == AR_EEP_COMPRESS_NONE) { 436 /* Block contains full ROM image. */ 437 if (len != sc->sc_eep_size) { 438 DPRINTFN(DBG_INIT, sc, "block length mismatch %zd\n", 439 len); 440 return EINVAL; 441 } 442 memcpy(eep, buf, len); 443 } 444 return 0; 445 } 446 447 Static int 448 ar9003_read_rom(struct athn_softc *sc) 449 { 450 struct athn_ops *ops = &sc->sc_ops; 451 uint8_t *buf, *ptr, alg, ref; 452 uint16_t sum, rsum; 453 uint32_t hdr; 454 int error, addr; 455 size_t len, i, j; 456 457 /* Allocate space to store ROM in host memory. */ 458 sc->sc_eep = malloc(sc->sc_eep_size, M_DEVBUF, M_NOWAIT); 459 if (sc->sc_eep == NULL) 460 return ENOMEM; 461 462 /* Allocate temporary buffer to store ROM blocks. */ 463 buf = malloc(2048, M_DEVBUF, M_NOWAIT); 464 if (buf == NULL) 465 return ENOMEM; 466 467 /* Restore vendor-specified ROM blocks. */ 468 addr = sc->sc_eep_base; 469 for (i = 0; i < 100; i++) { 470 /* Read block header. */ 471 error = ops->read_rom_data(sc, addr, &hdr, sizeof(hdr)); 472 if (error != 0) 473 break; 474 if (hdr == 0 || hdr == 0xffffffff) 475 break; 476 addr -= sizeof(hdr); 477 478 /* Extract bits from header. */ 479 ptr = (uint8_t *)&hdr; 480 alg = (ptr[0] & 0xe0) >> 5; 481 ref = (ptr[1] & 0x80) >> 2 | (ptr[0] & 0x1f); 482 len = (ptr[1] & 0x7f) << 4 | (ptr[2] & 0xf0) >> 4; 483 DPRINTFN(DBG_INIT, sc, 484 "ROM block %zd: alg=%d ref=%d len=%zd\n", 485 i, alg, ref, len); 486 487 /* Read block data (len <= 0x7ff). */ 488 error = ops->read_rom_data(sc, addr, buf, len); 489 if (error != 0) 490 break; 491 addr -= len; 492 493 /* Read block checksum. */ 494 error = ops->read_rom_data(sc, addr, &sum, sizeof(sum)); 495 if (error != 0) 496 break; 497 addr -= sizeof(sum); 498 499 /* Compute block checksum. */ 500 rsum = 0; 501 for (j = 0; j < len; j++) 502 rsum += buf[j]; 503 /* Compare to that in ROM. */ 504 if (le16toh(sum) != rsum) { 505 DPRINTFN(DBG_INIT, sc, 506 "bad block checksum 0x%x/0x%x\n", 507 le16toh(sum), rsum); 508 continue; /* Skip bad block. */ 509 } 510 /* Checksum is correct, restore block. */ 511 ar9003_restore_rom_block(sc, alg, ref, buf, len); 512 } 513 #if BYTE_ORDER == BIG_ENDIAN 514 /* NB: ROM is always little endian. */ 515 if (error == 0) 516 ops->swap_rom(sc); 517 #endif 518 free(buf, M_DEVBUF); 519 return error; 520 } 521 522 /* 523 * Access to General Purpose Input/Output ports. 524 */ 525 Static int 526 ar9003_gpio_read(struct athn_softc *sc, int pin) 527 { 528 529 KASSERT(pin < sc->sc_ngpiopins); 530 return ((AR_READ(sc, AR_GPIO_IN) & AR9300_GPIO_IN_VAL) & 531 (1 << pin)) != 0; 532 } 533 534 Static void 535 ar9003_gpio_write(struct athn_softc *sc, int pin, int set) 536 { 537 uint32_t reg; 538 539 KASSERT(pin < sc->sc_ngpiopins); 540 reg = AR_READ(sc, AR_GPIO_IN_OUT); 541 if (set) 542 reg |= 1 << pin; 543 else 544 reg &= ~(1 << pin); 545 AR_WRITE(sc, AR_GPIO_IN_OUT, reg); 546 AR_WRITE_BARRIER(sc); 547 } 548 549 Static void 550 ar9003_gpio_config_input(struct athn_softc *sc, int pin) 551 { 552 uint32_t reg; 553 554 reg = AR_READ(sc, AR_GPIO_OE_OUT); 555 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 556 reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2); 557 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 558 AR_WRITE_BARRIER(sc); 559 } 560 561 Static void 562 ar9003_gpio_config_output(struct athn_softc *sc, int pin, int type) 563 { 564 uint32_t reg; 565 int mux, off; 566 567 mux = pin / 6; 568 off = pin % 6; 569 570 reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux)); 571 reg &= ~(0x1f << (off * 5)); 572 reg |= (type & 0x1f) << (off * 5); 573 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg); 574 575 reg = AR_READ(sc, AR_GPIO_OE_OUT); 576 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 577 reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2); 578 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 579 AR_WRITE_BARRIER(sc); 580 } 581 582 Static void 583 ar9003_rfsilent_init(struct athn_softc *sc) 584 { 585 uint32_t reg; 586 587 /* Configure hardware radio switch. */ 588 AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 589 reg = AR_READ(sc, AR_GPIO_INPUT_MUX2); 590 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); 591 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg); 592 ar9003_gpio_config_input(sc, sc->sc_rfsilent_pin); 593 AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB); 594 if (!(sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED)) { 595 AR_SETBITS(sc, AR_GPIO_INTR_POL, 596 AR_GPIO_INTR_POL_PIN(sc->sc_rfsilent_pin)); 597 } 598 AR_WRITE_BARRIER(sc); 599 } 600 601 Static int 602 ar9003_dma_alloc(struct athn_softc *sc) 603 { 604 int error; 605 606 error = ar9003_tx_alloc(sc); 607 if (error != 0) 608 return error; 609 610 error = ar9003_rx_alloc(sc, ATHN_QID_LP, AR9003_RX_LP_QDEPTH); 611 if (error != 0) 612 return error; 613 614 error = ar9003_rx_alloc(sc, ATHN_QID_HP, AR9003_RX_HP_QDEPTH); 615 if (error != 0) 616 return error; 617 618 return 0; 619 } 620 621 Static void 622 ar9003_dma_free(struct athn_softc *sc) 623 { 624 625 ar9003_tx_free(sc); 626 ar9003_rx_free(sc, ATHN_QID_LP); 627 ar9003_rx_free(sc, ATHN_QID_HP); 628 } 629 630 Static int 631 ar9003_tx_alloc(struct athn_softc *sc) 632 { 633 struct athn_tx_buf *bf; 634 bus_size_t size; 635 int error, nsegs, i; 636 637 /* 638 * Allocate Tx status ring. 639 */ 640 size = AR9003_NTXSTATUS * sizeof(struct ar_tx_status); 641 642 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 643 BUS_DMA_NOWAIT, &sc->sc_txsmap); 644 if (error != 0) 645 goto fail; 646 647 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_txsseg, 1, 648 // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 649 &nsegs, BUS_DMA_NOWAIT); 650 if (error != 0) 651 goto fail; 652 653 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_txsseg, 1, size, 654 (void **)&sc->sc_txsring, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 655 if (error != 0) 656 goto fail; 657 658 error = bus_dmamap_load_raw(sc->sc_dmat, sc->sc_txsmap, &sc->sc_txsseg, 659 1, size, BUS_DMA_NOWAIT | BUS_DMA_READ); 660 if (error != 0) 661 goto fail; 662 663 /* 664 * Allocate a pool of Tx descriptors shared between all Tx queues. 665 */ 666 size = ATHN_NTXBUFS * sizeof(struct ar_tx_desc); 667 668 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 669 BUS_DMA_NOWAIT, &sc->sc_map); 670 if (error != 0) 671 goto fail; 672 673 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_seg, 1, 674 // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 675 &nsegs, BUS_DMA_NOWAIT); 676 if (error != 0) 677 goto fail; 678 679 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, 1, size, 680 (void **)&sc->sc_descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 681 if (error != 0) 682 goto fail; 683 684 error = bus_dmamap_load_raw(sc->sc_dmat, sc->sc_map, &sc->sc_seg, 1, size, 685 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 686 if (error != 0) 687 goto fail; 688 689 SIMPLEQ_INIT(&sc->sc_txbufs); 690 for (i = 0; i < ATHN_NTXBUFS; i++) { 691 bf = &sc->sc_txpool[i]; 692 693 error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ, 694 AR9003_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT, 695 &bf->bf_map); 696 if (error != 0) { 697 printf("%s: could not create Tx buf DMA map\n", 698 device_xname(sc->sc_dev)); 699 goto fail; 700 } 701 702 bf->bf_descs = &((struct ar_tx_desc *)sc->sc_descs)[i]; 703 bf->bf_daddr = sc->sc_map->dm_segs[0].ds_addr + 704 i * sizeof(struct ar_tx_desc); 705 706 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 707 } 708 return 0; 709 fail: 710 ar9003_tx_free(sc); 711 return error; 712 } 713 714 Static void 715 ar9003_tx_free(struct athn_softc *sc) 716 { 717 struct athn_tx_buf *bf; 718 int i; 719 720 for (i = 0; i < ATHN_NTXBUFS; i++) { 721 bf = &sc->sc_txpool[i]; 722 723 if (bf->bf_map != NULL) 724 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 725 } 726 /* Free Tx descriptors. */ 727 if (sc->sc_map != NULL) { 728 if (sc->sc_descs != NULL) { 729 bus_dmamap_unload(sc->sc_dmat, sc->sc_map); 730 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 731 ATHN_NTXBUFS * sizeof(struct ar_tx_desc)); 732 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 733 } 734 bus_dmamap_destroy(sc->sc_dmat, sc->sc_map); 735 } 736 /* Free Tx status ring. */ 737 if (sc->sc_txsmap != NULL) { 738 if (sc->sc_txsring != NULL) { 739 bus_dmamap_unload(sc->sc_dmat, sc->sc_txsmap); 740 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_txsring, 741 AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 742 bus_dmamem_free(sc->sc_dmat, &sc->sc_txsseg, 1); 743 } 744 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsmap); 745 } 746 } 747 748 Static int 749 ar9003_rx_alloc(struct athn_softc *sc, int qid, int count) 750 { 751 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 752 struct athn_rx_buf *bf; 753 struct ar_rx_status *ds; 754 int error, i; 755 756 rxq->bf = malloc(count * sizeof(*bf), M_DEVBUF, M_NOWAIT | M_ZERO); 757 if (rxq->bf == NULL) 758 return ENOMEM; 759 760 rxq->count = count; 761 762 for (i = 0; i < rxq->count; i++) { 763 bf = &rxq->bf[i]; 764 765 error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1, 766 ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 767 &bf->bf_map); 768 if (error != 0) { 769 printf("%s: could not create Rx buf DMA map\n", 770 device_xname(sc->sc_dev)); 771 goto fail; 772 } 773 /* 774 * Assumes MCLGETI returns cache-line-size aligned buffers. 775 */ 776 bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 777 if (bf->bf_m == NULL) { 778 printf("%s: could not allocate Rx mbuf\n", 779 device_xname(sc->sc_dev)); 780 error = ENOBUFS; 781 goto fail; 782 } 783 784 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 785 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 786 BUS_DMA_NOWAIT); 787 if (error != 0) { 788 printf("%s: could not DMA map Rx buffer\n", 789 device_xname(sc->sc_dev)); 790 goto fail; 791 } 792 793 ds = mtod(bf->bf_m, struct ar_rx_status *); 794 memset(ds, 0, sizeof(*ds)); 795 bf->bf_desc = ds; 796 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 797 798 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 799 BUS_DMASYNC_PREREAD); 800 } 801 return 0; 802 fail: 803 ar9003_rx_free(sc, qid); 804 return error; 805 } 806 807 Static void 808 ar9003_rx_free(struct athn_softc *sc, int qid) 809 { 810 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 811 struct athn_rx_buf *bf; 812 int i; 813 814 if (rxq->bf == NULL) 815 return; 816 for (i = 0; i < rxq->count; i++) { 817 bf = &rxq->bf[i]; 818 819 if (bf->bf_map != NULL) 820 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 821 if (bf->bf_m != NULL) 822 m_freem(bf->bf_m); 823 } 824 free(rxq->bf, M_DEVBUF); 825 } 826 827 PUBLIC void 828 ar9003_reset_txsring(struct athn_softc *sc) 829 { 830 831 sc->sc_txscur = 0; 832 memset(sc->sc_txsring, 0, AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 833 AR_WRITE(sc, AR_Q_STATUS_RING_START, 834 sc->sc_txsmap->dm_segs[0].ds_addr); 835 AR_WRITE(sc, AR_Q_STATUS_RING_END, 836 sc->sc_txsmap->dm_segs[0].ds_addr + sc->sc_txsmap->dm_segs[0].ds_len); 837 AR_WRITE_BARRIER(sc); 838 } 839 840 Static void 841 ar9003_rx_enable(struct athn_softc *sc) 842 { 843 struct athn_rxq *rxq; 844 struct athn_rx_buf *bf; 845 struct ar_rx_status *ds; 846 uint32_t reg; 847 int qid, i; 848 849 reg = AR_READ(sc, AR_RXBP_THRESH); 850 reg = RW(reg, AR_RXBP_THRESH_HP, 1); 851 reg = RW(reg, AR_RXBP_THRESH_LP, 1); 852 AR_WRITE(sc, AR_RXBP_THRESH, reg); 853 854 /* Set Rx buffer size. */ 855 AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds)); 856 857 for (qid = 0; qid < 2; qid++) { 858 rxq = &sc->sc_rxq[qid]; 859 860 /* Setup Rx status descriptors. */ 861 SIMPLEQ_INIT(&rxq->head); 862 for (i = 0; i < rxq->count; i++) { 863 bf = &rxq->bf[i]; 864 ds = bf->bf_desc; 865 866 memset(ds, 0, sizeof(*ds)); 867 if (qid == ATHN_QID_LP) 868 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 869 else 870 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 871 AR_WRITE_BARRIER(sc); 872 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 873 } 874 } 875 /* Enable Rx. */ 876 AR_WRITE(sc, AR_CR, 0); 877 AR_WRITE_BARRIER(sc); 878 } 879 880 Static void 881 ar9003_rx_radiotap(struct athn_softc *sc, struct mbuf *m, 882 struct ar_rx_status *ds) 883 { 884 struct athn_rx_radiotap_header *tap = &sc->sc_rxtap; 885 struct ieee80211com *ic = &sc->sc_ic; 886 uint64_t tsf; 887 uint32_t tstamp; 888 uint8_t rate; 889 890 /* Extend the 15-bit timestamp from Rx status to 64-bit TSF. */ 891 tstamp = ds->ds_status3; 892 tsf = AR_READ(sc, AR_TSF_U32); 893 tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32); 894 if ((tsf & 0x7fff) < tstamp) 895 tsf -= 0x8000; 896 tsf = (tsf & ~0x7fff) | tstamp; 897 898 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 899 tap->wr_tsft = htole64(tsf); 900 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 901 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 902 tap->wr_dbm_antsignal = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 903 /* XXX noise. */ 904 tap->wr_antenna = MS(ds->ds_status4, AR_RXS4_ANTENNA); 905 tap->wr_rate = 0; /* In case it can't be found below. */ 906 rate = MS(ds->ds_status1, AR_RXS1_RATE); 907 if (rate & 0x80) { /* HT. */ 908 /* Bit 7 set means HT MCS instead of rate. */ 909 tap->wr_rate = rate; 910 if (!(ds->ds_status4 & AR_RXS4_GI)) 911 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 912 913 } 914 else if (rate & 0x10) { /* CCK. */ 915 if (rate & 0x04) 916 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 917 switch (rate & ~0x14) { 918 case 0xb: tap->wr_rate = 2; break; 919 case 0xa: tap->wr_rate = 4; break; 920 case 0x9: tap->wr_rate = 11; break; 921 case 0x8: tap->wr_rate = 22; break; 922 } 923 } 924 else { /* OFDM. */ 925 switch (rate) { 926 case 0xb: tap->wr_rate = 12; break; 927 case 0xf: tap->wr_rate = 18; break; 928 case 0xa: tap->wr_rate = 24; break; 929 case 0xe: tap->wr_rate = 36; break; 930 case 0x9: tap->wr_rate = 48; break; 931 case 0xd: tap->wr_rate = 72; break; 932 case 0x8: tap->wr_rate = 96; break; 933 case 0xc: tap->wr_rate = 108; break; 934 } 935 } 936 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 937 } 938 939 Static int 940 ar9003_rx_process(struct athn_softc *sc, int qid) 941 { 942 struct ieee80211com *ic = &sc->sc_ic; 943 struct ifnet *ifp = &sc->sc_if; 944 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 945 struct athn_rx_buf *bf; 946 struct ar_rx_status *ds; 947 struct ieee80211_frame *wh; 948 struct ieee80211_node *ni; 949 struct mbuf *m, *m1; 950 size_t len; 951 u_int32_t rstamp; 952 int error, rssi; 953 954 bf = SIMPLEQ_FIRST(&rxq->head); 955 if (__predict_false(bf == NULL)) { /* Should not happen. */ 956 printf("%s: Rx queue is empty!\n", device_xname(sc->sc_dev)); 957 return ENOENT; 958 } 959 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 960 BUS_DMASYNC_POSTREAD); 961 962 ds = mtod(bf->bf_m, struct ar_rx_status *); 963 if (!(ds->ds_status1 & AR_RXS1_DONE)) 964 return EBUSY; 965 966 /* Check that it is a valid Rx status descriptor. */ 967 if ((ds->ds_info & (AR_RXI_DESC_ID_M | AR_RXI_DESC_TX | 968 AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS)) 969 goto skip; 970 971 if (!(ds->ds_status11 & AR_RXS11_FRAME_OK)) { 972 if (ds->ds_status11 & AR_RXS11_CRC_ERR) 973 DPRINTFN(DBG_RX, sc, "CRC error\n"); 974 else if (ds->ds_status11 & AR_RXS11_PHY_ERR) 975 DPRINTFN(DBG_RX, sc, "PHY error=0x%x\n", 976 MS(ds->ds_status11, AR_RXS11_PHY_ERR_CODE)); 977 else if (ds->ds_status11 & AR_RXS11_DECRYPT_CRC_ERR) 978 DPRINTFN(DBG_RX, sc, "Decryption CRC error\n"); 979 else if (ds->ds_status11 & AR_RXS11_MICHAEL_ERR) { 980 DPRINTFN(DBG_RX, sc, "Michael MIC failure\n"); 981 /* Report Michael MIC failures to net80211. */ 982 983 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 984 m = bf->bf_m; 985 m->m_pkthdr.rcvif = ifp; 986 m->m_data = (void *)&ds[1]; 987 m->m_pkthdr.len = m->m_len = len; 988 wh = mtod(m, struct ieee80211_frame *); 989 990 ieee80211_notify_michael_failure(ic, wh, 991 0 /* XXX: keyix */); 992 } 993 ifp->if_ierrors++; 994 goto skip; 995 } 996 997 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 998 if (__predict_false(len < IEEE80211_MIN_LEN || 999 len > ATHN_RXBUFSZ - sizeof(*ds))) { 1000 DPRINTFN(DBG_RX, sc, "corrupted descriptor length=%zd\n", 1001 len); 1002 ifp->if_ierrors++; 1003 goto skip; 1004 } 1005 1006 /* Allocate a new Rx buffer. */ 1007 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 1008 if (__predict_false(m1 == NULL)) { 1009 ic->ic_stats.is_rx_nobuf++; 1010 ifp->if_ierrors++; 1011 goto skip; 1012 } 1013 1014 /* Unmap the old Rx buffer. */ 1015 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1016 1017 /* Map the new Rx buffer. */ 1018 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *), 1019 ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1020 if (__predict_false(error != 0)) { 1021 m_freem(m1); 1022 1023 /* Remap the old Rx buffer or panic. */ 1024 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 1025 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 1026 BUS_DMA_NOWAIT | BUS_DMA_READ); 1027 KASSERT(error != 0); 1028 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1029 ifp->if_ierrors++; 1030 goto skip; 1031 } 1032 bf->bf_desc = mtod(m1, struct ar_rx_status *); 1033 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1034 1035 m = bf->bf_m; 1036 bf->bf_m = m1; 1037 1038 /* Finalize mbuf. */ 1039 m->m_pkthdr.rcvif = ifp; 1040 /* Strip Rx status descriptor from head. */ 1041 m->m_data = (void *)&ds[1]; 1042 m->m_pkthdr.len = m->m_len = len; 1043 1044 /* Grab a reference to the source node. */ 1045 wh = mtod(m, struct ieee80211_frame *); 1046 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1047 1048 /* Remove any HW padding after the 802.11 header. */ 1049 if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) { 1050 u_int hdrlen = ieee80211_anyhdrsize(wh); 1051 if (hdrlen & 3) { 1052 ovbcopy(wh, (uint8_t *)wh + 2, hdrlen); 1053 m_adj(m, 2); 1054 } 1055 } 1056 if (__predict_false(sc->sc_drvbpf != NULL)) 1057 ar9003_rx_radiotap(sc, m, ds); 1058 /* Trim 802.11 FCS after radiotap. */ 1059 m_adj(m, -IEEE80211_CRC_LEN); 1060 1061 /* Send the frame to the 802.11 layer. */ 1062 rssi = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 1063 rstamp = ds->ds_status3; 1064 ieee80211_input(ic, m, ni, rssi, rstamp); 1065 1066 /* Node is no longer needed. */ 1067 ieee80211_free_node(ni); 1068 1069 skip: 1070 /* Unlink this descriptor from head. */ 1071 SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list); 1072 memset(bf->bf_desc, 0, sizeof(*ds)); 1073 1074 /* Re-use this descriptor and link it to tail. */ 1075 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 1076 BUS_DMASYNC_PREREAD); 1077 1078 if (qid == ATHN_QID_LP) 1079 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 1080 else 1081 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 1082 AR_WRITE_BARRIER(sc); 1083 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 1084 1085 /* Re-enable Rx. */ 1086 AR_WRITE(sc, AR_CR, 0); 1087 AR_WRITE_BARRIER(sc); 1088 return 0; 1089 } 1090 1091 Static void 1092 ar9003_rx_intr(struct athn_softc *sc, int qid) 1093 { 1094 1095 while (ar9003_rx_process(sc, qid) == 0) 1096 continue; 1097 } 1098 1099 Static int 1100 ar9003_tx_process(struct athn_softc *sc) 1101 { 1102 struct ifnet *ifp = &sc->sc_if; 1103 struct athn_txq *txq; 1104 struct athn_node *an; 1105 struct athn_tx_buf *bf; 1106 struct ar_tx_status *ds; 1107 uint8_t qid, failcnt; 1108 1109 ds = &((struct ar_tx_status *)sc->sc_txsring)[sc->sc_txscur]; 1110 if (!(ds->ds_status8 & AR_TXS8_DONE)) 1111 return EBUSY; 1112 1113 sc->sc_txscur = (sc->sc_txscur + 1) % AR9003_NTXSTATUS; 1114 1115 /* Check that it is a valid Tx status descriptor. */ 1116 if ((ds->ds_info & (AR_TXI_DESC_ID_M | AR_TXI_DESC_TX)) != 1117 (SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX)) { 1118 memset(ds, 0, sizeof(*ds)); 1119 return 0; 1120 } 1121 /* Retrieve the queue that was used to send this PDU. */ 1122 qid = MS(ds->ds_info, AR_TXI_QCU_NUM); 1123 txq = &sc->sc_txq[qid]; 1124 1125 bf = SIMPLEQ_FIRST(&txq->head); 1126 if (bf == NULL || bf == txq->wait) { 1127 memset(ds, 0, sizeof(*ds)); 1128 return 0; 1129 } 1130 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1131 ifp->if_opackets++; 1132 1133 sc->sc_tx_timer = 0; 1134 1135 if (ds->ds_status3 & AR_TXS3_EXCESSIVE_RETRIES) 1136 ifp->if_oerrors++; 1137 1138 if (ds->ds_status3 & AR_TXS3_UNDERRUN) 1139 athn_inc_tx_trigger_level(sc); 1140 1141 /* Wakeup PA predistortion state machine. */ 1142 if (bf->bf_txflags & ATHN_TXFLAG_PAPRD) 1143 ar9003_paprd_tx_tone_done(sc); 1144 1145 an = (struct athn_node *)bf->bf_ni; 1146 /* 1147 * NB: the data fail count contains the number of un-acked tries 1148 * for the final series used. We must add the number of tries for 1149 * each series that was fully processed. 1150 */ 1151 failcnt = MS(ds->ds_status3, AR_TXS3_DATA_FAIL_CNT); 1152 /* NB: Assume two tries per series. */ 1153 failcnt += MS(ds->ds_status8, AR_TXS8_FINAL_IDX) * 2; 1154 1155 /* Update rate control statistics. */ 1156 an->amn.amn_txcnt++; 1157 if (failcnt > 0) 1158 an->amn.amn_retrycnt++; 1159 1160 DPRINTFN(DBG_TX, sc, "Tx done qid=%d status3=%d fail count=%d\n", 1161 qid, ds->ds_status3, failcnt); 1162 1163 /* Reset Tx status descriptor. */ 1164 memset(ds, 0, sizeof(*ds)); 1165 1166 /* Unmap Tx buffer. */ 1167 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1168 BUS_DMASYNC_POSTWRITE); 1169 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1170 1171 m_freem(bf->bf_m); 1172 bf->bf_m = NULL; 1173 ieee80211_free_node(bf->bf_ni); 1174 bf->bf_ni = NULL; 1175 1176 /* Link Tx buffer back to global free list. */ 1177 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1178 1179 /* Queue buffers that are waiting if there is new room. */ 1180 if (--txq->queued < AR9003_TX_QDEPTH && txq->wait != NULL) { 1181 AR_WRITE(sc, AR_QTXDP(qid), txq->wait->bf_daddr); 1182 AR_WRITE_BARRIER(sc); 1183 txq->wait = SIMPLEQ_NEXT(txq->wait, bf_list); 1184 } 1185 return 0; 1186 } 1187 1188 Static void 1189 ar9003_tx_intr(struct athn_softc *sc) 1190 { 1191 struct ifnet *ifp = &sc->sc_if; 1192 1193 while (ar9003_tx_process(sc) == 0); 1194 1195 if (!SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 1196 ifp->if_flags &= ~IFF_OACTIVE; 1197 ifp->if_start(ifp); 1198 } 1199 } 1200 1201 #ifndef IEEE80211_STA_ONLY 1202 /* 1203 * Process Software Beacon Alert interrupts. 1204 */ 1205 Static int 1206 ar9003_swba_intr(struct athn_softc *sc) 1207 { 1208 struct ieee80211com *ic = &sc->sc_ic; 1209 struct ifnet *ifp = &sc->sc_if; 1210 struct ieee80211_node *ni = ic->ic_bss; 1211 struct athn_tx_buf *bf = sc->sc_bcnbuf; 1212 struct ieee80211_frame *wh; 1213 struct ieee80211_beacon_offsets bo; 1214 struct ar_tx_desc *ds; 1215 struct mbuf *m; 1216 uint32_t sum; 1217 uint8_t ridx, hwrate; 1218 int error, totlen; 1219 1220 #if notyet 1221 if (ic->ic_tim_mcast_pending && 1222 IF_IS_EMPTY(&ni->ni_savedq) && 1223 SIMPLEQ_EMPTY(&sc->sc_txq[ATHN_QID_CAB].head)) 1224 ic->ic_tim_mcast_pending = 0; 1225 #endif 1226 if (ic->ic_dtim_count == 0) 1227 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1228 else 1229 ic->ic_dtim_count--; 1230 1231 /* Make sure previous beacon has been sent. */ 1232 if (athn_tx_pending(sc, ATHN_QID_BEACON)) { 1233 DPRINTFN(DBG_INTR, sc, "beacon stuck\n"); 1234 return EBUSY; 1235 } 1236 /* Get new beacon. */ 1237 m = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 1238 if (__predict_false(m == NULL)) 1239 return ENOBUFS; 1240 /* Assign sequence number. */ 1241 /* XXX: use non-QoS tid? */ 1242 wh = mtod(m, struct ieee80211_frame *); 1243 *(uint16_t *)&wh->i_seq[0] = 1244 htole16(ic->ic_bss->ni_txseqs[0] << IEEE80211_SEQ_SEQ_SHIFT); 1245 ic->ic_bss->ni_txseqs[0]++; 1246 1247 /* Unmap and free old beacon if any. */ 1248 if (__predict_true(bf->bf_m != NULL)) { 1249 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1250 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1251 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1252 m_freem(bf->bf_m); 1253 bf->bf_m = NULL; 1254 } 1255 /* DMA map new beacon. */ 1256 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1257 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1258 if (__predict_false(error != 0)) { 1259 m_freem(m); 1260 return error; 1261 } 1262 bf->bf_m = m; 1263 1264 /* Setup Tx descriptor (simplified ar9003_tx()). */ 1265 ds = bf->bf_descs; 1266 memset(ds, 0, sizeof(*ds)); 1267 1268 ds->ds_info = 1269 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1270 SM(AR_TXI_DESC_NDWORDS, 23) | 1271 SM(AR_TXI_QCU_NUM, ATHN_QID_BEACON) | 1272 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1273 1274 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1275 ds->ds_ctl11 = SM(AR_TXC11_FRAME_LEN, totlen); 1276 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, AR_MAX_RATE_POWER); 1277 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, AR_FRAME_TYPE_BEACON); 1278 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1279 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, AR_ENCR_TYPE_CLEAR); 1280 1281 /* Write number of tries. */ 1282 ds->ds_ctl13 = SM(AR_TXC13_XMIT_DATA_TRIES0, 1); 1283 1284 /* Write Tx rate. */ 1285 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1286 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1287 hwrate = athn_rates[ridx].hwrate; 1288 ds->ds_ctl14 = SM(AR_TXC14_XMIT_RATE0, hwrate); 1289 1290 /* Write Tx chains. */ 1291 ds->ds_ctl18 = SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask); 1292 1293 ds->ds_segs[0].ds_data = bf->bf_map->dm_segs[0].ds_addr; 1294 /* Segment length must be a multiple of 4. */ 1295 ds->ds_segs[0].ds_ctl |= SM(AR_TXC_BUF_LEN, 1296 (bf->bf_map->dm_segs[0].ds_len + 3) & ~3); 1297 /* Compute Tx descriptor checksum. */ 1298 sum = ds->ds_info; 1299 sum += ds->ds_segs[0].ds_data; 1300 sum += ds->ds_segs[0].ds_ctl; 1301 sum = (sum >> 16) + (sum & 0xffff); 1302 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1303 1304 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1305 BUS_DMASYNC_PREWRITE); 1306 1307 /* Stop Tx DMA before putting the new beacon on the queue. */ 1308 athn_stop_tx_dma(sc, ATHN_QID_BEACON); 1309 1310 AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr); 1311 1312 for(;;) { 1313 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) 1314 break; 1315 1316 IF_DEQUEUE(&ni->ni_savedq, m); 1317 if (m == NULL) 1318 break; 1319 if (!IF_IS_EMPTY(&ni->ni_savedq)) { 1320 /* more queued frames, set the more data bit */ 1321 wh = mtod(m, struct ieee80211_frame *); 1322 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 1323 } 1324 1325 if (sc->sc_ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) { 1326 ieee80211_free_node(ni); 1327 ifp->if_oerrors++; 1328 break; 1329 } 1330 } 1331 1332 /* Kick Tx. */ 1333 AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON); 1334 AR_WRITE_BARRIER(sc); 1335 return 0; 1336 } 1337 #endif 1338 1339 Static int 1340 ar9003_intr(struct athn_softc *sc) 1341 { 1342 uint32_t intr, intr2, intr5, sync; 1343 1344 /* Get pending interrupts. */ 1345 intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE); 1346 if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) { 1347 intr = AR_READ(sc, AR_INTR_SYNC_CAUSE); 1348 if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0) 1349 return 0; /* Not for us. */ 1350 } 1351 1352 if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 1353 (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 1354 intr = AR_READ(sc, AR_ISR); 1355 else 1356 intr = 0; 1357 sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync; 1358 if (intr == 0 && sync == 0) 1359 return 0; /* Not for us. */ 1360 1361 if (intr != 0) { 1362 if (intr & AR_ISR_BCNMISC) { 1363 intr2 = AR_READ(sc, AR_ISR_S2); 1364 #ifdef notyet 1365 if (intr2 & AR_ISR_S2_TIM) 1366 /* TBD */; 1367 if (intr2 & AR_ISR_S2_TSFOOR) 1368 /* TBD */; 1369 if (intr2 & AR_ISR_S2_BB_WATCHDOG) 1370 /* TBD */; 1371 #endif 1372 } 1373 intr = AR_READ(sc, AR_ISR_RAC); 1374 if (intr == AR_INTR_SPURIOUS) 1375 return 1; 1376 1377 #ifndef IEEE80211_STA_ONLY 1378 if (intr & AR_ISR_SWBA) 1379 ar9003_swba_intr(sc); 1380 #endif 1381 if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 1382 ar9003_rx_intr(sc, ATHN_QID_LP); 1383 if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 1384 ar9003_rx_intr(sc, ATHN_QID_LP); 1385 if (intr & AR_ISR_HP_RXOK) 1386 ar9003_rx_intr(sc, ATHN_QID_HP); 1387 1388 if (intr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 1389 ar9003_tx_intr(sc); 1390 if (intr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) 1391 ar9003_tx_intr(sc); 1392 1393 if (intr & AR_ISR_GENTMR) { 1394 intr5 = AR_READ(sc, AR_ISR_S5_S); 1395 DPRINTFN(DBG_INTR, sc, 1396 "GENTMR trigger=%d thresh=%d\n", 1397 MS(intr5, AR_ISR_S5_GENTIMER_TRIG), 1398 MS(intr5, AR_ISR_S5_GENTIMER_THRESH)); 1399 } 1400 } 1401 if (sync != 0) { 1402 if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 1403 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF); 1404 AR_WRITE(sc, AR_RC, 0); 1405 } 1406 1407 if ((sc->sc_flags & ATHN_FLAG_RFSILENT) && 1408 (sync & AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin))) { 1409 pmf_event_inject(sc->sc_dev, PMFE_RADIO_OFF); 1410 return 1; 1411 } 1412 1413 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync); 1414 (void)AR_READ(sc, AR_INTR_SYNC_CAUSE); 1415 } 1416 return 1; 1417 } 1418 1419 Static int 1420 ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 1421 int txflags) 1422 { 1423 struct ieee80211com *ic = &sc->sc_ic; 1424 struct ieee80211_key *k = NULL; 1425 struct ieee80211_frame *wh; 1426 struct athn_series series[4]; 1427 struct ar_tx_desc *ds; 1428 struct athn_txq *txq; 1429 struct athn_tx_buf *bf; 1430 struct athn_node *an = (void *)ni; 1431 struct mbuf *m1; 1432 uint32_t sum; 1433 uint16_t qos; 1434 uint8_t txpower, type, encrtype, ridx[4]; 1435 int i, error, totlen, hasqos, qid; 1436 1437 /* Grab a Tx buffer from our global free list. */ 1438 bf = SIMPLEQ_FIRST(&sc->sc_txbufs); 1439 KASSERT(bf != NULL); 1440 1441 /* Map 802.11 frame type to hardware frame type. */ 1442 wh = mtod(m, struct ieee80211_frame *); 1443 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1444 IEEE80211_FC0_TYPE_MGT) { 1445 /* NB: Beacons do not use ar9003_tx(). */ 1446 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1447 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1448 type = AR_FRAME_TYPE_PROBE_RESP; 1449 else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1450 IEEE80211_FC0_SUBTYPE_ATIM) 1451 type = AR_FRAME_TYPE_ATIM; 1452 else 1453 type = AR_FRAME_TYPE_NORMAL; 1454 } 1455 else if ((wh->i_fc[0] & 1456 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1457 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_PS_POLL)) { 1458 type = AR_FRAME_TYPE_PSPOLL; 1459 } 1460 else 1461 type = AR_FRAME_TYPE_NORMAL; 1462 1463 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1464 k = ieee80211_crypto_encap(ic, ni, m); 1465 if (k == NULL) 1466 return ENOBUFS; 1467 1468 /* packet header may have moved, reset our local pointer */ 1469 wh = mtod(m, struct ieee80211_frame *); 1470 } 1471 1472 /* XXX 2-byte padding for QoS and 4-addr headers. */ 1473 1474 /* Select the HW Tx queue to use for this frame. */ 1475 if ((hasqos = ieee80211_has_qos(wh))) { 1476 #ifdef notyet_edca 1477 uint8_t tid; 1478 1479 qos = ieee80211_get_qos(wh); 1480 tid = qos & IEEE80211_QOS_TID; 1481 qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)]; 1482 #else 1483 qos = ieee80211_get_qos(wh); 1484 qid = ATHN_QID_AC_BE; 1485 #endif /* notyet_edca */ 1486 } 1487 else if (type == AR_FRAME_TYPE_PSPOLL) { 1488 qos = 0; 1489 qid = ATHN_QID_PSPOLL; 1490 } 1491 else if (txflags & ATHN_TXFLAG_CAB) { 1492 qos = 0; 1493 qid = ATHN_QID_CAB; 1494 } 1495 else { 1496 qos = 0; 1497 qid = ATHN_QID_AC_BE; 1498 } 1499 txq = &sc->sc_txq[qid]; 1500 1501 /* Select the transmit rates to use for this frame. */ 1502 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1503 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 1504 IEEE80211_FC0_TYPE_DATA) { 1505 /* Use lowest rate for all tries. */ 1506 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1507 (ic->ic_curmode == IEEE80211_MODE_11A) ? 1508 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1509 } 1510 else if (ic->ic_fixed_rate != -1) { 1511 /* Use same fixed rate for all tries. */ 1512 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1513 sc->sc_fixed_ridx; 1514 } 1515 else { 1516 int txrate = ni->ni_txrate; 1517 /* Use fallback table of the node. */ 1518 for (i = 0; i < 4; i++) { 1519 ridx[i] = an->ridx[txrate]; 1520 txrate = an->fallback[txrate]; 1521 } 1522 } 1523 1524 if (__predict_false(sc->sc_drvbpf != NULL)) { 1525 struct athn_tx_radiotap_header *tap = &sc->sc_txtap; 1526 1527 tap->wt_flags = 0; 1528 /* Use initial transmit rate. */ 1529 tap->wt_rate = athn_rates[ridx[0]].rate; 1530 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1531 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1532 // XXX tap->wt_hwqueue = qid; 1533 if (ridx[0] != ATHN_RIDX_CCK1 && 1534 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1535 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1536 1537 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 1538 } 1539 1540 /* DMA map mbuf. */ 1541 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1542 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1543 if (__predict_false(error != 0)) { 1544 if (error != EFBIG) { 1545 printf("%s: can't map mbuf (error %d)\n", 1546 device_xname(sc->sc_dev), error); 1547 m_freem(m); 1548 return error; 1549 } 1550 /* 1551 * DMA mapping requires too many DMA segments; linearize 1552 * mbuf in kernel virtual address space and retry. 1553 */ 1554 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1555 if (m1 == NULL) { 1556 m_freem(m); 1557 return ENOBUFS; 1558 } 1559 if (m->m_pkthdr.len > (int)MHLEN) { 1560 MCLGET(m1, M_DONTWAIT); 1561 if (!(m1->m_flags & M_EXT)) { 1562 m_freem(m); 1563 m_freem(m1); 1564 return ENOBUFS; 1565 } 1566 } 1567 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 1568 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1569 m_freem(m); 1570 m = m1; 1571 1572 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1573 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1574 if (error != 0) { 1575 printf("%s: can't map mbuf (error %d)\n", 1576 device_xname(sc->sc_dev), error); 1577 m_freem(m); 1578 return error; 1579 } 1580 } 1581 bf->bf_m = m; 1582 bf->bf_ni = ni; 1583 bf->bf_txflags = txflags; 1584 1585 wh = mtod(m, struct ieee80211_frame *); 1586 1587 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1588 1589 /* Setup Tx descriptor. */ 1590 ds = bf->bf_descs; 1591 memset(ds, 0, sizeof(*ds)); 1592 1593 ds->ds_info = 1594 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1595 SM(AR_TXI_DESC_NDWORDS, 23) | 1596 SM(AR_TXI_QCU_NUM, qid) | 1597 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1598 1599 ds->ds_ctl11 = AR_TXC11_CLR_DEST_MASK; 1600 txpower = AR_MAX_RATE_POWER; /* Get from per-rate registers. */ 1601 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, txpower); 1602 1603 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, type); 1604 1605 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1606 (hasqos && (qos & IEEE80211_QOS_ACKPOLICY_MASK) == 1607 IEEE80211_QOS_ACKPOLICY_NOACK)) 1608 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1609 1610 #if notyet 1611 if (0 && k != NULL) { 1612 uintptr_t entry; 1613 1614 /* 1615 * Map 802.11 cipher to hardware encryption type and 1616 * compute MIC+ICV overhead. 1617 */ 1618 switch (k->k_cipher) { 1619 case IEEE80211_CIPHER_WEP40: 1620 case IEEE80211_CIPHER_WEP104: 1621 encrtype = AR_ENCR_TYPE_WEP; 1622 totlen += 4; 1623 break; 1624 case IEEE80211_CIPHER_TKIP: 1625 encrtype = AR_ENCR_TYPE_TKIP; 1626 totlen += 12; 1627 break; 1628 case IEEE80211_CIPHER_CCMP: 1629 encrtype = AR_ENCR_TYPE_AES; 1630 totlen += 8; 1631 break; 1632 default: 1633 panic("unsupported cipher"); 1634 } 1635 /* 1636 * NB: The key cache entry index is stored in the key 1637 * private field when the key is installed. 1638 */ 1639 entry = (uintptr_t)k->k_priv; 1640 ds->ds_ctl12 |= SM(AR_TXC12_DEST_IDX, entry); 1641 ds->ds_ctl11 |= AR_TXC11_DEST_IDX_VALID; 1642 } 1643 else 1644 #endif 1645 encrtype = AR_ENCR_TYPE_CLEAR; 1646 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, encrtype); 1647 1648 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 1649 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1650 /* NB: Group frames are sent using CCK in 802.11b/g. */ 1651 if (totlen > ic->ic_rtsthreshold) { 1652 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1653 } 1654 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1655 athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) { 1656 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1657 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1658 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1659 ds->ds_ctl11 |= AR_TXC11_CTS_ENABLE; 1660 } 1661 } 1662 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1663 /* Disable multi-rate retries when protection is used. */ 1664 ridx[1] = ridx[2] = ridx[3] = ridx[0]; 1665 } 1666 /* Setup multi-rate retries. */ 1667 for (i = 0; i < 4; i++) { 1668 series[i].hwrate = athn_rates[ridx[i]].hwrate; 1669 if (athn_rates[ridx[i]].phy == IEEE80211_T_DS && 1670 ridx[i] != ATHN_RIDX_CCK1 && 1671 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1672 series[i].hwrate |= 0x04; 1673 series[i].dur = 0; 1674 } 1675 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1676 /* Compute duration for each series. */ 1677 for (i = 0; i < 4; i++) { 1678 series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN, 1679 athn_rates[ridx[i]].rspridx, ic->ic_flags); 1680 } 1681 } 1682 /* If this is a PA training frame, select the Tx chain to use. */ 1683 if (__predict_false(txflags & ATHN_TXFLAG_PAPRD)) { 1684 ds->ds_ctl12 |= SM(AR_TXC12_PAPRD_CHAIN_MASK, 1685 1 << sc->sc_paprd_curchain); 1686 } 1687 1688 /* Write number of tries for each series. */ 1689 ds->ds_ctl13 = 1690 SM(AR_TXC13_XMIT_DATA_TRIES0, 2) | 1691 SM(AR_TXC13_XMIT_DATA_TRIES1, 2) | 1692 SM(AR_TXC13_XMIT_DATA_TRIES2, 2) | 1693 SM(AR_TXC13_XMIT_DATA_TRIES3, 4); 1694 1695 /* Tell HW to update duration field in 802.11 header. */ 1696 if (type != AR_FRAME_TYPE_PSPOLL) 1697 ds->ds_ctl13 |= AR_TXC13_DUR_UPDATE_ENA; 1698 1699 /* Write Tx rate for each series. */ 1700 ds->ds_ctl14 = 1701 SM(AR_TXC14_XMIT_RATE0, series[0].hwrate) | 1702 SM(AR_TXC14_XMIT_RATE1, series[1].hwrate) | 1703 SM(AR_TXC14_XMIT_RATE2, series[2].hwrate) | 1704 SM(AR_TXC14_XMIT_RATE3, series[3].hwrate); 1705 1706 /* Write duration for each series. */ 1707 ds->ds_ctl15 = 1708 SM(AR_TXC15_PACKET_DUR0, series[0].dur) | 1709 SM(AR_TXC15_PACKET_DUR1, series[1].dur); 1710 ds->ds_ctl16 = 1711 SM(AR_TXC16_PACKET_DUR2, series[2].dur) | 1712 SM(AR_TXC16_PACKET_DUR3, series[3].dur); 1713 1714 if ((sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) && 1715 ic->ic_curmode == IEEE80211_MODE_11A) { 1716 /* 1717 * In order to not exceed PCIe power requirements, we only 1718 * use two Tx chains for MCS0~15 on 5GHz band on these chips. 1719 */ 1720 ds->ds_ctl18 = 1721 SM(AR_TXC18_CHAIN_SEL0, 1722 (ridx[0] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1723 SM(AR_TXC18_CHAIN_SEL1, 1724 (ridx[1] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1725 SM(AR_TXC18_CHAIN_SEL2, 1726 (ridx[2] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1727 SM(AR_TXC18_CHAIN_SEL3, 1728 (ridx[3] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask); 1729 } 1730 else { 1731 /* Use the same Tx chains for all tries. */ 1732 ds->ds_ctl18 = 1733 SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask) | 1734 SM(AR_TXC18_CHAIN_SEL1, sc->sc_txchainmask) | 1735 SM(AR_TXC18_CHAIN_SEL2, sc->sc_txchainmask) | 1736 SM(AR_TXC18_CHAIN_SEL3, sc->sc_txchainmask); 1737 } 1738 #ifdef notyet 1739 #ifndef IEEE80211_NO_HT 1740 /* Use the same short GI setting for all tries. */ 1741 if (ic->ic_flags & IEEE80211_F_SHGI) 1742 ds->ds_ctl18 |= AR_TXC18_GI0123; 1743 /* Use the same channel width for all tries. */ 1744 if (ic->ic_flags & IEEE80211_F_CBW40) 1745 ds->ds_ctl18 |= AR_TXC18_2040_0123; 1746 #endif 1747 #endif 1748 1749 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1750 uint8_t protridx, hwrate; 1751 uint16_t dur = 0; 1752 1753 /* Use the same protection mode for all tries. */ 1754 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1755 ds->ds_ctl15 |= AR_TXC15_RTSCTS_QUAL01; 1756 ds->ds_ctl16 |= AR_TXC16_RTSCTS_QUAL23; 1757 } 1758 /* Select protection rate (suboptimal but ok). */ 1759 protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1760 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2; 1761 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1762 /* Account for CTS duration. */ 1763 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1764 athn_rates[protridx].rspridx, ic->ic_flags); 1765 } 1766 dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags); 1767 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1768 /* Account for ACK duration. */ 1769 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1770 athn_rates[ridx[0]].rspridx, ic->ic_flags); 1771 } 1772 /* Write protection frame duration and rate. */ 1773 ds->ds_ctl13 |= SM(AR_TXC13_BURST_DUR, dur); 1774 hwrate = athn_rates[protridx].hwrate; 1775 if (protridx == ATHN_RIDX_CCK2 && 1776 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1777 hwrate |= 0x04; 1778 ds->ds_ctl18 |= SM(AR_TXC18_RTSCTS_RATE, hwrate); 1779 } 1780 1781 ds->ds_ctl11 |= SM(AR_TXC11_FRAME_LEN, totlen); 1782 ds->ds_ctl19 = AR_TXC19_NOT_SOUNDING; 1783 1784 for (i = 0; i < bf->bf_map->dm_nsegs; i++) { 1785 ds->ds_segs[i].ds_data = bf->bf_map->dm_segs[i].ds_addr; 1786 ds->ds_segs[i].ds_ctl = SM(AR_TXC_BUF_LEN, 1787 bf->bf_map->dm_segs[i].ds_len); 1788 } 1789 /* Compute Tx descriptor checksum. */ 1790 sum = ds->ds_info + ds->ds_link; 1791 for (i = 0; i < 4; i++) { 1792 sum += ds->ds_segs[i].ds_data; 1793 sum += ds->ds_segs[i].ds_ctl; 1794 } 1795 sum = (sum >> 16) + (sum & 0xffff); 1796 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1797 1798 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1799 BUS_DMASYNC_PREWRITE); 1800 1801 DPRINTFN(DBG_TX, sc, 1802 "Tx qid=%d nsegs=%d ctl11=0x%x ctl12=0x%x ctl14=0x%x\n", 1803 qid, bf->bf_map->dm_nsegs, ds->ds_ctl11, ds->ds_ctl12, 1804 ds->ds_ctl14); 1805 1806 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 1807 SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list); 1808 1809 /* Queue buffer unless hardware FIFO is already full. */ 1810 if (++txq->queued <= AR9003_TX_QDEPTH) { 1811 AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr); 1812 AR_WRITE_BARRIER(sc); 1813 } 1814 else if (txq->wait == NULL) 1815 txq->wait = bf; 1816 return 0; 1817 } 1818 1819 Static void 1820 ar9003_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c) 1821 { 1822 uint32_t reg; 1823 1824 reg = IEEE80211_IS_CHAN_2GHZ(c) ? 1825 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 1826 if (IEEE80211_IS_CHAN_5GHZ(c) && 1827 (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 1828 reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE; 1829 } 1830 AR_WRITE(sc, AR_PHY_MODE, reg); 1831 AR_WRITE_BARRIER(sc); 1832 } 1833 1834 static __inline uint32_t 1835 ar9003_synth_delay(struct athn_softc *sc) 1836 { 1837 uint32_t delay; 1838 1839 delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY); 1840 if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B) 1841 delay = (delay * 4) / 22; 1842 else 1843 delay = delay / 10; /* in 100ns steps */ 1844 return delay; 1845 } 1846 1847 Static int 1848 ar9003_rf_bus_request(struct athn_softc *sc) 1849 { 1850 int ntries; 1851 1852 /* Request RF Bus grant. */ 1853 AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1854 for (ntries = 0; ntries < 10000; ntries++) { 1855 if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN) 1856 return 0; 1857 DELAY(10); 1858 } 1859 DPRINTFN(DBG_RF, sc, "could not kill baseband Rx"); 1860 return ETIMEDOUT; 1861 } 1862 1863 Static void 1864 ar9003_rf_bus_release(struct athn_softc *sc) 1865 { 1866 /* Wait for the synthesizer to settle. */ 1867 DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar9003_synth_delay(sc)); 1868 1869 /* Release the RF Bus grant. */ 1870 AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0); 1871 AR_WRITE_BARRIER(sc); 1872 } 1873 1874 Static void 1875 ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c, 1876 struct ieee80211_channel *extc) 1877 { 1878 uint32_t phy; 1879 1880 phy = AR_READ(sc, AR_PHY_GEN_CTRL); 1881 phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | 1882 AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH; 1883 #ifndef IEEE80211_NO_HT 1884 if (extc != NULL) { 1885 phy |= AR_PHY_GC_DYN2040_EN; 1886 if (extc > c) /* XXX */ 1887 phy |= AR_PHY_GC_DYN2040_PRI_CH; 1888 } 1889 #endif 1890 /* Turn off Green Field detection for now. */ 1891 phy &= ~AR_PHY_GC_GF_DETECT_EN; 1892 AR_WRITE(sc, AR_PHY_GEN_CTRL, phy); 1893 1894 AR_WRITE(sc, AR_2040_MODE, 1895 (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0); 1896 1897 /* Set global transmit timeout. */ 1898 AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25)); 1899 /* Set carrier sense timeout. */ 1900 AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15)); 1901 AR_WRITE_BARRIER(sc); 1902 } 1903 1904 Static void 1905 ar9003_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c, 1906 struct ieee80211_channel *extc) 1907 { 1908 uint32_t coeff, exp, man, reg; 1909 1910 /* Set Delta Slope (exponent and mantissa). */ 1911 coeff = (100 << 24) / c->ic_freq; 1912 athn_get_delta_slope(coeff, &exp, &man); 1913 DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man); 1914 1915 reg = AR_READ(sc, AR_PHY_TIMING3); 1916 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); 1917 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); 1918 AR_WRITE(sc, AR_PHY_TIMING3, reg); 1919 1920 /* For Short GI, coeff is 9/10 that of normal coeff. */ 1921 coeff = (9 * coeff) / 10; 1922 athn_get_delta_slope(coeff, &exp, &man); 1923 DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man); 1924 1925 reg = AR_READ(sc, AR_PHY_SGI_DELTA); 1926 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); 1927 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); 1928 AR_WRITE(sc, AR_PHY_SGI_DELTA, reg); 1929 AR_WRITE_BARRIER(sc); 1930 } 1931 1932 Static void 1933 ar9003_enable_antenna_diversity(struct athn_softc *sc) 1934 { 1935 AR_SETBITS(sc, AR_PHY_CCK_DETECT, 1936 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1937 AR_WRITE_BARRIER(sc); 1938 } 1939 1940 Static void 1941 ar9003_init_baseband(struct athn_softc *sc) 1942 { 1943 uint32_t synth_delay; 1944 1945 synth_delay = ar9003_synth_delay(sc); 1946 /* Activate the PHY (includes baseband activate and synthesizer on). */ 1947 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 1948 AR_WRITE_BARRIER(sc); 1949 DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay); 1950 } 1951 1952 Static void 1953 ar9003_disable_phy(struct athn_softc *sc) 1954 { 1955 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1956 AR_WRITE_BARRIER(sc); 1957 } 1958 1959 Static void 1960 ar9003_init_chains(struct athn_softc *sc) 1961 { 1962 if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5) 1963 AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 1964 1965 /* Setup chain masks. */ 1966 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); 1967 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); 1968 1969 if (sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) { 1970 /* 1971 * All self-generated frames are sent using two Tx chains 1972 * on these chips to not exceed PCIe power requirements. 1973 */ 1974 AR_WRITE(sc, AR_SELFGEN_MASK, 0x3); 1975 } 1976 else 1977 AR_WRITE(sc, AR_SELFGEN_MASK, sc->sc_txchainmask); 1978 AR_WRITE_BARRIER(sc); 1979 } 1980 1981 Static void 1982 ar9003_set_rxchains(struct athn_softc *sc) 1983 { 1984 if (sc->sc_rxchainmask == 0x3 || sc->sc_rxchainmask == 0x5) { 1985 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); 1986 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); 1987 AR_WRITE_BARRIER(sc); 1988 } 1989 } 1990 1991 #ifdef notused 1992 Static void 1993 ar9003_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 1994 { 1995 /* Sign-extends 9-bit value (assumes upper bits are zeroes). */ 1996 #define SIGN_EXT(v) (((v) ^ 0x100) - 0x100) 1997 uint32_t reg; 1998 int i; 1999 2000 for (i = 0; i < sc->sc_nrxchains; i++) { 2001 reg = AR_READ(sc, AR_PHY_CCA(i)); 2002 nf[i] = MS(reg, AR_PHY_MINCCA_PWR); 2003 nf[i] = SIGN_EXT(nf[i]); 2004 2005 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 2006 nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR); 2007 nf_ext[i] = SIGN_EXT(nf_ext[i]); 2008 } 2009 #undef SIGN_EXT 2010 } 2011 #endif /* notused */ 2012 2013 #ifdef notused 2014 Static void 2015 ar9003_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 2016 { 2017 uint32_t reg; 2018 int i; 2019 2020 for (i = 0; i < sc->sc_nrxchains; i++) { 2021 reg = AR_READ(sc, AR_PHY_CCA(i)); 2022 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); 2023 AR_WRITE(sc, AR_PHY_CCA(i), reg); 2024 2025 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 2026 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); 2027 AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg); 2028 } 2029 AR_WRITE_BARRIER(sc); 2030 } 2031 #endif /* notused */ 2032 2033 #ifdef notused 2034 Static void 2035 ar9003_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c) 2036 { 2037 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2038 int16_t cca_min, cca_max; 2039 int i; 2040 2041 if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 2042 /* Noisefloor calibration not finished. */ 2043 return; 2044 } 2045 /* Noisefloor calibration is finished. */ 2046 ar9003_read_noisefloor(sc, nf, nf_ext); 2047 2048 if (IEEE80211_IS_CHAN_2GHZ(c)) { 2049 cca_min = sc->sc_cca_min_2g; 2050 cca_max = sc->sc_cca_max_2g; 2051 } 2052 else { 2053 cca_min = sc->sc_cca_min_5g; 2054 cca_max = sc->sc_cca_max_5g; 2055 } 2056 /* Update noisefloor history. */ 2057 for (i = 0; i < sc->sc_nrxchains; i++) { 2058 if (nf[i] < cca_min) 2059 nf[i] = cca_min; 2060 else if (nf[i] > cca_max) 2061 nf[i] = cca_max; 2062 if (nf_ext[i] < cca_min) 2063 nf_ext[i] = cca_min; 2064 else if (nf_ext[i] > cca_max) 2065 nf_ext[i] = cca_max; 2066 2067 sc->sc_nf_hist[sc->sc_nf_hist_cur].nf[i] = nf[i]; 2068 sc->sc_nf_hist[sc->sc_nf_hist_cur].nf_ext[i] = nf_ext[i]; 2069 } 2070 if (++sc->sc_nf_hist_cur >= ATHN_NF_CAL_HIST_MAX) 2071 sc->sc_nf_hist_cur = 0; 2072 } 2073 #endif /* notused */ 2074 2075 #ifdef notused 2076 Static void 2077 ar9003_bb_load_noisefloor(struct athn_softc *sc) 2078 { 2079 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2080 int i, ntries; 2081 2082 /* Write filtered noisefloor values. */ 2083 for (i = 0; i < sc->sc_nrxchains; i++) { 2084 nf[i] = sc->sc_nf_priv[i] * 2; 2085 nf_ext[i] = sc->sc_nf_ext_priv[i] * 2; 2086 } 2087 ar9003_write_noisefloor(sc, nf, nf_ext); 2088 2089 /* Load filtered noisefloor values into baseband. */ 2090 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2091 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2092 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2093 /* Wait for load to complete. */ 2094 for (ntries = 0; ntries < 1000; ntries++) { 2095 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) 2096 break; 2097 DELAY(10); 2098 } 2099 if (ntries == 1000) { 2100 DPRINTFN(DBG_RF, sc, "failed to load noisefloor values\n"); 2101 return; 2102 } 2103 2104 /* Restore noisefloor values to initial (max) values. */ 2105 for (i = 0; i < AR_MAX_CHAINS; i++) 2106 nf[i] = nf_ext[i] = -50 * 2; 2107 ar9003_write_noisefloor(sc, nf, nf_ext); 2108 } 2109 #endif /* notused */ 2110 2111 #ifdef notused 2112 Static void 2113 ar9300_noisefloor_calib(struct athn_softc *sc) 2114 { 2115 2116 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2117 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2118 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2119 } 2120 #endif /* notused */ 2121 2122 Static void 2123 ar9003_do_noisefloor_calib(struct athn_softc *sc) 2124 { 2125 2126 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2127 } 2128 2129 PUBLIC int 2130 ar9003_init_calib(struct athn_softc *sc) 2131 { 2132 uint8_t txchainmask, rxchainmask; 2133 uint32_t reg; 2134 int ntries; 2135 2136 /* Save chains masks. */ 2137 txchainmask = sc->sc_txchainmask; 2138 rxchainmask = sc->sc_rxchainmask; 2139 /* Configure hardware before calibration. */ 2140 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE) 2141 txchainmask = rxchainmask = 0x3; 2142 else 2143 txchainmask = rxchainmask = 0x7; 2144 ar9003_init_chains(sc); 2145 2146 /* Perform Tx IQ calibration. */ 2147 ar9003_calib_tx_iq(sc); 2148 /* Disable and re-enable the PHY chips. */ 2149 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2150 AR_WRITE_BARRIER(sc); 2151 DELAY(5); 2152 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 2153 2154 /* Calibrate the AGC. */ 2155 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 2156 /* Poll for offset calibration completion. */ 2157 for (ntries = 0; ntries < 10000; ntries++) { 2158 reg = AR_READ(sc, AR_PHY_AGC_CONTROL); 2159 if (!(reg & AR_PHY_AGC_CONTROL_CAL)) 2160 break; 2161 DELAY(10); 2162 } 2163 if (ntries == 10000) 2164 return ETIMEDOUT; 2165 2166 /* Restore chains masks. */ 2167 sc->sc_txchainmask = txchainmask; 2168 sc->sc_rxchainmask = rxchainmask; 2169 ar9003_init_chains(sc); 2170 2171 return 0; 2172 } 2173 2174 Static void 2175 ar9003_do_calib(struct athn_softc *sc) 2176 { 2177 uint32_t reg; 2178 2179 if (sc->sc_cur_calib_mask & ATHN_CAL_IQ) { 2180 reg = AR_READ(sc, AR_PHY_TIMING4); 2181 reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10); 2182 AR_WRITE(sc, AR_PHY_TIMING4, reg); 2183 AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 2184 AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); 2185 AR_WRITE_BARRIER(sc); 2186 } 2187 else if (sc->sc_cur_calib_mask & ATHN_CAL_TEMP) { 2188 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2189 AR_PHY_65NM_CH0_THERM_LOCAL); 2190 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2191 AR_PHY_65NM_CH0_THERM_START); 2192 AR_WRITE_BARRIER(sc); 2193 } 2194 } 2195 2196 Static void 2197 ar9003_next_calib(struct athn_softc *sc) 2198 { 2199 /* Check if we have any calibration in progress. */ 2200 if (sc->sc_cur_calib_mask != 0) { 2201 if (!(AR_READ(sc, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { 2202 /* Calibration completed for current sample. */ 2203 ar9003_calib_iq(sc); 2204 } 2205 } 2206 } 2207 2208 Static void 2209 ar9003_calib_iq(struct athn_softc *sc) 2210 { 2211 struct athn_iq_cal *cal; 2212 uint32_t reg, i_coff_denom, q_coff_denom; 2213 int32_t i_coff, q_coff; 2214 int i, iq_corr_neg; 2215 2216 for (i = 0; i < AR_MAX_CHAINS; i++) { 2217 cal = &sc->sc_calib.iq[i]; 2218 2219 /* Read IQ calibration measures (clear on read). */ 2220 cal->pwr_meas_i = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_0_B(i)); 2221 cal->pwr_meas_q = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_1_B(i)); 2222 cal->iq_corr_meas = 2223 (int32_t)AR_READ(sc, AR_PHY_IQ_ADC_MEAS_2_B(i)); 2224 } 2225 2226 for (i = 0; i < sc->sc_nrxchains; i++) { 2227 cal = &sc->sc_calib.iq[i]; 2228 2229 if (cal->pwr_meas_q == 0) 2230 continue; 2231 2232 if ((iq_corr_neg = cal->iq_corr_meas < 0)) 2233 cal->iq_corr_meas = -cal->iq_corr_meas; 2234 2235 i_coff_denom = 2236 (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 256; 2237 q_coff_denom = cal->pwr_meas_q / 64; 2238 2239 if (i_coff_denom == 0 || q_coff_denom == 0) 2240 continue; /* Prevents division by zero. */ 2241 2242 i_coff = cal->iq_corr_meas / i_coff_denom; 2243 q_coff = (cal->pwr_meas_i / q_coff_denom) - 64; 2244 2245 if (i_coff > 63) 2246 i_coff = 63; 2247 else if (i_coff < -63) 2248 i_coff = -63; 2249 /* Negate i_coff if iq_corr_meas is positive. */ 2250 if (!iq_corr_neg) 2251 i_coff = -i_coff; 2252 if (q_coff > 63) 2253 q_coff = 63; 2254 else if (q_coff < -63) 2255 q_coff = -63; 2256 2257 DPRINTFN(DBG_RF, sc, "IQ calibration for chain %d\n", i); 2258 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2259 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff); 2260 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff); 2261 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2262 } 2263 2264 /* Apply new settings. */ 2265 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2266 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); 2267 AR_WRITE_BARRIER(sc); 2268 2269 /* IQ calibration done. */ 2270 sc->sc_cur_calib_mask &= ~ATHN_CAL_IQ; 2271 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2272 } 2273 2274 #define DELPT 32 2275 Static int 2276 ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2]) 2277 { 2278 /* Sign-extends 12-bit value (assumes upper bits are zeroes). */ 2279 #define SIGN_EXT(v) (((v) ^ 0x800) - 0x800) 2280 #define SCALE (1 << 15) 2281 #define SHIFT (1 << 8) 2282 struct { 2283 int32_t m, p, c; 2284 } val[2][2]; 2285 int32_t mag[2][2], phs[2][2], cos[2], sin[2]; 2286 int32_t div, f1, f2, f3, m, p, c; 2287 int32_t txmag, txphs, rxmag, rxphs; 2288 int32_t q_coff, i_coff; 2289 int i, j; 2290 2291 /* Extract our twelve signed 12-bit values from res[] array. */ 2292 val[0][0].m = res[0] & 0xfff; 2293 val[0][0].p = (res[0] >> 12) & 0xfff; 2294 val[0][0].c = ((res[0] >> 24) & 0xff) | (res[1] & 0xf) << 8; 2295 2296 val[0][1].m = (res[1] >> 4) & 0xfff; 2297 val[0][1].p = res[2] & 0xfff; 2298 val[0][1].c = (res[2] >> 12) & 0xfff; 2299 2300 val[1][0].m = ((res[2] >> 24) & 0xff) | (res[3] & 0xf) << 8; 2301 val[1][0].p = (res[3] >> 4) & 0xfff; 2302 val[1][0].c = res[4] & 0xfff; 2303 2304 val[1][1].m = (res[4] >> 12) & 0xfff; 2305 val[1][1].p = ((res[4] >> 24) & 0xff) | (res[5] & 0xf) << 8; 2306 val[1][1].c = (res[5] >> 4) & 0xfff; 2307 2308 for (i = 0; i < 2; i++) { 2309 int32_t ymin, ymax; 2310 for (j = 0; j < 2; j++) { 2311 m = SIGN_EXT(val[i][j].m); 2312 p = SIGN_EXT(val[i][j].p); 2313 c = SIGN_EXT(val[i][j].c); 2314 2315 if (p == 0) 2316 return 1; /* Prevent division by 0. */ 2317 2318 mag[i][j] = (m * SCALE) / p; 2319 phs[i][j] = (c * SCALE) / p; 2320 } 2321 sin[i] = ((mag[i][0] - mag[i][1]) * SHIFT) / DELPT; 2322 cos[i] = ((phs[i][0] - phs[i][1]) * SHIFT) / DELPT; 2323 /* Find magnitude by approximation. */ 2324 ymin = MIN(abs(sin[i]), abs(cos[i])); 2325 ymax = MAX(abs(sin[i]), abs(cos[i])); 2326 div = ymax - (ymax / 32) + (ymin / 8) + (ymin / 4); 2327 if (div == 0) 2328 return 1; /* Prevent division by 0. */ 2329 /* Normalize sin and cos by magnitude. */ 2330 sin[i] = (sin[i] * SCALE) / div; 2331 cos[i] = (cos[i] * SCALE) / div; 2332 } 2333 2334 /* Compute IQ mismatch (solve 4x4 linear equation). */ 2335 f1 = cos[0] - cos[1]; 2336 f3 = sin[0] - sin[1]; 2337 f2 = (f1 * f1 + f3 * f3) / SCALE; 2338 if (f2 == 0) 2339 return 1; /* Prevent division by 0. */ 2340 2341 /* Compute Tx magnitude mismatch. */ 2342 txmag = (f1 * ( mag[0][0] - mag[1][0]) + 2343 f3 * ( phs[0][0] - phs[1][0])) / f2; 2344 /* Compute Tx phase mismatch. */ 2345 txphs = (f3 * (-mag[0][0] + mag[1][0]) + 2346 f1 * ( phs[0][0] - phs[1][0])) / f2; 2347 2348 if (txmag == SCALE) 2349 return 1; /* Prevent division by 0. */ 2350 2351 /* Compute Rx magnitude mismatch. */ 2352 rxmag = mag[0][0] - (cos[0] * txmag + sin[0] * txphs) / SCALE; 2353 /* Compute Rx phase mismatch. */ 2354 rxphs = phs[0][0] + (sin[0] * txmag - cos[0] * txphs) / SCALE; 2355 2356 if (-rxmag == SCALE) 2357 return 1; /* Prevent division by 0. */ 2358 2359 txmag = (txmag * SCALE) / (SCALE - txmag); 2360 txphs = -txphs; 2361 2362 q_coff = (txmag * 128) / SCALE; 2363 if (q_coff < -63) 2364 q_coff = -63; 2365 else if (q_coff > 63) 2366 q_coff = 63; 2367 i_coff = (txphs * 256) / SCALE; 2368 if (i_coff < -63) 2369 i_coff = -63; 2370 else if (i_coff > 63) 2371 i_coff = 63; 2372 coeff[0] = q_coff * 128 + i_coff; 2373 2374 rxmag = (-rxmag * SCALE) / (SCALE + rxmag); 2375 rxphs = -rxphs; 2376 2377 q_coff = (rxmag * 128) / SCALE; 2378 if (q_coff < -63) 2379 q_coff = -63; 2380 else if (q_coff > 63) 2381 q_coff = 63; 2382 i_coff = (rxphs * 256) / SCALE; 2383 if (i_coff < -63) 2384 i_coff = -63; 2385 else if (i_coff > 63) 2386 i_coff = 63; 2387 coeff[1] = q_coff * 128 + i_coff; 2388 2389 return 0; 2390 #undef SHIFT 2391 #undef SCALE 2392 #undef SIGN_EXT 2393 } 2394 2395 Static int 2396 ar9003_calib_tx_iq(struct athn_softc *sc) 2397 { 2398 uint32_t reg; 2399 int32_t res[6], coeff[2]; 2400 int i, j, ntries; 2401 2402 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1); 2403 reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT); 2404 AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg); 2405 2406 /* Start Tx IQ calibration. */ 2407 AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL); 2408 /* Wait for completion. */ 2409 for (ntries = 0; ntries < 10000; ntries++) { 2410 reg = AR_READ(sc, AR_PHY_TX_IQCAL_START); 2411 if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL)) 2412 break; 2413 DELAY(10); 2414 } 2415 if (ntries == 10000) 2416 return ETIMEDOUT; 2417 2418 for (i = 0; i < sc->sc_ntxchains; i++) { 2419 /* Read Tx IQ calibration status for this chain. */ 2420 reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i)); 2421 if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED) 2422 return EIO; 2423 /* 2424 * Read Tx IQ calibration results for this chain. 2425 * This consists in twelve signed 12-bit values. 2426 */ 2427 for (j = 0; j < 3; j++) { 2428 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2429 AR_PHY_CHAN_INFO_TAB_S2_READ); 2430 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2431 res[j * 2 + 0] = reg; 2432 2433 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2434 AR_PHY_CHAN_INFO_TAB_S2_READ); 2435 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2436 res[j * 2 + 1] = reg & 0xffff; 2437 } 2438 2439 /* Compute Tx IQ correction. */ 2440 if (ar9003_get_iq_corr(sc, res, coeff) != 0) 2441 return EIO; 2442 2443 /* Write Tx IQ correction coefficients. */ 2444 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)); 2445 reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, 2446 coeff[0]); 2447 AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg); 2448 2449 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2450 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF, 2451 coeff[1] >> 7); 2452 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF, 2453 coeff[1]); 2454 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2455 AR_WRITE_BARRIER(sc); 2456 } 2457 2458 /* Enable Tx IQ correction. */ 2459 AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_3, 2460 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN); 2461 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2462 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN); 2463 AR_WRITE_BARRIER(sc); 2464 return 0; 2465 } 2466 #undef DELPT 2467 2468 /*- 2469 * The power amplifier predistortion state machine works as follows: 2470 * 1) Disable digital predistorters for all Tx chains 2471 * 2) Repeat steps 3~7 for all Tx chains 2472 * 3) Force Tx gain to that of training signal 2473 * 4) Send training signal (asynchronous) 2474 * 5) Wait for training signal to complete (asynchronous) 2475 * 6) Read PA measurements (input power, output power, output phase) 2476 * 7) Compute the predistortion function that linearizes PA output 2477 * 8) Write predistortion functions to hardware tables for all Tx chains 2478 * 9) Enable digital predistorters for all Tx chains 2479 */ 2480 #ifdef notused 2481 Static void 2482 ar9003_paprd_calib(struct athn_softc *sc, struct ieee80211_channel *c) 2483 { 2484 static const int scaling[] = { 2485 261376, 248079, 233759, 220464, 2486 208194, 196949, 185706, 175487 2487 }; 2488 struct athn_ops *ops = &sc->sc_ops; 2489 uint32_t reg, ht20mask, ht40mask; 2490 int i; 2491 2492 /* Read PA predistortion masks from ROM. */ 2493 ops->get_paprd_masks(sc, c, &ht20mask, &ht40mask); 2494 2495 /* AM-to-AM: amplifier's amplitude characteristic. */ 2496 reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM); 2497 reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask); 2498 AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg); 2499 2500 /* AM-to-PM: amplifier's phase transfer characteristic. */ 2501 reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM); 2502 reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask); 2503 AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg); 2504 2505 reg = AR_READ(sc, AR_PHY_PAPRD_HT40); 2506 reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask); 2507 AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg); 2508 2509 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2510 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2511 AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE); 2512 2513 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i)); 2514 reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181); 2515 reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361); 2516 reg &= ~AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA; 2517 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA; 2518 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA; 2519 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg); 2520 2521 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i)); 2522 reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3); 2523 AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg); 2524 } 2525 2526 /* Disable all digital predistorters during calibration. */ 2527 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2528 AR_CLRBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2529 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 2530 } 2531 AR_WRITE_BARRIER(sc); 2532 2533 /* 2534 * Configure training signal. 2535 */ 2536 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1); 2537 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28); 2538 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30); 2539 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE; 2540 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE; 2541 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE; 2542 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE; 2543 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE; 2544 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg); 2545 2546 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL2, 147); 2547 2548 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3); 2549 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4); 2550 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4); 2551 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7); 2552 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1); 2553 if (AR_SREV_9485(sc)) 2554 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3); 2555 else 2556 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6); 2557 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15); 2558 reg |= AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE; 2559 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg); 2560 2561 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4); 2562 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0); 2563 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400); 2564 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100); 2565 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg); 2566 2567 for (i = 0; i < __arraycount(scaling); i++) { 2568 reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i)); 2569 reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]); 2570 AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg); 2571 } 2572 2573 /* Save Tx gain table. */ 2574 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE; i++) 2575 sc->sc_txgain[i] = AR_READ(sc, AR_PHY_TXGAIN_TABLE(i)); 2576 2577 /* Set Tx power of training signal (use setting for MCS0). */ 2578 sc->sc_trainpow = MS(AR_READ(sc, AR_PHY_PWRTX_RATE5), 2579 AR_PHY_PWRTX_RATE5_POWERTXHT20_0) - 4; 2580 2581 /* 2582 * Start PA predistortion calibration state machine. 2583 */ 2584 /* Find first available Tx chain. */ 2585 sc->sc_paprd_curchain = 0; 2586 while (!(sc->sc_txchainmask & (1 << sc->sc_paprd_curchain))) 2587 sc->sc_paprd_curchain++; 2588 2589 /* Make sure training done bit is clear. */ 2590 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 2591 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 2592 AR_WRITE_BARRIER(sc); 2593 2594 /* Transmit training signal. */ 2595 ar9003_paprd_tx_tone(sc); 2596 } 2597 #endif /* notused */ 2598 2599 Static int 2600 ar9003_get_desired_txgain(struct athn_softc *sc, int chain, int pow) 2601 { 2602 int32_t scale, atemp, avolt, tempcal, voltcal, temp, volt; 2603 int32_t tempcorr, voltcorr; 2604 uint32_t reg; 2605 int8_t delta; 2606 2607 scale = MS(AR_READ(sc, AR_PHY_TPC_12), 2608 AR_PHY_TPC_12_DESIRED_SCALE_HT40_5); 2609 2610 reg = AR_READ(sc, AR_PHY_TPC_19); 2611 atemp = MS(reg, AR_PHY_TPC_19_ALPHA_THERM); 2612 avolt = MS(reg, AR_PHY_TPC_19_ALPHA_VOLT); 2613 2614 reg = AR_READ(sc, AR_PHY_TPC_18); 2615 tempcal = MS(reg, AR_PHY_TPC_18_THERM_CAL); 2616 voltcal = MS(reg, AR_PHY_TPC_18_VOLT_CAL); 2617 2618 reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4); 2619 temp = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_THERM); 2620 volt = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_VOLT); 2621 2622 delta = (int8_t)MS(AR_READ(sc, AR_PHY_TPC_11_B(chain)), 2623 AR_PHY_TPC_11_OLPC_GAIN_DELTA); 2624 2625 /* Compute temperature and voltage correction. */ 2626 tempcorr = (atemp * (temp - tempcal) + 128) / 256; 2627 voltcorr = (avolt * (volt - voltcal) + 64) / 128; 2628 2629 /* Compute desired Tx gain. */ 2630 return pow - delta - tempcorr - voltcorr + scale; 2631 } 2632 2633 Static void 2634 ar9003_force_txgain(struct athn_softc *sc, uint32_t txgain) 2635 { 2636 uint32_t reg; 2637 2638 reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN); 2639 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN, 2640 MS(txgain, AR_PHY_TXGAIN_TXBB1DBGAIN)); 2641 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN, 2642 MS(txgain, AR_PHY_TXGAIN_TXBB6DBGAIN)); 2643 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN, 2644 MS(txgain, AR_PHY_TXGAIN_TXMXRGAIN)); 2645 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA, 2646 MS(txgain, AR_PHY_TXGAIN_PADRVGNA)); 2647 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB, 2648 MS(txgain, AR_PHY_TXGAIN_PADRVGNB)); 2649 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC, 2650 MS(txgain, AR_PHY_TXGAIN_PADRVGNC)); 2651 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND, 2652 MS(txgain, AR_PHY_TXGAIN_PADRVGND)); 2653 reg &= ~AR_PHY_TX_FORCED_GAIN_ENABLE_PAL; 2654 reg &= ~AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN; 2655 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg); 2656 2657 reg = AR_READ(sc, AR_PHY_TPC_1); 2658 reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0); 2659 reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN; 2660 AR_WRITE(sc, AR_PHY_TPC_1, reg); 2661 AR_WRITE_BARRIER(sc); 2662 } 2663 2664 Static void 2665 ar9003_set_training_gain(struct athn_softc *sc, int chain) 2666 { 2667 size_t i; 2668 int gain; 2669 2670 /* 2671 * Get desired gain for training signal power (take into account 2672 * current temperature/voltage). 2673 */ 2674 gain = ar9003_get_desired_txgain(sc, chain, sc->sc_trainpow); 2675 /* Find entry in table. */ 2676 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE - 1; i++) 2677 if ((int)MS(sc->sc_txgain[i], AR_PHY_TXGAIN_INDEX) >= gain) 2678 break; 2679 ar9003_force_txgain(sc, sc->sc_txgain[i]); 2680 } 2681 2682 Static int 2683 ar9003_paprd_tx_tone(struct athn_softc *sc) 2684 { 2685 #define TONE_LEN 1800 2686 struct ieee80211com *ic = &sc->sc_ic; 2687 struct ieee80211_frame *wh; 2688 struct ieee80211_node *ni; 2689 struct mbuf *m; 2690 int error; 2691 2692 /* Build a Null (no data) frame of TONE_LEN bytes. */ 2693 m = MCLGETI(NULL, M_DONTWAIT, NULL, TONE_LEN); 2694 if (m == NULL) 2695 return ENOBUFS; 2696 memset(mtod(m, void *), 0, TONE_LEN); 2697 wh = mtod(m, struct ieee80211_frame *); 2698 wh->i_fc[0] = IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_NODATA; 2699 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 2700 *(uint16_t *)wh->i_dur = htole16(10); /* XXX */ 2701 IEEE80211_ADDR_COPY(wh->i_addr1, ic->ic_myaddr); 2702 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 2703 IEEE80211_ADDR_COPY(wh->i_addr3, ic->ic_myaddr); 2704 m->m_pkthdr.len = m->m_len = TONE_LEN; 2705 2706 /* Set gain of training signal. */ 2707 ar9003_set_training_gain(sc, sc->sc_paprd_curchain); 2708 2709 /* Transmit training signal. */ 2710 ni = ieee80211_ref_node(ic->ic_bss); 2711 if ((error = ar9003_tx(sc, m, ni, ATHN_TXFLAG_PAPRD)) != 0) 2712 ieee80211_free_node(ni); 2713 return error; 2714 #undef TONE_LEN 2715 } 2716 2717 static __inline int 2718 get_scale(int val) 2719 { 2720 int log = 0; 2721 2722 /* Find the log base 2 (position of highest bit set). */ 2723 while (val >>= 1) 2724 log++; 2725 2726 return (log > 10) ? log - 10 : 0; 2727 } 2728 2729 /* 2730 * Compute predistortion function to linearize power amplifier output based 2731 * on feedback from training signal. 2732 */ 2733 Static int 2734 ar9003_compute_predistortion(struct athn_softc *sc, const uint32_t *lo, 2735 const uint32_t *hi) 2736 { 2737 #define NBINS 23 2738 int chain = sc->sc_paprd_curchain; 2739 int x[NBINS + 1], y[NBINS + 1], t[NBINS + 1]; 2740 int b1[NBINS + 1], b2[NBINS + 1], xtilde[NBINS + 1]; 2741 int nsamples, txsum, rxsum, rosum, maxidx; 2742 int order, order5x, order5xrem, order3x, order3xrem, y5, y3; 2743 int icept, G, I, L, M, angle, xnonlin, y2, y4, sumy2, sumy4; 2744 int alpha, beta, scale, Qalpha, Qbeta, Qscale, Qx, Qb1, Qb2; 2745 int tavg, ttilde, maxb1abs, maxb2abs, maxxtildeabs, in; 2746 int tmp, i; 2747 2748 /* Set values at origin. */ 2749 x[0] = y[0] = t[0] = 0; 2750 2751 #define SCALE 32 2752 maxidx = 0; 2753 for (i = 0; i < NBINS; i++) { 2754 nsamples = lo[i] & 0xffff; 2755 /* Skip bins that contain 16 or less samples. */ 2756 if (nsamples <= 16) { 2757 x[i + 1] = y[i + 1] = t[i + 1] = 0; 2758 continue; 2759 } 2760 txsum = (hi[i] & 0x7ff) << 16 | lo[i] >> 16; 2761 rxsum = (lo[i + NBINS] & 0xffff) << 5 | 2762 ((hi[i] >> 11) & 0x1f); 2763 rosum = (hi[i + NBINS] & 0x7ff) << 16 | hi[i + NBINS] >> 16; 2764 /* Sign-extend 27-bit value. */ 2765 rosum = (rosum ^ 0x4000000) - 0x4000000; 2766 2767 txsum *= SCALE; 2768 rxsum *= SCALE; 2769 rosum *= SCALE; 2770 2771 x[i + 1] = ((txsum + nsamples) / nsamples + SCALE) / SCALE; 2772 y[i + 1] = ((rxsum + nsamples) / nsamples + SCALE) / SCALE + 2773 SCALE * maxidx + SCALE / 2; 2774 t[i + 1] = (rosum + nsamples) / nsamples; 2775 maxidx++; 2776 } 2777 #undef SCALE 2778 2779 #define SCALE_LOG 8 2780 #define SCALE (1 << SCALE_LOG) 2781 if (x[6] == x[3]) 2782 return 1; /* Prevent division by 0. */ 2783 G = ((y[6] - y[3]) * SCALE + (x[6] - x[3])) / (x[6] - x[3]); 2784 if (G == 0) 2785 return 1; /* Prevent division by 0. */ 2786 2787 sc->sc_gain1[chain] = G; /* Save low signal gain. */ 2788 2789 /* Find interception point. */ 2790 icept = (G * (x[0] - x[3]) + SCALE) / SCALE + y[3]; 2791 for (i = 0; i <= 3; i++) { 2792 y[i] = i * 32; 2793 x[i] = (y[i] * SCALE + G) / G; 2794 } 2795 for (i = 4; i <= maxidx; i++) 2796 y[i] -= icept; 2797 2798 xnonlin = x[maxidx] - (y[maxidx] * SCALE + G) / G; 2799 order = (xnonlin + y[maxidx]) / y[maxidx]; 2800 if (order == 0) 2801 M = 10; 2802 else if (order == 1) 2803 M = 9; 2804 else 2805 M = 8; 2806 2807 I = (maxidx >= 16) ? 7 : maxidx / 2; 2808 L = maxidx - I; 2809 2810 sumy2 = sumy4 = y2 = y4 = 0; 2811 for (i = 0; i <= L; i++) { 2812 if (y[i + I] == 0) 2813 return 1; /* Prevent division by 0. */ 2814 2815 xnonlin = x[i + I] - ((y[i + I] * SCALE) + G) / G; 2816 xtilde[i] = ((xnonlin << M) + y[i + I]) / y[i + I]; 2817 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2818 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2819 2820 y2 = (y[i + I] * y[i + I] + SCALE * SCALE) / (SCALE * SCALE); 2821 2822 sumy2 += y2; 2823 sumy4 += y2 * y2; 2824 2825 b1[i] = y2 * (L + 1); 2826 b2[i] = y2; 2827 } 2828 for (i = 0; i <= L; i++) { 2829 b1[i] -= sumy2; 2830 b2[i] = sumy4 - sumy2 * b2[i]; 2831 } 2832 2833 maxxtildeabs = maxb1abs = maxb2abs = 0; 2834 for (i = 0; i <= L; i++) { 2835 tmp = abs(xtilde[i]); 2836 if (tmp > maxxtildeabs) 2837 maxxtildeabs = tmp; 2838 2839 tmp = abs(b1[i]); 2840 if (tmp > maxb1abs) 2841 maxb1abs = tmp; 2842 2843 tmp = abs(b2[i]); 2844 if (tmp > maxb2abs) 2845 maxb2abs = tmp; 2846 } 2847 Qx = get_scale(maxxtildeabs); 2848 Qb1 = get_scale(maxb1abs); 2849 Qb2 = get_scale(maxb2abs); 2850 for (i = 0; i <= L; i++) { 2851 xtilde[i] /= 1 << Qx; 2852 b1[i] /= 1 << Qb1; 2853 b2[i] /= 1 << Qb2; 2854 } 2855 2856 alpha = beta = 0; 2857 for (i = 0; i <= L; i++) { 2858 alpha += b1[i] * xtilde[i]; 2859 beta += b2[i] * xtilde[i]; 2860 } 2861 2862 scale = ((y4 / SCALE_LOG) * (L + 1) - 2863 (y2 / SCALE_LOG) * sumy2) * SCALE_LOG; 2864 2865 Qscale = get_scale(abs(scale)); 2866 scale /= 1 << Qscale; 2867 Qalpha = get_scale(abs(alpha)); 2868 alpha /= 1 << Qalpha; 2869 Qbeta = get_scale(abs(beta)); 2870 beta /= 1 << Qbeta; 2871 2872 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale; 2873 order5x = 1 << (order / 5); 2874 order5xrem = 1 << (order % 5); 2875 2876 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale; 2877 order3x = 1 << (order / 3); 2878 order3xrem = 1 << (order % 3); 2879 2880 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2881 tmp = i * 32; 2882 2883 /* Fifth order. */ 2884 y5 = ((beta * tmp) / 64) / order5x; 2885 y5 = (y5 * tmp) / order5x; 2886 y5 = (y5 * tmp) / order5x; 2887 y5 = (y5 * tmp) / order5x; 2888 y5 = (y5 * tmp) / order5x; 2889 y5 = y5 / order5xrem; 2890 2891 /* Third oder. */ 2892 y3 = (alpha * tmp) / order3x; 2893 y3 = (y3 * tmp) / order3x; 2894 y3 = (y3 * tmp) / order3x; 2895 y3 = y3 / order3xrem; 2896 2897 in = y5 + y3 + (SCALE * tmp) / G; 2898 if (i >= 2 && in < sc->sc_pa_in[chain][i - 1]) { 2899 in = sc->sc_pa_in[chain][i - 1] + 2900 (sc->sc_pa_in[chain][i - 1] - 2901 sc->sc_pa_in[chain][i - 2]); 2902 } 2903 if (in > 1400) 2904 in = 1400; 2905 sc->sc_pa_in[chain][i] = in; 2906 } 2907 2908 /* Compute average theta of first 5 bins (linear region). */ 2909 tavg = 0; 2910 for (i = 1; i <= 5; i++) 2911 tavg += t[i]; 2912 tavg /= 5; 2913 for (i = 1; i <= 5; i++) 2914 t[i] = 0; 2915 for (i = 6; i <= maxidx; i++) 2916 t[i] -= tavg; 2917 2918 alpha = beta = 0; 2919 for (i = 0; i <= L; i++) { 2920 ttilde = ((t[i + I] << M) + y[i + I]) / y[i + I]; 2921 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2922 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2923 2924 alpha += b2[i] * ttilde; 2925 beta += b1[i] * ttilde; 2926 } 2927 2928 Qalpha = get_scale(abs(alpha)); 2929 alpha /= 1 << Qalpha; 2930 Qbeta = get_scale(abs(beta)); 2931 beta /= 1 << Qbeta; 2932 2933 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale + 5; 2934 order5x = 1 << (order / 5); 2935 order5xrem = 1 << (order % 5); 2936 2937 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale + 5; 2938 order3x = 1 << (order / 3); 2939 order3xrem = 1 << (order % 3); 2940 2941 for (i = 0; i <= 4; i++) 2942 sc->sc_angle[chain][i] = 0; /* Linear at that range. */ 2943 for (i = 5; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2944 tmp = i * 32; 2945 2946 /* Fifth order. */ 2947 if (beta > 0) 2948 y5 = (((beta * tmp - 64) / 64) - order5x) / order5x; 2949 else 2950 y5 = (((beta * tmp - 64) / 64) + order5x) / order5x; 2951 y5 = (y5 * tmp) / order5x; 2952 y5 = (y5 * tmp) / order5x; 2953 y5 = (y5 * tmp) / order5x; 2954 y5 = (y5 * tmp) / order5x; 2955 y5 = y5 / order5xrem; 2956 2957 /* Third oder. */ 2958 if (beta > 0) /* XXX alpha? */ 2959 y3 = (alpha * tmp - order3x) / order3x; 2960 else 2961 y3 = (alpha * tmp + order3x) / order3x; 2962 y3 = (y3 * tmp) / order3x; 2963 y3 = (y3 * tmp) / order3x; 2964 y3 = y3 / order3xrem; 2965 2966 angle = y5 + y3; 2967 if (angle < -150) 2968 angle = -150; 2969 else if (angle > 150) 2970 angle = 150; 2971 sc->sc_angle[chain][i] = angle; 2972 } 2973 /* Angle for entry 4 is derived from angle for entry 5. */ 2974 sc->sc_angle[chain][4] = (sc->sc_angle[chain][5] + 2) / 2; 2975 2976 return 0; 2977 #undef SCALE 2978 #undef SCALE_LOG 2979 #undef NBINS 2980 } 2981 2982 Static void 2983 ar9003_enable_predistorter(struct athn_softc *sc, int chain) 2984 { 2985 uint32_t reg; 2986 int i; 2987 2988 /* Write digital predistorter lookup table. */ 2989 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2990 AR_WRITE(sc, AR_PHY_PAPRD_MEM_TAB_B(chain, i), 2991 SM(AR_PHY_PAPRD_PA_IN, sc->sc_pa_in[chain][i]) | 2992 SM(AR_PHY_PAPRD_ANGLE, sc->sc_angle[chain][i])); 2993 } 2994 2995 reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain)); 2996 reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->sc_gain1[chain]); 2997 AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg); 2998 2999 /* Indicate Tx power used for calibration (training signal). */ 3000 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain)); 3001 reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->sc_trainpow); 3002 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg); 3003 3004 /* Enable digital predistorter for this chain. */ 3005 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(chain), 3006 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 3007 AR_WRITE_BARRIER(sc); 3008 } 3009 3010 Static void 3011 ar9003_paprd_enable(struct athn_softc *sc) 3012 { 3013 int i; 3014 3015 /* Enable digital predistorters for all Tx chains. */ 3016 for (i = 0; i < AR9003_MAX_CHAINS; i++) 3017 if (sc->sc_txchainmask & (1 << i)) 3018 ar9003_enable_predistorter(sc, i); 3019 } 3020 3021 /* 3022 * This function is called when our training signal has been sent. 3023 */ 3024 Static void 3025 ar9003_paprd_tx_tone_done(struct athn_softc *sc) 3026 { 3027 uint32_t lo[48], hi[48]; 3028 size_t i; 3029 3030 /* Make sure training is complete. */ 3031 if (!(AR_READ(sc, AR_PHY_PAPRD_TRAINER_STAT1) & 3032 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE)) 3033 return; 3034 3035 /* Read feedback from training signal. */ 3036 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 3037 for (i = 0; i < __arraycount(lo); i++) 3038 lo[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 3039 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 3040 for (i = 0; i < __arraycount(hi); i++) 3041 hi[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 3042 3043 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 3044 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 3045 3046 /* Compute predistortion function based on this feedback. */ 3047 if (ar9003_compute_predistortion(sc, lo, hi) != 0) 3048 return; 3049 3050 /* Get next available Tx chain. */ 3051 while (++sc->sc_paprd_curchain < AR9003_MAX_CHAINS) 3052 if (sc->sc_txchainmask & (1 << sc->sc_paprd_curchain)) 3053 break; 3054 if (sc->sc_paprd_curchain == AR9003_MAX_CHAINS) { 3055 /* All Tx chains measured; enable digital predistortion. */ 3056 ar9003_paprd_enable(sc); 3057 } 3058 else /* Measure next Tx chain. */ 3059 ar9003_paprd_tx_tone(sc); 3060 } 3061 3062 PUBLIC void 3063 ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT]) 3064 { 3065 3066 /* Make sure forced gain is disabled. */ 3067 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, 0); 3068 3069 AR_WRITE(sc, AR_PHY_PWRTX_RATE1, 3070 (power[ATHN_POWER_OFDM18 ] & 0x3f) << 24 | 3071 (power[ATHN_POWER_OFDM12 ] & 0x3f) << 16 | 3072 (power[ATHN_POWER_OFDM9 ] & 0x3f) << 8 | 3073 (power[ATHN_POWER_OFDM6 ] & 0x3f)); 3074 AR_WRITE(sc, AR_PHY_PWRTX_RATE2, 3075 (power[ATHN_POWER_OFDM54 ] & 0x3f) << 24 | 3076 (power[ATHN_POWER_OFDM48 ] & 0x3f) << 16 | 3077 (power[ATHN_POWER_OFDM36 ] & 0x3f) << 8 | 3078 (power[ATHN_POWER_OFDM24 ] & 0x3f)); 3079 AR_WRITE(sc, AR_PHY_PWRTX_RATE3, 3080 (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 | 3081 (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 | 3082 /* NB: No eXtended Range for AR9003. */ 3083 (power[ATHN_POWER_CCK1_LP ] & 0x3f)); 3084 AR_WRITE(sc, AR_PHY_PWRTX_RATE4, 3085 (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 | 3086 (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 | 3087 (power[ATHN_POWER_CCK55_SP] & 0x3f) << 8 | 3088 (power[ATHN_POWER_CCK55_LP] & 0x3f)); 3089 /* 3090 * NB: AR_PHY_PWRTX_RATE5 needs to be written even if HT is disabled 3091 * because it is read by PA predistortion functions. 3092 */ 3093 AR_WRITE(sc, AR_PHY_PWRTX_RATE5, 3094 (power[ATHN_POWER_HT20( 5)] & 0x3f) << 24 | 3095 (power[ATHN_POWER_HT20( 4)] & 0x3f) << 16 | 3096 (power[ATHN_POWER_HT20( 1)] & 0x3f) << 8 | 3097 (power[ATHN_POWER_HT20( 0)] & 0x3f)); 3098 #ifndef IEEE80211_NO_HT 3099 AR_WRITE(sc, AR_PHY_PWRTX_RATE6, 3100 (power[ATHN_POWER_HT20(13)] & 0x3f) << 24 | 3101 (power[ATHN_POWER_HT20(12)] & 0x3f) << 16 | 3102 (power[ATHN_POWER_HT20( 7)] & 0x3f) << 8 | 3103 (power[ATHN_POWER_HT20( 6)] & 0x3f)); 3104 AR_WRITE(sc, AR_PHY_PWRTX_RATE7, 3105 (power[ATHN_POWER_HT40( 5)] & 0x3f) << 24 | 3106 (power[ATHN_POWER_HT40( 4)] & 0x3f) << 16 | 3107 (power[ATHN_POWER_HT40( 1)] & 0x3f) << 8 | 3108 (power[ATHN_POWER_HT40( 0)] & 0x3f)); 3109 AR_WRITE(sc, AR_PHY_PWRTX_RATE8, 3110 (power[ATHN_POWER_HT40(13)] & 0x3f) << 24 | 3111 (power[ATHN_POWER_HT40(12)] & 0x3f) << 16 | 3112 (power[ATHN_POWER_HT40( 7)] & 0x3f) << 8 | 3113 (power[ATHN_POWER_HT40( 6)] & 0x3f)); 3114 AR_WRITE(sc, AR_PHY_PWRTX_RATE10, 3115 (power[ATHN_POWER_HT20(21)] & 0x3f) << 24 | 3116 (power[ATHN_POWER_HT20(20)] & 0x3f) << 16 | 3117 (power[ATHN_POWER_HT20(15)] & 0x3f) << 8 | 3118 (power[ATHN_POWER_HT20(14)] & 0x3f)); 3119 AR_WRITE(sc, AR_PHY_PWRTX_RATE11, 3120 (power[ATHN_POWER_HT40(23)] & 0x3f) << 24 | 3121 (power[ATHN_POWER_HT40(22)] & 0x3f) << 16 | 3122 (power[ATHN_POWER_HT20(23)] & 0x3f) << 8 | 3123 (power[ATHN_POWER_HT20(22)] & 0x3f)); 3124 AR_WRITE(sc, AR_PHY_PWRTX_RATE12, 3125 (power[ATHN_POWER_HT40(21)] & 0x3f) << 24 | 3126 (power[ATHN_POWER_HT40(20)] & 0x3f) << 16 | 3127 (power[ATHN_POWER_HT40(15)] & 0x3f) << 8 | 3128 (power[ATHN_POWER_HT40(14)] & 0x3f)); 3129 #endif 3130 AR_WRITE_BARRIER(sc); 3131 } 3132 3133 Static void 3134 ar9003_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3135 { 3136 #define X(x) ((uint32_t)(x) << 2) 3137 const struct athn_gain *prog = sc->sc_rx_gain; 3138 const uint32_t *pvals; 3139 int i; 3140 3141 if (IEEE80211_IS_CHAN_2GHZ(c)) 3142 pvals = prog->vals_2g; 3143 else 3144 pvals = prog->vals_5g; 3145 for (i = 0; i < prog->nregs; i++) 3146 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3147 AR_WRITE_BARRIER(sc); 3148 #undef X 3149 } 3150 3151 Static void 3152 ar9003_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3153 { 3154 #define X(x) ((uint32_t)(x) << 2) 3155 const struct athn_gain *prog = sc->sc_tx_gain; 3156 const uint32_t *pvals; 3157 int i; 3158 3159 if (IEEE80211_IS_CHAN_2GHZ(c)) 3160 pvals = prog->vals_2g; 3161 else 3162 pvals = prog->vals_5g; 3163 for (i = 0; i < prog->nregs; i++) 3164 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3165 AR_WRITE_BARRIER(sc); 3166 #undef X 3167 } 3168 3169 Static void 3170 ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c, 3171 struct ieee80211_channel *extc) 3172 { 3173 #define X(x) ((uint32_t)(x) << 2) 3174 struct athn_ops *ops = &sc->sc_ops; 3175 const struct athn_ini *ini = sc->sc_ini; 3176 const uint32_t *pvals; 3177 uint32_t reg; 3178 int i; 3179 3180 /* 3181 * The common init values include the pre and core phases for the 3182 * SoC, MAC, BB and Radio subsystems. 3183 */ 3184 DPRINTFN(DBG_INIT, sc, "writing pre and core init vals\n"); 3185 for (i = 0; i < ini->ncmregs; i++) { 3186 AR_WRITE(sc, X(ini->cmregs[i]), ini->cmvals[i]); 3187 if (AR_IS_ANALOG_REG(X(ini->cmregs[i]))) 3188 DELAY(100); 3189 if ((i & 0x1f) == 0) 3190 DELAY(1); 3191 } 3192 3193 /* 3194 * The modal init values include the post phase for the SoC, MAC, 3195 * BB and Radio subsystems. 3196 */ 3197 #ifndef IEEE80211_NO_HT 3198 if (extc != NULL) { 3199 if (IEEE80211_IS_CHAN_2GHZ(c)) 3200 pvals = ini->vals_2g40; 3201 else 3202 pvals = ini->vals_5g40; 3203 } 3204 else 3205 #endif 3206 { 3207 if (IEEE80211_IS_CHAN_2GHZ(c)) 3208 pvals = ini->vals_2g20; 3209 else 3210 pvals = ini->vals_5g20; 3211 } 3212 DPRINTFN(DBG_INIT, sc, "writing post init vals\n"); 3213 for (i = 0; i < ini->nregs; i++) { 3214 AR_WRITE(sc, X(ini->regs[i]), pvals[i]); 3215 if (AR_IS_ANALOG_REG(X(ini->regs[i]))) 3216 DELAY(100); 3217 if ((i & 0x1f) == 0) 3218 DELAY(1); 3219 } 3220 3221 if (sc->sc_rx_gain != NULL) 3222 ar9003_reset_rx_gain(sc, c); 3223 if (sc->sc_tx_gain != NULL) 3224 ar9003_reset_tx_gain(sc, c); 3225 3226 if (IEEE80211_IS_CHAN_5GHZ(c) && 3227 (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 3228 /* Update modal values for fast PLL clock. */ 3229 #ifndef IEEE80211_NO_HT 3230 if (extc != NULL) 3231 pvals = ini->fastvals_5g40; 3232 else 3233 #endif 3234 pvals = ini->fastvals_5g20; 3235 DPRINTFN(DBG_INIT, sc, "writing fast pll clock init vals\n"); 3236 for (i = 0; i < ini->nfastregs; i++) { 3237 AR_WRITE(sc, X(ini->fastregs[i]), pvals[i]); 3238 if (AR_IS_ANALOG_REG(X(ini->fastregs[i]))) 3239 DELAY(100); 3240 if ((i & 0x1f) == 0) 3241 DELAY(1); 3242 } 3243 } 3244 3245 /* 3246 * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted 3247 * descriptor status. 3248 */ 3249 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 3250 3251 reg = AR_READ(sc, AR_PCU_MISC_MODE2); 3252 reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE; 3253 reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX; 3254 reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP; 3255 AR_WRITE(sc, AR_PCU_MISC_MODE2, reg); 3256 AR_WRITE_BARRIER(sc); 3257 3258 ar9003_set_phy(sc, c, extc); 3259 ar9003_init_chains(sc); 3260 3261 ops->set_txpower(sc, c, extc); 3262 #undef X 3263 } 3264 3265 PUBLIC void 3266 ar9003_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3267 uint8_t ctl, const uint8_t *fbins, 3268 const struct ar_cal_target_power_leg *tgt, int nchans, uint8_t tpow[4]) 3269 { 3270 uint8_t fbin; 3271 int i, delta, lo, hi; 3272 3273 lo = hi = -1; 3274 fbin = athn_chan2fbin(c); 3275 for (i = 0; i < nchans; i++) { 3276 delta = fbin - fbins[i]; 3277 /* Find the largest sample that is <= our frequency. */ 3278 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3279 lo = i; 3280 /* Find the smallest sample that is >= our frequency. */ 3281 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3282 hi = i; 3283 } 3284 if (lo == -1) 3285 lo = hi; 3286 else if (hi == -1) 3287 hi = lo; 3288 /* Interpolate values. */ 3289 for (i = 0; i < 4; i++) { 3290 tpow[i] = athn_interpolate(fbin, 3291 fbins[lo], tgt[lo].tPow2x[i], 3292 fbins[hi], tgt[hi].tPow2x[i]); 3293 } 3294 /* XXX Apply conformance test limit. */ 3295 } 3296 3297 PUBLIC void 3298 ar9003_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3299 uint8_t ctl, const uint8_t *fbins, 3300 const struct ar_cal_target_power_ht *tgt, int nchans, uint8_t tpow[14]) 3301 { 3302 uint8_t fbin; 3303 int i, delta, lo, hi; 3304 3305 lo = hi = -1; 3306 fbin = athn_chan2fbin(c); 3307 for (i = 0; i < nchans; i++) { 3308 delta = fbin - fbins[i]; 3309 /* Find the largest sample that is <= our frequency. */ 3310 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3311 lo = i; 3312 /* Find the smallest sample that is >= our frequency. */ 3313 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3314 hi = i; 3315 } 3316 if (lo == -1) 3317 lo = hi; 3318 else if (hi == -1) 3319 hi = lo; 3320 /* Interpolate values. */ 3321 for (i = 0; i < 14; i++) { 3322 tpow[i] = athn_interpolate(fbin, 3323 fbins[lo], tgt[lo].tPow2x[i], 3324 fbins[hi], tgt[hi].tPow2x[i]); 3325 } 3326 /* XXX Apply conformance test limit. */ 3327 } 3328 3329 /* 3330 * Adaptive noise immunity. 3331 */ 3332 Static void 3333 ar9003_set_noise_immunity_level(struct athn_softc *sc, int level) 3334 { 3335 int high = level == 4; 3336 uint32_t reg; 3337 3338 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 3339 reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55); 3340 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 3341 3342 reg = AR_READ(sc, AR_PHY_AGC); 3343 reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64); 3344 reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14); 3345 AR_WRITE(sc, AR_PHY_AGC, reg); 3346 3347 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3348 reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78); 3349 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3350 AR_WRITE_BARRIER(sc); 3351 } 3352 3353 Static void 3354 ar9003_enable_ofdm_weak_signal(struct athn_softc *sc) 3355 { 3356 uint32_t reg; 3357 3358 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3359 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50); 3360 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40); 3361 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48); 3362 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3363 3364 reg = AR_READ(sc, AR_PHY_SFCORR); 3365 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77); 3366 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64); 3367 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16); 3368 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3369 3370 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3371 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50); 3372 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40); 3373 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77); 3374 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64); 3375 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3376 3377 AR_SETBITS(sc, AR_PHY_SFCORR_LOW, 3378 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3379 AR_WRITE_BARRIER(sc); 3380 } 3381 3382 Static void 3383 ar9003_disable_ofdm_weak_signal(struct athn_softc *sc) 3384 { 3385 uint32_t reg; 3386 3387 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3388 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127); 3389 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127); 3390 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63); 3391 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3392 3393 reg = AR_READ(sc, AR_PHY_SFCORR); 3394 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127); 3395 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127); 3396 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31); 3397 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3398 3399 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3400 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127); 3401 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127); 3402 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127); 3403 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127); 3404 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3405 3406 AR_CLRBITS(sc, AR_PHY_SFCORR_LOW, 3407 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3408 AR_WRITE_BARRIER(sc); 3409 } 3410 3411 Static void 3412 ar9003_set_cck_weak_signal(struct athn_softc *sc, int high) 3413 { 3414 uint32_t reg; 3415 3416 reg = AR_READ(sc, AR_PHY_CCK_DETECT); 3417 reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8); 3418 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); 3419 AR_WRITE_BARRIER(sc); 3420 } 3421 3422 Static void 3423 ar9003_set_firstep_level(struct athn_softc *sc, int level) 3424 { 3425 uint32_t reg; 3426 3427 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3428 reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4); 3429 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3430 AR_WRITE_BARRIER(sc); 3431 } 3432 3433 Static void 3434 ar9003_set_spur_immunity_level(struct athn_softc *sc, int level) 3435 { 3436 uint32_t reg; 3437 3438 reg = AR_READ(sc, AR_PHY_TIMING5); 3439 reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2); 3440 AR_WRITE(sc, AR_PHY_TIMING5, reg); 3441 AR_WRITE_BARRIER(sc); 3442 } 3443
Indexes created Wed Oct 22 06:10:02 GMT 2025