arn9003.c revision 1.6.8.5
1 /* $NetBSD: arn9003.c,v 1.6.8.5 2017/08/28 17:52:03 skrll Exp $ */ 2 /* $OpenBSD: ar9003.c,v 1.25 2012/10/20 09:53:32 stsp Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 * Routines for AR9003 family. 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: arn9003.c,v 1.6.8.5 2017/08/28 17:52:03 skrll Exp $"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/queue.h> 37 #include <sys/callout.h> 38 #include <sys/conf.h> 39 #include <sys/device.h> 40 41 #include <sys/bus.h> 42 #include <sys/endian.h> 43 #include <sys/intr.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_ether.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/in_var.h> 56 #include <netinet/ip.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_amrr.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <dev/ic/athnreg.h> 63 #include <dev/ic/athnvar.h> 64 #include <dev/ic/arn9003reg.h> 65 #include <dev/ic/arn9003.h> 66 67 #define Static static 68 69 Static void ar9003_calib_iq(struct athn_softc *); 70 Static int ar9003_calib_tx_iq(struct athn_softc *); 71 Static int ar9003_compute_predistortion(struct athn_softc *, 72 const uint32_t *, const uint32_t *); 73 Static void ar9003_disable_ofdm_weak_signal(struct athn_softc *); 74 Static void ar9003_disable_phy(struct athn_softc *); 75 Static int ar9003_dma_alloc(struct athn_softc *); 76 Static void ar9003_dma_free(struct athn_softc *); 77 Static void ar9003_do_calib(struct athn_softc *); 78 Static void ar9003_do_noisefloor_calib(struct athn_softc *); 79 Static void ar9003_enable_antenna_diversity(struct athn_softc *); 80 Static void ar9003_enable_ofdm_weak_signal(struct athn_softc *); 81 Static void ar9003_enable_predistorter(struct athn_softc *, int); 82 Static int ar9003_find_rom(struct athn_softc *); 83 Static void ar9003_force_txgain(struct athn_softc *, uint32_t); 84 Static int ar9003_get_desired_txgain(struct athn_softc *, int, int); 85 Static int ar9003_get_iq_corr(struct athn_softc *, int32_t[], int32_t[]); 86 Static void ar9003_gpio_config_input(struct athn_softc *, int); 87 Static void ar9003_gpio_config_output(struct athn_softc *, int, int); 88 Static int ar9003_gpio_read(struct athn_softc *, int); 89 Static void ar9003_gpio_write(struct athn_softc *, int, int); 90 Static void ar9003_hw_init(struct athn_softc *, struct ieee80211_channel *, 91 struct ieee80211_channel *); 92 Static void ar9003_init_baseband(struct athn_softc *); 93 Static void ar9003_init_chains(struct athn_softc *); 94 Static int ar9003_intr_status(struct athn_softc *); 95 Static int ar9003_intr(struct athn_softc *); 96 Static void ar9003_next_calib(struct athn_softc *); 97 Static void ar9003_paprd_enable(struct athn_softc *); 98 Static int ar9003_paprd_tx_tone(struct athn_softc *); 99 Static void ar9003_paprd_tx_tone_done(struct athn_softc *); 100 Static int ar9003_read_eep_data(struct athn_softc *, uint32_t, void *, 101 int); 102 Static int ar9003_read_eep_word(struct athn_softc *, uint32_t, 103 uint16_t *); 104 Static int ar9003_read_otp_data(struct athn_softc *, uint32_t, void *, 105 int); 106 Static int ar9003_read_otp_word(struct athn_softc *, uint32_t, 107 uint32_t *); 108 Static int ar9003_read_rom(struct athn_softc *); 109 Static void ar9003_reset_rx_gain(struct athn_softc *, 110 struct ieee80211_channel *); 111 Static void ar9003_reset_tx_gain(struct athn_softc *, 112 struct ieee80211_channel *); 113 Static int ar9003_restore_rom_block(struct athn_softc *, uint8_t, 114 uint8_t, const uint8_t *, size_t); 115 Static void ar9003_rf_bus_release(struct athn_softc *); 116 Static int ar9003_rf_bus_request(struct athn_softc *); 117 Static void ar9003_rfsilent_init(struct athn_softc *); 118 Static int ar9003_rx_alloc(struct athn_softc *, int, int); 119 Static void ar9003_rx_enable(struct athn_softc *); 120 Static void ar9003_rx_free(struct athn_softc *, int); 121 Static void ar9003_rx_intr(struct athn_softc *, int); 122 Static int ar9003_rx_process(struct athn_softc *, int); 123 Static void ar9003_rx_radiotap(struct athn_softc *, struct mbuf *, 124 struct ar_rx_status *); 125 Static void ar9003_set_cck_weak_signal(struct athn_softc *, int); 126 Static void ar9003_set_delta_slope(struct athn_softc *, 127 struct ieee80211_channel *, struct ieee80211_channel *); 128 Static void ar9003_set_firstep_level(struct athn_softc *, int); 129 Static void ar9003_set_noise_immunity_level(struct athn_softc *, int); 130 Static void ar9003_set_phy(struct athn_softc *, struct ieee80211_channel *, 131 struct ieee80211_channel *); 132 Static void ar9003_set_rf_mode(struct athn_softc *, 133 struct ieee80211_channel *); 134 Static void ar9003_set_rxchains(struct athn_softc *); 135 Static void ar9003_set_spur_immunity_level(struct athn_softc *, int); 136 Static void ar9003_set_training_gain(struct athn_softc *, int); 137 Static int ar9003_swba_intr(struct athn_softc *); 138 Static int ar9003_tx(struct athn_softc *, struct mbuf *, 139 struct ieee80211_node *, int); 140 Static int ar9003_tx_alloc(struct athn_softc *); 141 Static void ar9003_tx_free(struct athn_softc *); 142 Static void ar9003_tx_intr(struct athn_softc *); 143 Static int ar9003_tx_process(struct athn_softc *); 144 145 #ifdef notused 146 Static void ar9003_bb_load_noisefloor(struct athn_softc *); 147 Static void ar9003_get_noisefloor(struct athn_softc *, 148 struct ieee80211_channel *); 149 Static void ar9003_paprd_calib(struct athn_softc *, 150 struct ieee80211_channel *); 151 Static void ar9003_read_noisefloor(struct athn_softc *, int16_t *, 152 int16_t *); 153 Static void ar9003_write_noisefloor(struct athn_softc *, int16_t *, 154 int16_t *); 155 Static void ar9300_noisefloor_calib(struct athn_softc *); 156 #endif /* notused */ 157 158 /* 159 * XXX: See if_iwn.c:MCLGETIalt() for a better solution. 160 * XXX: Put this in a header or in athn.c so it can be shared between 161 * ar5008.c and ar9003.c? 162 */ 163 static struct mbuf * 164 MCLGETI(struct athn_softc *sc __unused, int how, 165 struct ifnet *ifp __unused, u_int size) 166 { 167 struct mbuf *m; 168 169 MGETHDR(m, how, MT_DATA); 170 if (m == NULL) 171 return NULL; 172 173 MEXTMALLOC(m, size, how); 174 if ((m->m_flags & M_EXT) == 0) { 175 m_freem(m); 176 return NULL; 177 } 178 return m; 179 } 180 181 PUBLIC int 182 ar9003_attach(struct athn_softc *sc) 183 { 184 struct athn_ops *ops = &sc->sc_ops; 185 int error; 186 187 /* Set callbacks for AR9003 family. */ 188 ops->gpio_read = ar9003_gpio_read; 189 ops->gpio_write = ar9003_gpio_write; 190 ops->gpio_config_input = ar9003_gpio_config_input; 191 ops->gpio_config_output = ar9003_gpio_config_output; 192 ops->rfsilent_init = ar9003_rfsilent_init; 193 194 ops->dma_alloc = ar9003_dma_alloc; 195 ops->dma_free = ar9003_dma_free; 196 ops->rx_enable = ar9003_rx_enable; 197 ops->intr_status = ar9003_intr_status; 198 ops->intr = ar9003_intr; 199 ops->tx = ar9003_tx; 200 201 ops->set_rf_mode = ar9003_set_rf_mode; 202 ops->rf_bus_request = ar9003_rf_bus_request; 203 ops->rf_bus_release = ar9003_rf_bus_release; 204 ops->set_phy = ar9003_set_phy; 205 ops->set_delta_slope = ar9003_set_delta_slope; 206 ops->enable_antenna_diversity = ar9003_enable_antenna_diversity; 207 ops->init_baseband = ar9003_init_baseband; 208 ops->disable_phy = ar9003_disable_phy; 209 ops->set_rxchains = ar9003_set_rxchains; 210 ops->noisefloor_calib = ar9003_do_noisefloor_calib; 211 ops->do_calib = ar9003_do_calib; 212 ops->next_calib = ar9003_next_calib; 213 ops->hw_init = ar9003_hw_init; 214 215 ops->set_noise_immunity_level = ar9003_set_noise_immunity_level; 216 ops->enable_ofdm_weak_signal = ar9003_enable_ofdm_weak_signal; 217 ops->disable_ofdm_weak_signal = ar9003_disable_ofdm_weak_signal; 218 ops->set_cck_weak_signal = ar9003_set_cck_weak_signal; 219 ops->set_firstep_level = ar9003_set_firstep_level; 220 ops->set_spur_immunity_level = ar9003_set_spur_immunity_level; 221 222 /* Set MAC registers offsets. */ 223 sc->sc_obs_off = AR_OBS; 224 sc->sc_gpio_input_en_off = AR_GPIO_INPUT_EN_VAL; 225 226 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 227 athn_config_nonpcie(sc); 228 else 229 athn_config_pcie(sc); 230 231 /* Determine ROM type and location. */ 232 if ((error = ar9003_find_rom(sc)) != 0) { 233 aprint_error_dev(sc->sc_dev, "could not find ROM\n"); 234 return error; 235 } 236 /* Read entire ROM content in memory. */ 237 if ((error = ar9003_read_rom(sc)) != 0) { 238 aprint_error_dev(sc->sc_dev, "could not read ROM\n"); 239 return error; 240 } 241 242 /* Determine if it is a non-enterprise AR9003 card. */ 243 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_MPSD) 244 sc->sc_flags |= ATHN_FLAG_NON_ENTERPRISE; 245 246 ops->setup(sc); 247 return 0; 248 } 249 250 /* 251 * Read 16-bit word from EEPROM. 252 */ 253 Static int 254 ar9003_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val) 255 { 256 uint32_t reg; 257 int ntries; 258 259 reg = AR_READ(sc, AR_EEPROM_OFFSET(addr)); 260 for (ntries = 0; ntries < 1000; ntries++) { 261 reg = AR_READ(sc, AR_EEPROM_STATUS_DATA); 262 if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY | 263 AR_EEPROM_STATUS_DATA_PROT_ACCESS))) { 264 *val = MS(reg, AR_EEPROM_STATUS_DATA_VAL); 265 return 0; 266 } 267 DELAY(10); 268 } 269 *val = 0xffff; 270 return ETIMEDOUT; 271 } 272 273 /* 274 * Read an arbitrary number of bytes at a specified address in EEPROM. 275 * NB: The address may not be 16-bit aligned. 276 */ 277 Static int 278 ar9003_read_eep_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 279 { 280 uint8_t *dst = buf; 281 uint16_t val; 282 int error; 283 284 if (len > 0 && (addr & 1)) { 285 /* Deal with non-aligned reads. */ 286 addr >>= 1; 287 error = ar9003_read_eep_word(sc, addr, &val); 288 if (error != 0) 289 return error; 290 *dst++ = val & 0xff; 291 addr--; 292 len--; 293 } 294 else 295 addr >>= 1; 296 for (; len >= 2; addr--, len -= 2) { 297 error = ar9003_read_eep_word(sc, addr, &val); 298 if (error != 0) 299 return error; 300 *dst++ = val >> 8; 301 *dst++ = val & 0xff; 302 } 303 if (len > 0) { 304 error = ar9003_read_eep_word(sc, addr, &val); 305 if (error != 0) 306 return error; 307 *dst++ = val >> 8; 308 } 309 return 0; 310 } 311 312 /* 313 * Read 32-bit word from OTPROM. 314 */ 315 Static int 316 ar9003_read_otp_word(struct athn_softc *sc, uint32_t addr, uint32_t *val) 317 { 318 uint32_t reg; 319 int ntries; 320 321 reg = AR_READ(sc, AR_OTP_BASE(addr)); 322 for (ntries = 0; ntries < 1000; ntries++) { 323 reg = AR_READ(sc, AR_OTP_STATUS); 324 if (MS(reg, AR_OTP_STATUS_TYPE) == AR_OTP_STATUS_VALID) { 325 *val = AR_READ(sc, AR_OTP_READ_DATA); 326 return 0; 327 } 328 DELAY(10); 329 } 330 return ETIMEDOUT; 331 } 332 333 /* 334 * Read an arbitrary number of bytes at a specified address in OTPROM. 335 * NB: The address may not be 32-bit aligned. 336 */ 337 Static int 338 ar9003_read_otp_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 339 { 340 uint8_t *dst = buf; 341 uint32_t val; 342 int error; 343 344 /* NB: not optimal for non-aligned reads, but correct. */ 345 for (; len > 0; addr--, len--) { 346 error = ar9003_read_otp_word(sc, addr >> 2, &val); 347 if (error != 0) 348 return error; 349 *dst++ = (val >> ((addr & 3) * 8)) & 0xff; 350 } 351 return 0; 352 } 353 354 /* 355 * Determine if the chip has an external EEPROM or an OTPROM and its size. 356 */ 357 Static int 358 ar9003_find_rom(struct athn_softc *sc) 359 { 360 struct athn_ops *ops = &sc->sc_ops; 361 uint32_t hdr; 362 int error; 363 364 /* Try EEPROM. */ 365 ops->read_rom_data = ar9003_read_eep_data; 366 367 sc->sc_eep_size = AR_SREV_9485(sc) ? 4096 : 1024; 368 sc->sc_eep_base = sc->sc_eep_size - 1; 369 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 370 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 371 return 0; 372 373 sc->sc_eep_size = 512; 374 sc->sc_eep_base = sc->sc_eep_size - 1; 375 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 376 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 377 return 0; 378 379 /* Try OTPROM. */ 380 ops->read_rom_data = ar9003_read_otp_data; 381 382 sc->sc_eep_size = 1024; 383 sc->sc_eep_base = sc->sc_eep_size - 1; 384 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 385 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 386 return 0; 387 388 sc->sc_eep_size = 512; 389 sc->sc_eep_base = sc->sc_eep_size - 1; 390 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 391 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 392 return 0; 393 394 return EIO; /* Not found. */ 395 } 396 397 Static int 398 ar9003_restore_rom_block(struct athn_softc *sc, uint8_t alg, uint8_t ref, 399 const uint8_t *buf, size_t len) 400 { 401 const uint8_t *def, *ptr, *end; 402 uint8_t *eep = sc->sc_eep; 403 size_t off, clen; 404 405 if (alg == AR_EEP_COMPRESS_BLOCK) { 406 /* Block contains chunks that shadow ROM template. */ 407 def = sc->sc_ops.get_rom_template(sc, ref); 408 if (def == NULL) { 409 DPRINTFN(DBG_INIT, sc, "unknown template image %d\n", 410 ref); 411 return EINVAL; 412 } 413 /* Start with template. */ 414 memcpy(eep, def, sc->sc_eep_size); 415 /* Shadow template with chunks. */ 416 off = 0; /* Offset in ROM image. */ 417 ptr = buf; /* Offset in block. */ 418 end = buf + len; 419 /* Process chunks. */ 420 while (ptr + 2 <= end) { 421 off += *ptr++; /* Gap with previous chunk. */ 422 clen = *ptr++; /* Chunk length. */ 423 /* Make sure block is large enough. */ 424 if (ptr + clen > end) 425 return EINVAL; 426 /* Make sure chunk fits in ROM image. */ 427 if (off + clen > sc->sc_eep_size) 428 return EINVAL; 429 /* Restore chunk. */ 430 DPRINTFN(DBG_INIT, sc, "ROM chunk @%zd/%zd\n", 431 off, clen); 432 memcpy(&eep[off], ptr, clen); 433 ptr += clen; 434 off += clen; 435 } 436 } 437 else if (alg == AR_EEP_COMPRESS_NONE) { 438 /* Block contains full ROM image. */ 439 if (len != sc->sc_eep_size) { 440 DPRINTFN(DBG_INIT, sc, "block length mismatch %zd\n", 441 len); 442 return EINVAL; 443 } 444 memcpy(eep, buf, len); 445 } 446 return 0; 447 } 448 449 Static int 450 ar9003_read_rom(struct athn_softc *sc) 451 { 452 struct athn_ops *ops = &sc->sc_ops; 453 uint8_t *buf, *ptr, alg, ref; 454 uint16_t sum, rsum; 455 uint32_t hdr; 456 int error, addr; 457 size_t len, i, j; 458 459 /* Allocate space to store ROM in host memory. */ 460 sc->sc_eep = malloc(sc->sc_eep_size, M_DEVBUF, M_NOWAIT); 461 if (sc->sc_eep == NULL) 462 return ENOMEM; 463 464 /* Allocate temporary buffer to store ROM blocks. */ 465 buf = malloc(2048, M_DEVBUF, M_NOWAIT); 466 if (buf == NULL) 467 return ENOMEM; 468 469 /* Restore vendor-specified ROM blocks. */ 470 addr = sc->sc_eep_base; 471 for (i = 0; i < 100; i++) { 472 /* Read block header. */ 473 error = ops->read_rom_data(sc, addr, &hdr, sizeof(hdr)); 474 if (error != 0) 475 break; 476 if (hdr == 0 || hdr == 0xffffffff) 477 break; 478 addr -= sizeof(hdr); 479 480 /* Extract bits from header. */ 481 ptr = (uint8_t *)&hdr; 482 alg = (ptr[0] & 0xe0) >> 5; 483 ref = (ptr[1] & 0x80) >> 2 | (ptr[0] & 0x1f); 484 len = (ptr[1] & 0x7f) << 4 | (ptr[2] & 0xf0) >> 4; 485 DPRINTFN(DBG_INIT, sc, 486 "ROM block %zd: alg=%d ref=%d len=%zd\n", 487 i, alg, ref, len); 488 489 /* Read block data (len <= 0x7ff). */ 490 error = ops->read_rom_data(sc, addr, buf, len); 491 if (error != 0) 492 break; 493 addr -= len; 494 495 /* Read block checksum. */ 496 error = ops->read_rom_data(sc, addr, &sum, sizeof(sum)); 497 if (error != 0) 498 break; 499 addr -= sizeof(sum); 500 501 /* Compute block checksum. */ 502 rsum = 0; 503 for (j = 0; j < len; j++) 504 rsum += buf[j]; 505 /* Compare to that in ROM. */ 506 if (le16toh(sum) != rsum) { 507 DPRINTFN(DBG_INIT, sc, 508 "bad block checksum 0x%x/0x%x\n", 509 le16toh(sum), rsum); 510 continue; /* Skip bad block. */ 511 } 512 /* Checksum is correct, restore block. */ 513 ar9003_restore_rom_block(sc, alg, ref, buf, len); 514 } 515 #if BYTE_ORDER == BIG_ENDIAN 516 /* NB: ROM is always little endian. */ 517 if (error == 0) 518 ops->swap_rom(sc); 519 #endif 520 free(buf, M_DEVBUF); 521 return error; 522 } 523 524 /* 525 * Access to General Purpose Input/Output ports. 526 */ 527 Static int 528 ar9003_gpio_read(struct athn_softc *sc, int pin) 529 { 530 531 KASSERT(pin < sc->sc_ngpiopins); 532 return ((AR_READ(sc, AR_GPIO_IN) & AR9300_GPIO_IN_VAL) & 533 (1 << pin)) != 0; 534 } 535 536 Static void 537 ar9003_gpio_write(struct athn_softc *sc, int pin, int set) 538 { 539 uint32_t reg; 540 541 KASSERT(pin < sc->sc_ngpiopins); 542 reg = AR_READ(sc, AR_GPIO_IN_OUT); 543 if (set) 544 reg |= 1 << pin; 545 else 546 reg &= ~(1 << pin); 547 AR_WRITE(sc, AR_GPIO_IN_OUT, reg); 548 AR_WRITE_BARRIER(sc); 549 } 550 551 Static void 552 ar9003_gpio_config_input(struct athn_softc *sc, int pin) 553 { 554 uint32_t reg; 555 556 reg = AR_READ(sc, AR_GPIO_OE_OUT); 557 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 558 reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2); 559 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 560 AR_WRITE_BARRIER(sc); 561 } 562 563 Static void 564 ar9003_gpio_config_output(struct athn_softc *sc, int pin, int type) 565 { 566 uint32_t reg; 567 int mux, off; 568 569 mux = pin / 6; 570 off = pin % 6; 571 572 reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux)); 573 reg &= ~(0x1f << (off * 5)); 574 reg |= (type & 0x1f) << (off * 5); 575 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg); 576 577 reg = AR_READ(sc, AR_GPIO_OE_OUT); 578 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 579 reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2); 580 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 581 AR_WRITE_BARRIER(sc); 582 } 583 584 Static void 585 ar9003_rfsilent_init(struct athn_softc *sc) 586 { 587 uint32_t reg; 588 589 /* Configure hardware radio switch. */ 590 AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 591 reg = AR_READ(sc, AR_GPIO_INPUT_MUX2); 592 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); 593 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg); 594 ar9003_gpio_config_input(sc, sc->sc_rfsilent_pin); 595 AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB); 596 if (!(sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED)) { 597 AR_SETBITS(sc, AR_GPIO_INTR_POL, 598 AR_GPIO_INTR_POL_PIN(sc->sc_rfsilent_pin)); 599 } 600 AR_WRITE_BARRIER(sc); 601 } 602 603 Static int 604 ar9003_dma_alloc(struct athn_softc *sc) 605 { 606 int error; 607 608 error = ar9003_tx_alloc(sc); 609 if (error != 0) 610 return error; 611 612 error = ar9003_rx_alloc(sc, ATHN_QID_LP, AR9003_RX_LP_QDEPTH); 613 if (error != 0) 614 return error; 615 616 error = ar9003_rx_alloc(sc, ATHN_QID_HP, AR9003_RX_HP_QDEPTH); 617 if (error != 0) 618 return error; 619 620 return 0; 621 } 622 623 Static void 624 ar9003_dma_free(struct athn_softc *sc) 625 { 626 627 ar9003_tx_free(sc); 628 ar9003_rx_free(sc, ATHN_QID_LP); 629 ar9003_rx_free(sc, ATHN_QID_HP); 630 } 631 632 Static int 633 ar9003_tx_alloc(struct athn_softc *sc) 634 { 635 struct athn_tx_buf *bf; 636 bus_size_t size; 637 int error, nsegs, i; 638 639 /* 640 * Allocate Tx status ring. 641 */ 642 size = AR9003_NTXSTATUS * sizeof(struct ar_tx_status); 643 644 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 645 BUS_DMA_NOWAIT, &sc->sc_txsmap); 646 if (error != 0) 647 goto fail; 648 649 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_txsseg, 1, 650 // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 651 &nsegs, BUS_DMA_NOWAIT); 652 if (error != 0) 653 goto fail; 654 655 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_txsseg, 1, size, 656 (void **)&sc->sc_txsring, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 657 if (error != 0) 658 goto fail; 659 660 error = bus_dmamap_load(sc->sc_dmat, sc->sc_txsmap, sc->sc_txsring, 661 size, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 662 if (error != 0) 663 goto fail; 664 665 /* 666 * Allocate a pool of Tx descriptors shared between all Tx queues. 667 */ 668 size = ATHN_NTXBUFS * sizeof(struct ar_tx_desc); 669 670 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 671 BUS_DMA_NOWAIT, &sc->sc_map); 672 if (error != 0) 673 goto fail; 674 675 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_seg, 1, 676 // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 677 &nsegs, BUS_DMA_NOWAIT); 678 if (error != 0) 679 goto fail; 680 681 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, 1, size, 682 (void **)&sc->sc_descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 683 if (error != 0) 684 goto fail; 685 686 error = bus_dmamap_load(sc->sc_dmat, sc->sc_map, sc->sc_descs, size, 687 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 688 if (error != 0) 689 goto fail; 690 691 SIMPLEQ_INIT(&sc->sc_txbufs); 692 for (i = 0; i < ATHN_NTXBUFS; i++) { 693 bf = &sc->sc_txpool[i]; 694 695 error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ, 696 AR9003_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT, 697 &bf->bf_map); 698 if (error != 0) { 699 aprint_error_dev(sc->sc_dev, 700 "could not create Tx buf DMA map\n"); 701 goto fail; 702 } 703 704 bf->bf_descs = &((struct ar_tx_desc *)sc->sc_descs)[i]; 705 bf->bf_daddr = sc->sc_map->dm_segs[0].ds_addr + 706 i * sizeof(struct ar_tx_desc); 707 708 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 709 } 710 return 0; 711 fail: 712 ar9003_tx_free(sc); 713 return error; 714 } 715 716 Static void 717 ar9003_tx_free(struct athn_softc *sc) 718 { 719 struct athn_tx_buf *bf; 720 int i; 721 722 for (i = 0; i < ATHN_NTXBUFS; i++) { 723 bf = &sc->sc_txpool[i]; 724 725 if (bf->bf_map != NULL) 726 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 727 } 728 /* Free Tx descriptors. */ 729 if (sc->sc_map != NULL) { 730 if (sc->sc_descs != NULL) { 731 bus_dmamap_unload(sc->sc_dmat, sc->sc_map); 732 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 733 ATHN_NTXBUFS * sizeof(struct ar_tx_desc)); 734 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 735 } 736 bus_dmamap_destroy(sc->sc_dmat, sc->sc_map); 737 } 738 /* Free Tx status ring. */ 739 if (sc->sc_txsmap != NULL) { 740 if (sc->sc_txsring != NULL) { 741 bus_dmamap_unload(sc->sc_dmat, sc->sc_txsmap); 742 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_txsring, 743 AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 744 bus_dmamem_free(sc->sc_dmat, &sc->sc_txsseg, 1); 745 } 746 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsmap); 747 } 748 } 749 750 Static int 751 ar9003_rx_alloc(struct athn_softc *sc, int qid, int count) 752 { 753 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 754 struct athn_rx_buf *bf; 755 struct ar_rx_status *ds; 756 int error, i; 757 758 rxq->bf = malloc(count * sizeof(*bf), M_DEVBUF, M_NOWAIT | M_ZERO); 759 if (rxq->bf == NULL) 760 return ENOMEM; 761 762 rxq->count = count; 763 764 for (i = 0; i < rxq->count; i++) { 765 bf = &rxq->bf[i]; 766 767 error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1, 768 ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 769 &bf->bf_map); 770 if (error != 0) { 771 aprint_error_dev(sc->sc_dev, 772 "could not create Rx buf DMA map\n"); 773 goto fail; 774 } 775 /* 776 * Assumes MCLGETI returns cache-line-size aligned buffers. 777 */ 778 bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 779 if (bf->bf_m == NULL) { 780 aprint_error_dev(sc->sc_dev, 781 "could not allocate Rx mbuf\n"); 782 error = ENOBUFS; 783 goto fail; 784 } 785 786 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 787 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 788 BUS_DMA_NOWAIT); 789 if (error != 0) { 790 aprint_error_dev(sc->sc_dev, 791 "could not DMA map Rx buffer\n"); 792 goto fail; 793 } 794 795 ds = mtod(bf->bf_m, struct ar_rx_status *); 796 memset(ds, 0, sizeof(*ds)); 797 bf->bf_desc = ds; 798 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 799 800 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 801 BUS_DMASYNC_PREREAD); 802 } 803 return 0; 804 fail: 805 ar9003_rx_free(sc, qid); 806 return error; 807 } 808 809 Static void 810 ar9003_rx_free(struct athn_softc *sc, int qid) 811 { 812 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 813 struct athn_rx_buf *bf; 814 int i; 815 816 if (rxq->bf == NULL) 817 return; 818 for (i = 0; i < rxq->count; i++) { 819 bf = &rxq->bf[i]; 820 821 if (bf->bf_map != NULL) 822 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 823 if (bf->bf_m != NULL) 824 m_freem(bf->bf_m); 825 } 826 free(rxq->bf, M_DEVBUF); 827 } 828 829 PUBLIC void 830 ar9003_reset_txsring(struct athn_softc *sc) 831 { 832 833 sc->sc_txscur = 0; 834 memset(sc->sc_txsring, 0, AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 835 AR_WRITE(sc, AR_Q_STATUS_RING_START, 836 sc->sc_txsmap->dm_segs[0].ds_addr); 837 AR_WRITE(sc, AR_Q_STATUS_RING_END, 838 sc->sc_txsmap->dm_segs[0].ds_addr + sc->sc_txsmap->dm_segs[0].ds_len); 839 AR_WRITE_BARRIER(sc); 840 } 841 842 Static void 843 ar9003_rx_enable(struct athn_softc *sc) 844 { 845 struct athn_rxq *rxq; 846 struct athn_rx_buf *bf; 847 struct ar_rx_status *ds; 848 uint32_t reg; 849 int qid, i; 850 851 reg = AR_READ(sc, AR_RXBP_THRESH); 852 reg = RW(reg, AR_RXBP_THRESH_HP, 1); 853 reg = RW(reg, AR_RXBP_THRESH_LP, 1); 854 AR_WRITE(sc, AR_RXBP_THRESH, reg); 855 856 /* Set Rx buffer size. */ 857 AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds)); 858 859 for (qid = 0; qid < 2; qid++) { 860 rxq = &sc->sc_rxq[qid]; 861 862 /* Setup Rx status descriptors. */ 863 SIMPLEQ_INIT(&rxq->head); 864 for (i = 0; i < rxq->count; i++) { 865 bf = &rxq->bf[i]; 866 ds = bf->bf_desc; 867 868 memset(ds, 0, sizeof(*ds)); 869 if (qid == ATHN_QID_LP) 870 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 871 else 872 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 873 AR_WRITE_BARRIER(sc); 874 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 875 } 876 } 877 /* Enable Rx. */ 878 AR_WRITE(sc, AR_CR, 0); 879 AR_WRITE_BARRIER(sc); 880 } 881 882 Static void 883 ar9003_rx_radiotap(struct athn_softc *sc, struct mbuf *m, 884 struct ar_rx_status *ds) 885 { 886 struct athn_rx_radiotap_header *tap = &sc->sc_rxtap; 887 struct ieee80211com *ic = &sc->sc_ic; 888 uint64_t tsf; 889 uint32_t tstamp; 890 uint8_t rate; 891 892 /* Extend the 15-bit timestamp from Rx status to 64-bit TSF. */ 893 tstamp = ds->ds_status3; 894 tsf = AR_READ(sc, AR_TSF_U32); 895 tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32); 896 if ((tsf & 0x7fff) < tstamp) 897 tsf -= 0x8000; 898 tsf = (tsf & ~0x7fff) | tstamp; 899 900 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 901 tap->wr_tsft = htole64(tsf); 902 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 903 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 904 tap->wr_dbm_antsignal = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 905 /* XXX noise. */ 906 tap->wr_antenna = MS(ds->ds_status4, AR_RXS4_ANTENNA); 907 tap->wr_rate = 0; /* In case it can't be found below. */ 908 rate = MS(ds->ds_status1, AR_RXS1_RATE); 909 if (rate & 0x80) { /* HT. */ 910 /* Bit 7 set means HT MCS instead of rate. */ 911 tap->wr_rate = rate; 912 if (!(ds->ds_status4 & AR_RXS4_GI)) 913 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 914 915 } 916 else if (rate & 0x10) { /* CCK. */ 917 if (rate & 0x04) 918 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 919 switch (rate & ~0x14) { 920 case 0xb: tap->wr_rate = 2; break; 921 case 0xa: tap->wr_rate = 4; break; 922 case 0x9: tap->wr_rate = 11; break; 923 case 0x8: tap->wr_rate = 22; break; 924 } 925 } 926 else { /* OFDM. */ 927 switch (rate) { 928 case 0xb: tap->wr_rate = 12; break; 929 case 0xf: tap->wr_rate = 18; break; 930 case 0xa: tap->wr_rate = 24; break; 931 case 0xe: tap->wr_rate = 36; break; 932 case 0x9: tap->wr_rate = 48; break; 933 case 0xd: tap->wr_rate = 72; break; 934 case 0x8: tap->wr_rate = 96; break; 935 case 0xc: tap->wr_rate = 108; break; 936 } 937 } 938 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 939 } 940 941 Static int 942 ar9003_rx_process(struct athn_softc *sc, int qid) 943 { 944 struct ieee80211com *ic = &sc->sc_ic; 945 struct ifnet *ifp = &sc->sc_if; 946 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 947 struct athn_rx_buf *bf; 948 struct ar_rx_status *ds; 949 struct ieee80211_frame *wh; 950 struct ieee80211_node *ni; 951 struct mbuf *m, *m1; 952 size_t len; 953 u_int32_t rstamp; 954 int error, rssi, s; 955 956 bf = SIMPLEQ_FIRST(&rxq->head); 957 if (__predict_false(bf == NULL)) { /* Should not happen. */ 958 aprint_error_dev(sc->sc_dev, "Rx queue is empty!\n"); 959 return ENOENT; 960 } 961 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 962 BUS_DMASYNC_POSTREAD); 963 964 ds = mtod(bf->bf_m, struct ar_rx_status *); 965 if (!(ds->ds_status1 & AR_RXS1_DONE)) 966 return EBUSY; 967 968 /* Check that it is a valid Rx status descriptor. */ 969 if ((ds->ds_info & (AR_RXI_DESC_ID_M | AR_RXI_DESC_TX | 970 AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS)) 971 goto skip; 972 973 if (!(ds->ds_status11 & AR_RXS11_FRAME_OK)) { 974 if (ds->ds_status11 & AR_RXS11_CRC_ERR) 975 DPRINTFN(DBG_RX, sc, "CRC error\n"); 976 else if (ds->ds_status11 & AR_RXS11_PHY_ERR) 977 DPRINTFN(DBG_RX, sc, "PHY error=0x%x\n", 978 MS(ds->ds_status11, AR_RXS11_PHY_ERR_CODE)); 979 else if (ds->ds_status11 & AR_RXS11_DECRYPT_CRC_ERR) 980 DPRINTFN(DBG_RX, sc, "Decryption CRC error\n"); 981 else if (ds->ds_status11 & AR_RXS11_MICHAEL_ERR) { 982 DPRINTFN(DBG_RX, sc, "Michael MIC failure\n"); 983 /* Report Michael MIC failures to net80211. */ 984 985 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 986 m = bf->bf_m; 987 m_set_rcvif(m, ifp); 988 m->m_data = (void *)&ds[1]; 989 m->m_pkthdr.len = m->m_len = len; 990 wh = mtod(m, struct ieee80211_frame *); 991 992 ieee80211_notify_michael_failure(ic, wh, 993 0 /* XXX: keyix */); 994 } 995 ifp->if_ierrors++; 996 goto skip; 997 } 998 999 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 1000 if (__predict_false(len < IEEE80211_MIN_LEN || 1001 len > ATHN_RXBUFSZ - sizeof(*ds))) { 1002 DPRINTFN(DBG_RX, sc, "corrupted descriptor length=%zd\n", 1003 len); 1004 ifp->if_ierrors++; 1005 goto skip; 1006 } 1007 1008 /* Allocate a new Rx buffer. */ 1009 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 1010 if (__predict_false(m1 == NULL)) { 1011 ic->ic_stats.is_rx_nobuf++; 1012 ifp->if_ierrors++; 1013 goto skip; 1014 } 1015 1016 /* Unmap the old Rx buffer. */ 1017 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1018 1019 /* Map the new Rx buffer. */ 1020 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *), 1021 ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1022 if (__predict_false(error != 0)) { 1023 m_freem(m1); 1024 1025 /* Remap the old Rx buffer or panic. */ 1026 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 1027 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 1028 BUS_DMA_NOWAIT | BUS_DMA_READ); 1029 KASSERT(error != 0); 1030 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1031 ifp->if_ierrors++; 1032 goto skip; 1033 } 1034 bf->bf_desc = mtod(m1, struct ar_rx_status *); 1035 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1036 1037 m = bf->bf_m; 1038 bf->bf_m = m1; 1039 1040 /* Finalize mbuf. */ 1041 m_set_rcvif(m, ifp); 1042 /* Strip Rx status descriptor from head. */ 1043 m->m_data = (void *)&ds[1]; 1044 m->m_pkthdr.len = m->m_len = len; 1045 1046 s = splnet(); 1047 1048 /* Grab a reference to the source node. */ 1049 wh = mtod(m, struct ieee80211_frame *); 1050 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1051 1052 /* Remove any HW padding after the 802.11 header. */ 1053 if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) { 1054 u_int hdrlen = ieee80211_anyhdrsize(wh); 1055 if (hdrlen & 3) { 1056 ovbcopy(wh, (uint8_t *)wh + 2, hdrlen); 1057 m_adj(m, 2); 1058 } 1059 } 1060 if (__predict_false(sc->sc_drvbpf != NULL)) 1061 ar9003_rx_radiotap(sc, m, ds); 1062 /* Trim 802.11 FCS after radiotap. */ 1063 m_adj(m, -IEEE80211_CRC_LEN); 1064 1065 /* Send the frame to the 802.11 layer. */ 1066 rssi = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 1067 rstamp = ds->ds_status3; 1068 ieee80211_input(ic, m, ni, rssi, rstamp); 1069 1070 /* Node is no longer needed. */ 1071 ieee80211_free_node(ni); 1072 1073 splx(s); 1074 1075 skip: 1076 /* Unlink this descriptor from head. */ 1077 SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list); 1078 memset(bf->bf_desc, 0, sizeof(*ds)); 1079 1080 /* Re-use this descriptor and link it to tail. */ 1081 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 1082 BUS_DMASYNC_PREREAD); 1083 1084 if (qid == ATHN_QID_LP) 1085 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 1086 else 1087 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 1088 AR_WRITE_BARRIER(sc); 1089 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 1090 1091 /* Re-enable Rx. */ 1092 AR_WRITE(sc, AR_CR, 0); 1093 AR_WRITE_BARRIER(sc); 1094 return 0; 1095 } 1096 1097 Static void 1098 ar9003_rx_intr(struct athn_softc *sc, int qid) 1099 { 1100 1101 while (ar9003_rx_process(sc, qid) == 0) 1102 continue; 1103 } 1104 1105 Static int 1106 ar9003_tx_process(struct athn_softc *sc) 1107 { 1108 struct ifnet *ifp = &sc->sc_if; 1109 struct athn_txq *txq; 1110 struct athn_node *an; 1111 struct athn_tx_buf *bf; 1112 struct ar_tx_status *ds; 1113 uint8_t qid, failcnt; 1114 1115 ds = &((struct ar_tx_status *)sc->sc_txsring)[sc->sc_txscur]; 1116 if (!(ds->ds_status8 & AR_TXS8_DONE)) 1117 return EBUSY; 1118 1119 sc->sc_txscur = (sc->sc_txscur + 1) % AR9003_NTXSTATUS; 1120 1121 /* Check that it is a valid Tx status descriptor. */ 1122 if ((ds->ds_info & (AR_TXI_DESC_ID_M | AR_TXI_DESC_TX)) != 1123 (SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX)) { 1124 memset(ds, 0, sizeof(*ds)); 1125 return 0; 1126 } 1127 /* Retrieve the queue that was used to send this PDU. */ 1128 qid = MS(ds->ds_info, AR_TXI_QCU_NUM); 1129 txq = &sc->sc_txq[qid]; 1130 1131 bf = SIMPLEQ_FIRST(&txq->head); 1132 if (bf == NULL || bf == txq->wait) { 1133 memset(ds, 0, sizeof(*ds)); 1134 return 0; 1135 } 1136 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1137 ifp->if_opackets++; 1138 1139 sc->sc_tx_timer = 0; 1140 1141 if (ds->ds_status3 & AR_TXS3_EXCESSIVE_RETRIES) 1142 ifp->if_oerrors++; 1143 1144 if (ds->ds_status3 & AR_TXS3_UNDERRUN) 1145 athn_inc_tx_trigger_level(sc); 1146 1147 /* Wakeup PA predistortion state machine. */ 1148 if (bf->bf_txflags & ATHN_TXFLAG_PAPRD) 1149 ar9003_paprd_tx_tone_done(sc); 1150 1151 an = (struct athn_node *)bf->bf_ni; 1152 /* 1153 * NB: the data fail count contains the number of un-acked tries 1154 * for the final series used. We must add the number of tries for 1155 * each series that was fully processed. 1156 */ 1157 failcnt = MS(ds->ds_status3, AR_TXS3_DATA_FAIL_CNT); 1158 /* NB: Assume two tries per series. */ 1159 failcnt += MS(ds->ds_status8, AR_TXS8_FINAL_IDX) * 2; 1160 1161 /* Update rate control statistics. */ 1162 an->amn.amn_txcnt++; 1163 if (failcnt > 0) 1164 an->amn.amn_retrycnt++; 1165 1166 DPRINTFN(DBG_TX, sc, "Tx done qid=%d status3=%d fail count=%d\n", 1167 qid, ds->ds_status3, failcnt); 1168 1169 /* Reset Tx status descriptor. */ 1170 memset(ds, 0, sizeof(*ds)); 1171 1172 /* Unmap Tx buffer. */ 1173 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1174 BUS_DMASYNC_POSTWRITE); 1175 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1176 1177 m_freem(bf->bf_m); 1178 bf->bf_m = NULL; 1179 ieee80211_free_node(bf->bf_ni); 1180 bf->bf_ni = NULL; 1181 1182 /* Link Tx buffer back to global free list. */ 1183 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1184 1185 /* Queue buffers that are waiting if there is new room. */ 1186 if (--txq->queued < AR9003_TX_QDEPTH && txq->wait != NULL) { 1187 AR_WRITE(sc, AR_QTXDP(qid), txq->wait->bf_daddr); 1188 AR_WRITE_BARRIER(sc); 1189 txq->wait = SIMPLEQ_NEXT(txq->wait, bf_list); 1190 } 1191 return 0; 1192 } 1193 1194 Static void 1195 ar9003_tx_intr(struct athn_softc *sc) 1196 { 1197 struct ifnet *ifp = &sc->sc_if; 1198 int s; 1199 1200 s = splnet(); 1201 1202 while (ar9003_tx_process(sc) == 0) 1203 continue; 1204 1205 if (!SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 1206 ifp->if_flags &= ~IFF_OACTIVE; 1207 ifp->if_start(ifp); /* in softint */ 1208 } 1209 1210 splx(s); 1211 } 1212 1213 #ifndef IEEE80211_STA_ONLY 1214 /* 1215 * Process Software Beacon Alert interrupts. 1216 */ 1217 Static int 1218 ar9003_swba_intr(struct athn_softc *sc) 1219 { 1220 struct ieee80211com *ic = &sc->sc_ic; 1221 struct ifnet *ifp = &sc->sc_if; 1222 struct ieee80211_node *ni = ic->ic_bss; 1223 struct athn_tx_buf *bf = sc->sc_bcnbuf; 1224 struct ieee80211_frame *wh; 1225 struct ieee80211_beacon_offsets bo; 1226 struct ar_tx_desc *ds; 1227 struct mbuf *m; 1228 uint32_t sum; 1229 uint8_t ridx, hwrate; 1230 int error, totlen; 1231 1232 #if notyet 1233 if (ic->ic_tim_mcast_pending && 1234 IF_IS_EMPTY(&ni->ni_savedq) && 1235 SIMPLEQ_EMPTY(&sc->sc_txq[ATHN_QID_CAB].head)) 1236 ic->ic_tim_mcast_pending = 0; 1237 #endif 1238 if (ic->ic_dtim_count == 0) 1239 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1240 else 1241 ic->ic_dtim_count--; 1242 1243 /* Make sure previous beacon has been sent. */ 1244 if (athn_tx_pending(sc, ATHN_QID_BEACON)) { 1245 DPRINTFN(DBG_INTR, sc, "beacon stuck\n"); 1246 return EBUSY; 1247 } 1248 /* Get new beacon. */ 1249 m = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 1250 if (__predict_false(m == NULL)) 1251 return ENOBUFS; 1252 /* Assign sequence number. */ 1253 /* XXX: use non-QoS tid? */ 1254 wh = mtod(m, struct ieee80211_frame *); 1255 *(uint16_t *)&wh->i_seq[0] = 1256 htole16(ic->ic_bss->ni_txseqs[0] << IEEE80211_SEQ_SEQ_SHIFT); 1257 ic->ic_bss->ni_txseqs[0]++; 1258 1259 /* Unmap and free old beacon if any. */ 1260 if (__predict_true(bf->bf_m != NULL)) { 1261 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1262 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1263 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1264 m_freem(bf->bf_m); 1265 bf->bf_m = NULL; 1266 } 1267 /* DMA map new beacon. */ 1268 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1269 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1270 if (__predict_false(error != 0)) { 1271 m_freem(m); 1272 return error; 1273 } 1274 bf->bf_m = m; 1275 1276 /* Setup Tx descriptor (simplified ar9003_tx()). */ 1277 ds = bf->bf_descs; 1278 memset(ds, 0, sizeof(*ds)); 1279 1280 ds->ds_info = 1281 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1282 SM(AR_TXI_DESC_NDWORDS, 23) | 1283 SM(AR_TXI_QCU_NUM, ATHN_QID_BEACON) | 1284 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1285 1286 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1287 ds->ds_ctl11 = SM(AR_TXC11_FRAME_LEN, totlen); 1288 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, AR_MAX_RATE_POWER); 1289 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, AR_FRAME_TYPE_BEACON); 1290 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1291 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, AR_ENCR_TYPE_CLEAR); 1292 1293 /* Write number of tries. */ 1294 ds->ds_ctl13 = SM(AR_TXC13_XMIT_DATA_TRIES0, 1); 1295 1296 /* Write Tx rate. */ 1297 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1298 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1299 hwrate = athn_rates[ridx].hwrate; 1300 ds->ds_ctl14 = SM(AR_TXC14_XMIT_RATE0, hwrate); 1301 1302 /* Write Tx chains. */ 1303 ds->ds_ctl18 = SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask); 1304 1305 ds->ds_segs[0].ds_data = bf->bf_map->dm_segs[0].ds_addr; 1306 /* Segment length must be a multiple of 4. */ 1307 ds->ds_segs[0].ds_ctl |= SM(AR_TXC_BUF_LEN, 1308 (bf->bf_map->dm_segs[0].ds_len + 3) & ~3); 1309 /* Compute Tx descriptor checksum. */ 1310 sum = ds->ds_info; 1311 sum += ds->ds_segs[0].ds_data; 1312 sum += ds->ds_segs[0].ds_ctl; 1313 sum = (sum >> 16) + (sum & 0xffff); 1314 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1315 1316 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1317 BUS_DMASYNC_PREWRITE); 1318 1319 /* Stop Tx DMA before putting the new beacon on the queue. */ 1320 athn_stop_tx_dma(sc, ATHN_QID_BEACON); 1321 1322 AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr); 1323 1324 for(;;) { 1325 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) 1326 break; 1327 1328 IF_DEQUEUE(&ni->ni_savedq, m); 1329 if (m == NULL) 1330 break; 1331 if (!IF_IS_EMPTY(&ni->ni_savedq)) { 1332 /* more queued frames, set the more data bit */ 1333 wh = mtod(m, struct ieee80211_frame *); 1334 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 1335 } 1336 1337 if (sc->sc_ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) { 1338 ieee80211_free_node(ni); 1339 ifp->if_oerrors++; 1340 break; 1341 } 1342 } 1343 1344 /* Kick Tx. */ 1345 AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON); 1346 AR_WRITE_BARRIER(sc); 1347 return 0; 1348 } 1349 #endif 1350 1351 static int 1352 ar9003_get_intr_status(struct athn_softc *sc, uint32_t *intrp, uint32_t *syncp) 1353 { 1354 uint32_t intr, sync; 1355 1356 /* Get pending interrupts. */ 1357 intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE); 1358 if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) { 1359 intr = AR_READ(sc, AR_INTR_SYNC_CAUSE); 1360 if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0) 1361 return 0; /* Not for us. */ 1362 } 1363 1364 if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 1365 (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 1366 intr = AR_READ(sc, AR_ISR); 1367 else 1368 intr = 0; 1369 sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync; 1370 if (intr == 0 && sync == 0) 1371 return 0; /* Not for us. */ 1372 1373 *intrp = intr; 1374 *syncp = sync; 1375 return 1; 1376 } 1377 1378 Static int 1379 ar9003_intr_status(struct athn_softc *sc) 1380 { 1381 uint32_t intr, sync; 1382 1383 return ar9003_get_intr_status(sc, &intr, &sync); 1384 } 1385 1386 Static int 1387 ar9003_intr(struct athn_softc *sc) 1388 { 1389 uint32_t intr, sync; 1390 #ifndef IEEE80211_STA_ONLY 1391 int s; 1392 #endif 1393 1394 if (!ar9003_get_intr_status(sc, &intr, &sync)) 1395 return 0; 1396 1397 if (intr != 0) { 1398 if (intr & AR_ISR_BCNMISC) { 1399 uint32_t intr2 = AR_READ(sc, AR_ISR_S2); 1400 #ifdef notyet 1401 if (intr2 & AR_ISR_S2_TIM) 1402 /* TBD */; 1403 if (intr2 & AR_ISR_S2_TSFOOR) 1404 /* TBD */; 1405 if (intr2 & AR_ISR_S2_BB_WATCHDOG) 1406 /* TBD */; 1407 #else 1408 __USE(intr2); 1409 #endif 1410 } 1411 intr = AR_READ(sc, AR_ISR_RAC); 1412 if (intr == AR_INTR_SPURIOUS) 1413 return 1; 1414 1415 #ifndef IEEE80211_STA_ONLY 1416 if (intr & AR_ISR_SWBA) { 1417 s = splnet(); 1418 ar9003_swba_intr(sc); 1419 splx(s); 1420 } 1421 #endif 1422 if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 1423 ar9003_rx_intr(sc, ATHN_QID_LP); 1424 if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 1425 ar9003_rx_intr(sc, ATHN_QID_LP); 1426 if (intr & AR_ISR_HP_RXOK) 1427 ar9003_rx_intr(sc, ATHN_QID_HP); 1428 1429 if (intr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 1430 ar9003_tx_intr(sc); 1431 if (intr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) 1432 ar9003_tx_intr(sc); 1433 1434 if (intr & AR_ISR_GENTMR) { 1435 uint32_t intr5 = AR_READ(sc, AR_ISR_S5_S); 1436 #ifdef ATHN_DEBUG 1437 DPRINTFN(DBG_INTR, sc, 1438 "GENTMR trigger=%d thresh=%d\n", 1439 MS(intr5, AR_ISR_S5_GENTIMER_TRIG), 1440 MS(intr5, AR_ISR_S5_GENTIMER_THRESH)); 1441 #else 1442 __USE(intr5); 1443 #endif 1444 } 1445 } 1446 if (sync != 0) { 1447 if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 1448 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF); 1449 AR_WRITE(sc, AR_RC, 0); 1450 } 1451 1452 if ((sc->sc_flags & ATHN_FLAG_RFSILENT) && 1453 (sync & AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin))) { 1454 pmf_event_inject(sc->sc_dev, PMFE_RADIO_OFF); 1455 return 1; 1456 } 1457 1458 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync); 1459 (void)AR_READ(sc, AR_INTR_SYNC_CAUSE); 1460 } 1461 return 1; 1462 } 1463 1464 Static int 1465 ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 1466 int txflags) 1467 { 1468 struct ieee80211com *ic = &sc->sc_ic; 1469 struct ieee80211_key *k = NULL; 1470 struct ieee80211_frame *wh; 1471 struct athn_series series[4]; 1472 struct ar_tx_desc *ds; 1473 struct athn_txq *txq; 1474 struct athn_tx_buf *bf; 1475 struct athn_node *an = (void *)ni; 1476 struct mbuf *m1; 1477 uint32_t sum; 1478 uint16_t qos; 1479 uint8_t txpower, type, encrtype, ridx[4]; 1480 int i, error, totlen, hasqos, qid; 1481 1482 /* Grab a Tx buffer from our global free list. */ 1483 bf = SIMPLEQ_FIRST(&sc->sc_txbufs); 1484 KASSERT(bf != NULL); 1485 1486 /* Map 802.11 frame type to hardware frame type. */ 1487 wh = mtod(m, struct ieee80211_frame *); 1488 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1489 IEEE80211_FC0_TYPE_MGT) { 1490 /* NB: Beacons do not use ar9003_tx(). */ 1491 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1492 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1493 type = AR_FRAME_TYPE_PROBE_RESP; 1494 else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1495 IEEE80211_FC0_SUBTYPE_ATIM) 1496 type = AR_FRAME_TYPE_ATIM; 1497 else 1498 type = AR_FRAME_TYPE_NORMAL; 1499 } 1500 else if ((wh->i_fc[0] & 1501 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1502 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_PS_POLL)) { 1503 type = AR_FRAME_TYPE_PSPOLL; 1504 } 1505 else 1506 type = AR_FRAME_TYPE_NORMAL; 1507 1508 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1509 k = ieee80211_crypto_encap(ic, ni, m); 1510 if (k == NULL) 1511 return ENOBUFS; 1512 1513 /* packet header may have moved, reset our local pointer */ 1514 wh = mtod(m, struct ieee80211_frame *); 1515 } 1516 1517 /* XXX 2-byte padding for QoS and 4-addr headers. */ 1518 1519 /* Select the HW Tx queue to use for this frame. */ 1520 if ((hasqos = ieee80211_has_qos(wh))) { 1521 #ifdef notyet_edca 1522 uint8_t tid; 1523 1524 qos = ieee80211_get_qos(wh); 1525 tid = qos & IEEE80211_QOS_TID; 1526 qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)]; 1527 #else 1528 qos = ieee80211_get_qos(wh); 1529 qid = ATHN_QID_AC_BE; 1530 #endif /* notyet_edca */ 1531 } 1532 else if (type == AR_FRAME_TYPE_PSPOLL) { 1533 qos = 0; 1534 qid = ATHN_QID_PSPOLL; 1535 } 1536 else if (txflags & ATHN_TXFLAG_CAB) { 1537 qos = 0; 1538 qid = ATHN_QID_CAB; 1539 } 1540 else { 1541 qos = 0; 1542 qid = ATHN_QID_AC_BE; 1543 } 1544 txq = &sc->sc_txq[qid]; 1545 1546 /* Select the transmit rates to use for this frame. */ 1547 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1548 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 1549 IEEE80211_FC0_TYPE_DATA) { 1550 /* Use lowest rate for all tries. */ 1551 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1552 (ic->ic_curmode == IEEE80211_MODE_11A) ? 1553 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1554 } 1555 else if (ic->ic_fixed_rate != -1) { 1556 /* Use same fixed rate for all tries. */ 1557 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1558 sc->sc_fixed_ridx; 1559 } 1560 else { 1561 int txrate = ni->ni_txrate; 1562 /* Use fallback table of the node. */ 1563 for (i = 0; i < 4; i++) { 1564 ridx[i] = an->ridx[txrate]; 1565 txrate = an->fallback[txrate]; 1566 } 1567 } 1568 1569 if (__predict_false(sc->sc_drvbpf != NULL)) { 1570 struct athn_tx_radiotap_header *tap = &sc->sc_txtap; 1571 1572 tap->wt_flags = 0; 1573 /* Use initial transmit rate. */ 1574 tap->wt_rate = athn_rates[ridx[0]].rate; 1575 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1576 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1577 // XXX tap->wt_hwqueue = qid; 1578 if (ridx[0] != ATHN_RIDX_CCK1 && 1579 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1580 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1581 1582 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 1583 } 1584 1585 /* DMA map mbuf. */ 1586 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1587 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1588 if (__predict_false(error != 0)) { 1589 if (error != EFBIG) { 1590 aprint_error_dev(sc->sc_dev, 1591 "can't map mbuf (error %d)\n", error); 1592 m_freem(m); 1593 return error; 1594 } 1595 /* 1596 * DMA mapping requires too many DMA segments; linearize 1597 * mbuf in kernel virtual address space and retry. 1598 */ 1599 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1600 if (m1 == NULL) { 1601 m_freem(m); 1602 return ENOBUFS; 1603 } 1604 if (m->m_pkthdr.len > (int)MHLEN) { 1605 MCLGET(m1, M_DONTWAIT); 1606 if (!(m1->m_flags & M_EXT)) { 1607 m_freem(m); 1608 m_freem(m1); 1609 return ENOBUFS; 1610 } 1611 } 1612 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 1613 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1614 m_freem(m); 1615 m = m1; 1616 1617 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1618 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1619 if (error != 0) { 1620 aprint_error_dev(sc->sc_dev, 1621 "can't map mbuf (error %d)\n", error); 1622 m_freem(m); 1623 return error; 1624 } 1625 } 1626 bf->bf_m = m; 1627 bf->bf_ni = ni; 1628 bf->bf_txflags = txflags; 1629 1630 wh = mtod(m, struct ieee80211_frame *); 1631 1632 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1633 1634 /* Setup Tx descriptor. */ 1635 ds = bf->bf_descs; 1636 memset(ds, 0, sizeof(*ds)); 1637 1638 ds->ds_info = 1639 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1640 SM(AR_TXI_DESC_NDWORDS, 23) | 1641 SM(AR_TXI_QCU_NUM, qid) | 1642 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1643 1644 ds->ds_ctl11 = AR_TXC11_CLR_DEST_MASK; 1645 txpower = AR_MAX_RATE_POWER; /* Get from per-rate registers. */ 1646 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, txpower); 1647 1648 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, type); 1649 1650 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1651 (hasqos && (qos & IEEE80211_QOS_ACKPOLICY_MASK) == 1652 IEEE80211_QOS_ACKPOLICY_NOACK)) 1653 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1654 1655 #if notyet 1656 if (0 && k != NULL) { 1657 uintptr_t entry; 1658 1659 /* 1660 * Map 802.11 cipher to hardware encryption type and 1661 * compute MIC+ICV overhead. 1662 */ 1663 switch (k->k_cipher) { 1664 case IEEE80211_CIPHER_WEP40: 1665 case IEEE80211_CIPHER_WEP104: 1666 encrtype = AR_ENCR_TYPE_WEP; 1667 totlen += 4; 1668 break; 1669 case IEEE80211_CIPHER_TKIP: 1670 encrtype = AR_ENCR_TYPE_TKIP; 1671 totlen += 12; 1672 break; 1673 case IEEE80211_CIPHER_CCMP: 1674 encrtype = AR_ENCR_TYPE_AES; 1675 totlen += 8; 1676 break; 1677 default: 1678 panic("unsupported cipher"); 1679 } 1680 /* 1681 * NB: The key cache entry index is stored in the key 1682 * private field when the key is installed. 1683 */ 1684 entry = (uintptr_t)k->k_priv; 1685 ds->ds_ctl12 |= SM(AR_TXC12_DEST_IDX, entry); 1686 ds->ds_ctl11 |= AR_TXC11_DEST_IDX_VALID; 1687 } 1688 else 1689 #endif 1690 encrtype = AR_ENCR_TYPE_CLEAR; 1691 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, encrtype); 1692 1693 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 1694 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1695 /* NB: Group frames are sent using CCK in 802.11b/g. */ 1696 if (totlen > ic->ic_rtsthreshold) { 1697 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1698 } 1699 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1700 athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) { 1701 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1702 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1703 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1704 ds->ds_ctl11 |= AR_TXC11_CTS_ENABLE; 1705 } 1706 } 1707 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1708 /* Disable multi-rate retries when protection is used. */ 1709 ridx[1] = ridx[2] = ridx[3] = ridx[0]; 1710 } 1711 /* Setup multi-rate retries. */ 1712 for (i = 0; i < 4; i++) { 1713 series[i].hwrate = athn_rates[ridx[i]].hwrate; 1714 if (athn_rates[ridx[i]].phy == IEEE80211_T_DS && 1715 ridx[i] != ATHN_RIDX_CCK1 && 1716 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1717 series[i].hwrate |= 0x04; 1718 series[i].dur = 0; 1719 } 1720 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1721 /* Compute duration for each series. */ 1722 for (i = 0; i < 4; i++) { 1723 series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN, 1724 athn_rates[ridx[i]].rspridx, ic->ic_flags); 1725 } 1726 } 1727 /* If this is a PA training frame, select the Tx chain to use. */ 1728 if (__predict_false(txflags & ATHN_TXFLAG_PAPRD)) { 1729 ds->ds_ctl12 |= SM(AR_TXC12_PAPRD_CHAIN_MASK, 1730 1 << sc->sc_paprd_curchain); 1731 } 1732 1733 /* Write number of tries for each series. */ 1734 ds->ds_ctl13 = 1735 SM(AR_TXC13_XMIT_DATA_TRIES0, 2) | 1736 SM(AR_TXC13_XMIT_DATA_TRIES1, 2) | 1737 SM(AR_TXC13_XMIT_DATA_TRIES2, 2) | 1738 SM(AR_TXC13_XMIT_DATA_TRIES3, 4); 1739 1740 /* Tell HW to update duration field in 802.11 header. */ 1741 if (type != AR_FRAME_TYPE_PSPOLL) 1742 ds->ds_ctl13 |= AR_TXC13_DUR_UPDATE_ENA; 1743 1744 /* Write Tx rate for each series. */ 1745 ds->ds_ctl14 = 1746 SM(AR_TXC14_XMIT_RATE0, series[0].hwrate) | 1747 SM(AR_TXC14_XMIT_RATE1, series[1].hwrate) | 1748 SM(AR_TXC14_XMIT_RATE2, series[2].hwrate) | 1749 SM(AR_TXC14_XMIT_RATE3, series[3].hwrate); 1750 1751 /* Write duration for each series. */ 1752 ds->ds_ctl15 = 1753 SM(AR_TXC15_PACKET_DUR0, series[0].dur) | 1754 SM(AR_TXC15_PACKET_DUR1, series[1].dur); 1755 ds->ds_ctl16 = 1756 SM(AR_TXC16_PACKET_DUR2, series[2].dur) | 1757 SM(AR_TXC16_PACKET_DUR3, series[3].dur); 1758 1759 if ((sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) && 1760 ic->ic_curmode == IEEE80211_MODE_11A) { 1761 /* 1762 * In order to not exceed PCIe power requirements, we only 1763 * use two Tx chains for MCS0~15 on 5GHz band on these chips. 1764 */ 1765 ds->ds_ctl18 = 1766 SM(AR_TXC18_CHAIN_SEL0, 1767 (ridx[0] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1768 SM(AR_TXC18_CHAIN_SEL1, 1769 (ridx[1] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1770 SM(AR_TXC18_CHAIN_SEL2, 1771 (ridx[2] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1772 SM(AR_TXC18_CHAIN_SEL3, 1773 (ridx[3] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask); 1774 } 1775 else { 1776 /* Use the same Tx chains for all tries. */ 1777 ds->ds_ctl18 = 1778 SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask) | 1779 SM(AR_TXC18_CHAIN_SEL1, sc->sc_txchainmask) | 1780 SM(AR_TXC18_CHAIN_SEL2, sc->sc_txchainmask) | 1781 SM(AR_TXC18_CHAIN_SEL3, sc->sc_txchainmask); 1782 } 1783 #ifdef notyet 1784 #ifndef IEEE80211_NO_HT 1785 /* Use the same short GI setting for all tries. */ 1786 if (ic->ic_flags & IEEE80211_F_SHGI) 1787 ds->ds_ctl18 |= AR_TXC18_GI0123; 1788 /* Use the same channel width for all tries. */ 1789 if (ic->ic_flags & IEEE80211_F_CBW40) 1790 ds->ds_ctl18 |= AR_TXC18_2040_0123; 1791 #endif 1792 #endif 1793 1794 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1795 uint8_t protridx, hwrate; 1796 uint16_t dur = 0; 1797 1798 /* Use the same protection mode for all tries. */ 1799 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1800 ds->ds_ctl15 |= AR_TXC15_RTSCTS_QUAL01; 1801 ds->ds_ctl16 |= AR_TXC16_RTSCTS_QUAL23; 1802 } 1803 /* Select protection rate (suboptimal but ok). */ 1804 protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1805 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2; 1806 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1807 /* Account for CTS duration. */ 1808 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1809 athn_rates[protridx].rspridx, ic->ic_flags); 1810 } 1811 dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags); 1812 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1813 /* Account for ACK duration. */ 1814 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1815 athn_rates[ridx[0]].rspridx, ic->ic_flags); 1816 } 1817 /* Write protection frame duration and rate. */ 1818 ds->ds_ctl13 |= SM(AR_TXC13_BURST_DUR, dur); 1819 hwrate = athn_rates[protridx].hwrate; 1820 if (protridx == ATHN_RIDX_CCK2 && 1821 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1822 hwrate |= 0x04; 1823 ds->ds_ctl18 |= SM(AR_TXC18_RTSCTS_RATE, hwrate); 1824 } 1825 1826 ds->ds_ctl11 |= SM(AR_TXC11_FRAME_LEN, totlen); 1827 ds->ds_ctl19 = AR_TXC19_NOT_SOUNDING; 1828 1829 for (i = 0; i < bf->bf_map->dm_nsegs; i++) { 1830 ds->ds_segs[i].ds_data = bf->bf_map->dm_segs[i].ds_addr; 1831 ds->ds_segs[i].ds_ctl = SM(AR_TXC_BUF_LEN, 1832 bf->bf_map->dm_segs[i].ds_len); 1833 } 1834 /* Compute Tx descriptor checksum. */ 1835 sum = ds->ds_info + ds->ds_link; 1836 for (i = 0; i < 4; i++) { 1837 sum += ds->ds_segs[i].ds_data; 1838 sum += ds->ds_segs[i].ds_ctl; 1839 } 1840 sum = (sum >> 16) + (sum & 0xffff); 1841 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1842 1843 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1844 BUS_DMASYNC_PREWRITE); 1845 1846 DPRINTFN(DBG_TX, sc, 1847 "Tx qid=%d nsegs=%d ctl11=0x%x ctl12=0x%x ctl14=0x%x\n", 1848 qid, bf->bf_map->dm_nsegs, ds->ds_ctl11, ds->ds_ctl12, 1849 ds->ds_ctl14); 1850 1851 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 1852 SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list); 1853 1854 /* Queue buffer unless hardware FIFO is already full. */ 1855 if (++txq->queued <= AR9003_TX_QDEPTH) { 1856 AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr); 1857 AR_WRITE_BARRIER(sc); 1858 } 1859 else if (txq->wait == NULL) 1860 txq->wait = bf; 1861 return 0; 1862 } 1863 1864 Static void 1865 ar9003_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c) 1866 { 1867 uint32_t reg; 1868 1869 reg = IEEE80211_IS_CHAN_2GHZ(c) ? 1870 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 1871 if (IEEE80211_IS_CHAN_5GHZ(c) && 1872 (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 1873 reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE; 1874 } 1875 AR_WRITE(sc, AR_PHY_MODE, reg); 1876 AR_WRITE_BARRIER(sc); 1877 } 1878 1879 static __inline uint32_t 1880 ar9003_synth_delay(struct athn_softc *sc) 1881 { 1882 uint32_t synth_delay; 1883 1884 synth_delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY); 1885 if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B) 1886 synth_delay = (synth_delay * 4) / 22; 1887 else 1888 synth_delay = synth_delay / 10; /* in 100ns steps */ 1889 return synth_delay; 1890 } 1891 1892 Static int 1893 ar9003_rf_bus_request(struct athn_softc *sc) 1894 { 1895 int ntries; 1896 1897 /* Request RF Bus grant. */ 1898 AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1899 for (ntries = 0; ntries < 10000; ntries++) { 1900 if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN) 1901 return 0; 1902 DELAY(10); 1903 } 1904 DPRINTFN(DBG_RF, sc, "could not kill baseband Rx"); 1905 return ETIMEDOUT; 1906 } 1907 1908 Static void 1909 ar9003_rf_bus_release(struct athn_softc *sc) 1910 { 1911 /* Wait for the synthesizer to settle. */ 1912 DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar9003_synth_delay(sc)); 1913 1914 /* Release the RF Bus grant. */ 1915 AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0); 1916 AR_WRITE_BARRIER(sc); 1917 } 1918 1919 Static void 1920 ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c, 1921 struct ieee80211_channel *extc) 1922 { 1923 uint32_t phy; 1924 1925 phy = AR_READ(sc, AR_PHY_GEN_CTRL); 1926 phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | 1927 AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH; 1928 #ifndef IEEE80211_NO_HT 1929 if (extc != NULL) { 1930 phy |= AR_PHY_GC_DYN2040_EN; 1931 if (extc > c) /* XXX */ 1932 phy |= AR_PHY_GC_DYN2040_PRI_CH; 1933 } 1934 #endif 1935 /* Turn off Green Field detection for now. */ 1936 phy &= ~AR_PHY_GC_GF_DETECT_EN; 1937 AR_WRITE(sc, AR_PHY_GEN_CTRL, phy); 1938 1939 AR_WRITE(sc, AR_2040_MODE, 1940 (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0); 1941 1942 /* Set global transmit timeout. */ 1943 AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25)); 1944 /* Set carrier sense timeout. */ 1945 AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15)); 1946 AR_WRITE_BARRIER(sc); 1947 } 1948 1949 Static void 1950 ar9003_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c, 1951 struct ieee80211_channel *extc) 1952 { 1953 uint32_t coeff, exp, man, reg; 1954 1955 /* Set Delta Slope (exponent and mantissa). */ 1956 coeff = (100 << 24) / c->ic_freq; 1957 athn_get_delta_slope(coeff, &exp, &man); 1958 DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man); 1959 1960 reg = AR_READ(sc, AR_PHY_TIMING3); 1961 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); 1962 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); 1963 AR_WRITE(sc, AR_PHY_TIMING3, reg); 1964 1965 /* For Short GI, coeff is 9/10 that of normal coeff. */ 1966 coeff = (9 * coeff) / 10; 1967 athn_get_delta_slope(coeff, &exp, &man); 1968 DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man); 1969 1970 reg = AR_READ(sc, AR_PHY_SGI_DELTA); 1971 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); 1972 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); 1973 AR_WRITE(sc, AR_PHY_SGI_DELTA, reg); 1974 AR_WRITE_BARRIER(sc); 1975 } 1976 1977 Static void 1978 ar9003_enable_antenna_diversity(struct athn_softc *sc) 1979 { 1980 AR_SETBITS(sc, AR_PHY_CCK_DETECT, 1981 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1982 AR_WRITE_BARRIER(sc); 1983 } 1984 1985 Static void 1986 ar9003_init_baseband(struct athn_softc *sc) 1987 { 1988 uint32_t synth_delay; 1989 1990 synth_delay = ar9003_synth_delay(sc); 1991 /* Activate the PHY (includes baseband activate and synthesizer on). */ 1992 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 1993 AR_WRITE_BARRIER(sc); 1994 DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay); 1995 } 1996 1997 Static void 1998 ar9003_disable_phy(struct athn_softc *sc) 1999 { 2000 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2001 AR_WRITE_BARRIER(sc); 2002 } 2003 2004 Static void 2005 ar9003_init_chains(struct athn_softc *sc) 2006 { 2007 if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5) 2008 AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 2009 2010 /* Setup chain masks. */ 2011 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); 2012 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); 2013 2014 if (sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) { 2015 /* 2016 * All self-generated frames are sent using two Tx chains 2017 * on these chips to not exceed PCIe power requirements. 2018 */ 2019 AR_WRITE(sc, AR_SELFGEN_MASK, 0x3); 2020 } 2021 else 2022 AR_WRITE(sc, AR_SELFGEN_MASK, sc->sc_txchainmask); 2023 AR_WRITE_BARRIER(sc); 2024 } 2025 2026 Static void 2027 ar9003_set_rxchains(struct athn_softc *sc) 2028 { 2029 if (sc->sc_rxchainmask == 0x3 || sc->sc_rxchainmask == 0x5) { 2030 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); 2031 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); 2032 AR_WRITE_BARRIER(sc); 2033 } 2034 } 2035 2036 #ifdef notused 2037 Static void 2038 ar9003_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 2039 { 2040 /* Sign-extends 9-bit value (assumes upper bits are zeroes). */ 2041 #define SIGN_EXT(v) (((v) ^ 0x100) - 0x100) 2042 uint32_t reg; 2043 int i; 2044 2045 for (i = 0; i < sc->sc_nrxchains; i++) { 2046 reg = AR_READ(sc, AR_PHY_CCA(i)); 2047 nf[i] = MS(reg, AR_PHY_MINCCA_PWR); 2048 nf[i] = SIGN_EXT(nf[i]); 2049 2050 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 2051 nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR); 2052 nf_ext[i] = SIGN_EXT(nf_ext[i]); 2053 } 2054 #undef SIGN_EXT 2055 } 2056 #endif /* notused */ 2057 2058 #ifdef notused 2059 Static void 2060 ar9003_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 2061 { 2062 uint32_t reg; 2063 int i; 2064 2065 for (i = 0; i < sc->sc_nrxchains; i++) { 2066 reg = AR_READ(sc, AR_PHY_CCA(i)); 2067 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); 2068 AR_WRITE(sc, AR_PHY_CCA(i), reg); 2069 2070 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 2071 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); 2072 AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg); 2073 } 2074 AR_WRITE_BARRIER(sc); 2075 } 2076 #endif /* notused */ 2077 2078 #ifdef notused 2079 Static void 2080 ar9003_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c) 2081 { 2082 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2083 int16_t cca_min, cca_max; 2084 int i; 2085 2086 if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 2087 /* Noisefloor calibration not finished. */ 2088 return; 2089 } 2090 /* Noisefloor calibration is finished. */ 2091 ar9003_read_noisefloor(sc, nf, nf_ext); 2092 2093 if (IEEE80211_IS_CHAN_2GHZ(c)) { 2094 cca_min = sc->sc_cca_min_2g; 2095 cca_max = sc->sc_cca_max_2g; 2096 } 2097 else { 2098 cca_min = sc->sc_cca_min_5g; 2099 cca_max = sc->sc_cca_max_5g; 2100 } 2101 /* Update noisefloor history. */ 2102 for (i = 0; i < sc->sc_nrxchains; i++) { 2103 if (nf[i] < cca_min) 2104 nf[i] = cca_min; 2105 else if (nf[i] > cca_max) 2106 nf[i] = cca_max; 2107 if (nf_ext[i] < cca_min) 2108 nf_ext[i] = cca_min; 2109 else if (nf_ext[i] > cca_max) 2110 nf_ext[i] = cca_max; 2111 2112 sc->sc_nf_hist[sc->sc_nf_hist_cur].nf[i] = nf[i]; 2113 sc->sc_nf_hist[sc->sc_nf_hist_cur].nf_ext[i] = nf_ext[i]; 2114 } 2115 if (++sc->sc_nf_hist_cur >= ATHN_NF_CAL_HIST_MAX) 2116 sc->sc_nf_hist_cur = 0; 2117 } 2118 #endif /* notused */ 2119 2120 #ifdef notused 2121 Static void 2122 ar9003_bb_load_noisefloor(struct athn_softc *sc) 2123 { 2124 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2125 int i, ntries; 2126 2127 /* Write filtered noisefloor values. */ 2128 for (i = 0; i < sc->sc_nrxchains; i++) { 2129 nf[i] = sc->sc_nf_priv[i] * 2; 2130 nf_ext[i] = sc->sc_nf_ext_priv[i] * 2; 2131 } 2132 ar9003_write_noisefloor(sc, nf, nf_ext); 2133 2134 /* Load filtered noisefloor values into baseband. */ 2135 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2136 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2137 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2138 /* Wait for load to complete. */ 2139 for (ntries = 0; ntries < 1000; ntries++) { 2140 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) 2141 break; 2142 DELAY(10); 2143 } 2144 if (ntries == 1000) { 2145 DPRINTFN(DBG_RF, sc, "failed to load noisefloor values\n"); 2146 return; 2147 } 2148 2149 /* Restore noisefloor values to initial (max) values. */ 2150 for (i = 0; i < AR_MAX_CHAINS; i++) 2151 nf[i] = nf_ext[i] = -50 * 2; 2152 ar9003_write_noisefloor(sc, nf, nf_ext); 2153 } 2154 #endif /* notused */ 2155 2156 #ifdef notused 2157 Static void 2158 ar9300_noisefloor_calib(struct athn_softc *sc) 2159 { 2160 2161 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2162 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2163 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2164 } 2165 #endif /* notused */ 2166 2167 Static void 2168 ar9003_do_noisefloor_calib(struct athn_softc *sc) 2169 { 2170 2171 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2172 } 2173 2174 PUBLIC int 2175 ar9003_init_calib(struct athn_softc *sc) 2176 { 2177 uint8_t txchainmask, rxchainmask; 2178 uint32_t reg; 2179 int ntries; 2180 2181 /* Save chains masks. */ 2182 txchainmask = sc->sc_txchainmask; 2183 rxchainmask = sc->sc_rxchainmask; 2184 /* Configure hardware before calibration. */ 2185 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE) 2186 txchainmask = rxchainmask = 0x3; 2187 else 2188 txchainmask = rxchainmask = 0x7; 2189 ar9003_init_chains(sc); 2190 2191 /* Perform Tx IQ calibration. */ 2192 ar9003_calib_tx_iq(sc); 2193 /* Disable and re-enable the PHY chips. */ 2194 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2195 AR_WRITE_BARRIER(sc); 2196 DELAY(5); 2197 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 2198 2199 /* Calibrate the AGC. */ 2200 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 2201 /* Poll for offset calibration completion. */ 2202 for (ntries = 0; ntries < 10000; ntries++) { 2203 reg = AR_READ(sc, AR_PHY_AGC_CONTROL); 2204 if (!(reg & AR_PHY_AGC_CONTROL_CAL)) 2205 break; 2206 DELAY(10); 2207 } 2208 if (ntries == 10000) 2209 return ETIMEDOUT; 2210 2211 /* Restore chains masks. */ 2212 sc->sc_txchainmask = txchainmask; 2213 sc->sc_rxchainmask = rxchainmask; 2214 ar9003_init_chains(sc); 2215 2216 return 0; 2217 } 2218 2219 Static void 2220 ar9003_do_calib(struct athn_softc *sc) 2221 { 2222 uint32_t reg; 2223 2224 if (sc->sc_cur_calib_mask & ATHN_CAL_IQ) { 2225 reg = AR_READ(sc, AR_PHY_TIMING4); 2226 reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10); 2227 AR_WRITE(sc, AR_PHY_TIMING4, reg); 2228 AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 2229 AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); 2230 AR_WRITE_BARRIER(sc); 2231 } 2232 else if (sc->sc_cur_calib_mask & ATHN_CAL_TEMP) { 2233 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2234 AR_PHY_65NM_CH0_THERM_LOCAL); 2235 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2236 AR_PHY_65NM_CH0_THERM_START); 2237 AR_WRITE_BARRIER(sc); 2238 } 2239 } 2240 2241 Static void 2242 ar9003_next_calib(struct athn_softc *sc) 2243 { 2244 /* Check if we have any calibration in progress. */ 2245 if (sc->sc_cur_calib_mask != 0) { 2246 if (!(AR_READ(sc, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { 2247 /* Calibration completed for current sample. */ 2248 ar9003_calib_iq(sc); 2249 } 2250 } 2251 } 2252 2253 Static void 2254 ar9003_calib_iq(struct athn_softc *sc) 2255 { 2256 struct athn_iq_cal *cal; 2257 uint32_t reg, i_coff_denom, q_coff_denom; 2258 int32_t i_coff, q_coff; 2259 int i, iq_corr_neg; 2260 2261 for (i = 0; i < AR_MAX_CHAINS; i++) { 2262 cal = &sc->sc_calib.iq[i]; 2263 2264 /* Read IQ calibration measures (clear on read). */ 2265 cal->pwr_meas_i = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_0_B(i)); 2266 cal->pwr_meas_q = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_1_B(i)); 2267 cal->iq_corr_meas = 2268 (int32_t)AR_READ(sc, AR_PHY_IQ_ADC_MEAS_2_B(i)); 2269 } 2270 2271 for (i = 0; i < sc->sc_nrxchains; i++) { 2272 cal = &sc->sc_calib.iq[i]; 2273 2274 if (cal->pwr_meas_q == 0) 2275 continue; 2276 2277 if ((iq_corr_neg = cal->iq_corr_meas) < 0) 2278 cal->iq_corr_meas = -cal->iq_corr_meas; 2279 2280 i_coff_denom = 2281 (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 256; 2282 q_coff_denom = cal->pwr_meas_q / 64; 2283 2284 if (i_coff_denom == 0 || q_coff_denom == 0) 2285 continue; /* Prevents division by zero. */ 2286 2287 i_coff = cal->iq_corr_meas / i_coff_denom; 2288 q_coff = (cal->pwr_meas_i / q_coff_denom) - 64; 2289 2290 if (i_coff > 63) 2291 i_coff = 63; 2292 else if (i_coff < -63) 2293 i_coff = -63; 2294 /* Negate i_coff if iq_corr_meas is positive. */ 2295 if (!iq_corr_neg) 2296 i_coff = -i_coff; 2297 if (q_coff > 63) 2298 q_coff = 63; 2299 else if (q_coff < -63) 2300 q_coff = -63; 2301 2302 DPRINTFN(DBG_RF, sc, "IQ calibration for chain %d\n", i); 2303 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2304 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff); 2305 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff); 2306 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2307 } 2308 2309 /* Apply new settings. */ 2310 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2311 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); 2312 AR_WRITE_BARRIER(sc); 2313 2314 /* IQ calibration done. */ 2315 sc->sc_cur_calib_mask &= ~ATHN_CAL_IQ; 2316 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2317 } 2318 2319 #define DELPT 32 2320 Static int 2321 ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2]) 2322 { 2323 /* Sign-extends 12-bit value (assumes upper bits are zeroes). */ 2324 #define SIGN_EXT(v) (((v) ^ 0x800) - 0x800) 2325 #define SCALE (1 << 15) 2326 #define SHIFT (1 << 8) 2327 struct { 2328 int32_t m, p, c; 2329 } val[2][2]; 2330 int32_t mag[2][2], phs[2][2], cos[2], sin[2]; 2331 int32_t div, f1, f2, f3, m, p, c; 2332 int32_t txmag, txphs, rxmag, rxphs; 2333 int32_t q_coff, i_coff; 2334 int i, j; 2335 2336 /* Extract our twelve signed 12-bit values from res[] array. */ 2337 val[0][0].m = res[0] & 0xfff; 2338 val[0][0].p = (res[0] >> 12) & 0xfff; 2339 val[0][0].c = ((res[0] >> 24) & 0xff) | (res[1] & 0xf) << 8; 2340 2341 val[0][1].m = (res[1] >> 4) & 0xfff; 2342 val[0][1].p = res[2] & 0xfff; 2343 val[0][1].c = (res[2] >> 12) & 0xfff; 2344 2345 val[1][0].m = ((res[2] >> 24) & 0xff) | (res[3] & 0xf) << 8; 2346 val[1][0].p = (res[3] >> 4) & 0xfff; 2347 val[1][0].c = res[4] & 0xfff; 2348 2349 val[1][1].m = (res[4] >> 12) & 0xfff; 2350 val[1][1].p = ((res[4] >> 24) & 0xff) | (res[5] & 0xf) << 8; 2351 val[1][1].c = (res[5] >> 4) & 0xfff; 2352 2353 for (i = 0; i < 2; i++) { 2354 int32_t ymin, ymax; 2355 for (j = 0; j < 2; j++) { 2356 m = SIGN_EXT(val[i][j].m); 2357 p = SIGN_EXT(val[i][j].p); 2358 c = SIGN_EXT(val[i][j].c); 2359 2360 if (p == 0) 2361 return 1; /* Prevent division by 0. */ 2362 2363 mag[i][j] = (m * SCALE) / p; 2364 phs[i][j] = (c * SCALE) / p; 2365 } 2366 sin[i] = ((mag[i][0] - mag[i][1]) * SHIFT) / DELPT; 2367 cos[i] = ((phs[i][0] - phs[i][1]) * SHIFT) / DELPT; 2368 /* Find magnitude by approximation. */ 2369 ymin = MIN(abs(sin[i]), abs(cos[i])); 2370 ymax = MAX(abs(sin[i]), abs(cos[i])); 2371 div = ymax - (ymax / 32) + (ymin / 8) + (ymin / 4); 2372 if (div == 0) 2373 return 1; /* Prevent division by 0. */ 2374 /* Normalize sin and cos by magnitude. */ 2375 sin[i] = (sin[i] * SCALE) / div; 2376 cos[i] = (cos[i] * SCALE) / div; 2377 } 2378 2379 /* Compute IQ mismatch (solve 4x4 linear equation). */ 2380 f1 = cos[0] - cos[1]; 2381 f3 = sin[0] - sin[1]; 2382 f2 = (f1 * f1 + f3 * f3) / SCALE; 2383 if (f2 == 0) 2384 return 1; /* Prevent division by 0. */ 2385 2386 /* Compute Tx magnitude mismatch. */ 2387 txmag = (f1 * ( mag[0][0] - mag[1][0]) + 2388 f3 * ( phs[0][0] - phs[1][0])) / f2; 2389 /* Compute Tx phase mismatch. */ 2390 txphs = (f3 * (-mag[0][0] + mag[1][0]) + 2391 f1 * ( phs[0][0] - phs[1][0])) / f2; 2392 2393 if (txmag == SCALE) 2394 return 1; /* Prevent division by 0. */ 2395 2396 /* Compute Rx magnitude mismatch. */ 2397 rxmag = mag[0][0] - (cos[0] * txmag + sin[0] * txphs) / SCALE; 2398 /* Compute Rx phase mismatch. */ 2399 rxphs = phs[0][0] + (sin[0] * txmag - cos[0] * txphs) / SCALE; 2400 2401 if (-rxmag == SCALE) 2402 return 1; /* Prevent division by 0. */ 2403 2404 txmag = (txmag * SCALE) / (SCALE - txmag); 2405 txphs = -txphs; 2406 2407 q_coff = (txmag * 128) / SCALE; 2408 if (q_coff < -63) 2409 q_coff = -63; 2410 else if (q_coff > 63) 2411 q_coff = 63; 2412 i_coff = (txphs * 256) / SCALE; 2413 if (i_coff < -63) 2414 i_coff = -63; 2415 else if (i_coff > 63) 2416 i_coff = 63; 2417 coeff[0] = q_coff * 128 + i_coff; 2418 2419 rxmag = (-rxmag * SCALE) / (SCALE + rxmag); 2420 rxphs = -rxphs; 2421 2422 q_coff = (rxmag * 128) / SCALE; 2423 if (q_coff < -63) 2424 q_coff = -63; 2425 else if (q_coff > 63) 2426 q_coff = 63; 2427 i_coff = (rxphs * 256) / SCALE; 2428 if (i_coff < -63) 2429 i_coff = -63; 2430 else if (i_coff > 63) 2431 i_coff = 63; 2432 coeff[1] = q_coff * 128 + i_coff; 2433 2434 return 0; 2435 #undef SHIFT 2436 #undef SCALE 2437 #undef SIGN_EXT 2438 } 2439 2440 Static int 2441 ar9003_calib_tx_iq(struct athn_softc *sc) 2442 { 2443 uint32_t reg; 2444 int32_t res[6], coeff[2]; 2445 int i, j, ntries; 2446 2447 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1); 2448 reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT); 2449 AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg); 2450 2451 /* Start Tx IQ calibration. */ 2452 AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL); 2453 /* Wait for completion. */ 2454 for (ntries = 0; ntries < 10000; ntries++) { 2455 reg = AR_READ(sc, AR_PHY_TX_IQCAL_START); 2456 if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL)) 2457 break; 2458 DELAY(10); 2459 } 2460 if (ntries == 10000) 2461 return ETIMEDOUT; 2462 2463 for (i = 0; i < sc->sc_ntxchains; i++) { 2464 /* Read Tx IQ calibration status for this chain. */ 2465 reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i)); 2466 if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED) 2467 return EIO; 2468 /* 2469 * Read Tx IQ calibration results for this chain. 2470 * This consists in twelve signed 12-bit values. 2471 */ 2472 for (j = 0; j < 3; j++) { 2473 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2474 AR_PHY_CHAN_INFO_TAB_S2_READ); 2475 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2476 res[j * 2 + 0] = reg; 2477 2478 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2479 AR_PHY_CHAN_INFO_TAB_S2_READ); 2480 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2481 res[j * 2 + 1] = reg & 0xffff; 2482 } 2483 2484 /* Compute Tx IQ correction. */ 2485 if (ar9003_get_iq_corr(sc, res, coeff) != 0) 2486 return EIO; 2487 2488 /* Write Tx IQ correction coefficients. */ 2489 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)); 2490 reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, 2491 coeff[0]); 2492 AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg); 2493 2494 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2495 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF, 2496 coeff[1] >> 7); 2497 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF, 2498 coeff[1]); 2499 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2500 AR_WRITE_BARRIER(sc); 2501 } 2502 2503 /* Enable Tx IQ correction. */ 2504 AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_3, 2505 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN); 2506 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2507 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN); 2508 AR_WRITE_BARRIER(sc); 2509 return 0; 2510 } 2511 #undef DELPT 2512 2513 /*- 2514 * The power amplifier predistortion state machine works as follows: 2515 * 1) Disable digital predistorters for all Tx chains 2516 * 2) Repeat steps 3~7 for all Tx chains 2517 * 3) Force Tx gain to that of training signal 2518 * 4) Send training signal (asynchronous) 2519 * 5) Wait for training signal to complete (asynchronous) 2520 * 6) Read PA measurements (input power, output power, output phase) 2521 * 7) Compute the predistortion function that linearizes PA output 2522 * 8) Write predistortion functions to hardware tables for all Tx chains 2523 * 9) Enable digital predistorters for all Tx chains 2524 */ 2525 #ifdef notused 2526 Static void 2527 ar9003_paprd_calib(struct athn_softc *sc, struct ieee80211_channel *c) 2528 { 2529 static const int scaling[] = { 2530 261376, 248079, 233759, 220464, 2531 208194, 196949, 185706, 175487 2532 }; 2533 struct athn_ops *ops = &sc->sc_ops; 2534 uint32_t reg, ht20mask, ht40mask; 2535 int i; 2536 2537 /* Read PA predistortion masks from ROM. */ 2538 ops->get_paprd_masks(sc, c, &ht20mask, &ht40mask); 2539 2540 /* AM-to-AM: amplifier's amplitude characteristic. */ 2541 reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM); 2542 reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask); 2543 AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg); 2544 2545 /* AM-to-PM: amplifier's phase transfer characteristic. */ 2546 reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM); 2547 reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask); 2548 AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg); 2549 2550 reg = AR_READ(sc, AR_PHY_PAPRD_HT40); 2551 reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask); 2552 AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg); 2553 2554 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2555 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2556 AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE); 2557 2558 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i)); 2559 reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181); 2560 reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361); 2561 reg &= ~AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA; 2562 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA; 2563 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA; 2564 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg); 2565 2566 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i)); 2567 reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3); 2568 AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg); 2569 } 2570 2571 /* Disable all digital predistorters during calibration. */ 2572 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2573 AR_CLRBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2574 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 2575 } 2576 AR_WRITE_BARRIER(sc); 2577 2578 /* 2579 * Configure training signal. 2580 */ 2581 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1); 2582 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28); 2583 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30); 2584 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE; 2585 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE; 2586 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE; 2587 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE; 2588 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE; 2589 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg); 2590 2591 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL2, 147); 2592 2593 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3); 2594 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4); 2595 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4); 2596 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7); 2597 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1); 2598 if (AR_SREV_9485(sc)) 2599 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3); 2600 else 2601 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6); 2602 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15); 2603 reg |= AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE; 2604 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg); 2605 2606 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4); 2607 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0); 2608 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400); 2609 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100); 2610 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg); 2611 2612 for (i = 0; i < __arraycount(scaling); i++) { 2613 reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i)); 2614 reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]); 2615 AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg); 2616 } 2617 2618 /* Save Tx gain table. */ 2619 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE; i++) 2620 sc->sc_txgain[i] = AR_READ(sc, AR_PHY_TXGAIN_TABLE(i)); 2621 2622 /* Set Tx power of training signal (use setting for MCS0). */ 2623 sc->sc_trainpow = MS(AR_READ(sc, AR_PHY_PWRTX_RATE5), 2624 AR_PHY_PWRTX_RATE5_POWERTXHT20_0) - 4; 2625 2626 /* 2627 * Start PA predistortion calibration state machine. 2628 */ 2629 /* Find first available Tx chain. */ 2630 sc->sc_paprd_curchain = 0; 2631 while (!(sc->sc_txchainmask & (1 << sc->sc_paprd_curchain))) 2632 sc->sc_paprd_curchain++; 2633 2634 /* Make sure training done bit is clear. */ 2635 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 2636 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 2637 AR_WRITE_BARRIER(sc); 2638 2639 /* Transmit training signal. */ 2640 ar9003_paprd_tx_tone(sc); 2641 } 2642 #endif /* notused */ 2643 2644 Static int 2645 ar9003_get_desired_txgain(struct athn_softc *sc, int chain, int pow) 2646 { 2647 int32_t scale, atemp, avolt, tempcal, voltcal, temp, volt; 2648 int32_t tempcorr, voltcorr; 2649 uint32_t reg; 2650 int8_t delta; 2651 2652 scale = MS(AR_READ(sc, AR_PHY_TPC_12), 2653 AR_PHY_TPC_12_DESIRED_SCALE_HT40_5); 2654 2655 reg = AR_READ(sc, AR_PHY_TPC_19); 2656 atemp = MS(reg, AR_PHY_TPC_19_ALPHA_THERM); 2657 avolt = MS(reg, AR_PHY_TPC_19_ALPHA_VOLT); 2658 2659 reg = AR_READ(sc, AR_PHY_TPC_18); 2660 tempcal = MS(reg, AR_PHY_TPC_18_THERM_CAL); 2661 voltcal = MS(reg, AR_PHY_TPC_18_VOLT_CAL); 2662 2663 reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4); 2664 temp = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_THERM); 2665 volt = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_VOLT); 2666 2667 delta = (int8_t)MS(AR_READ(sc, AR_PHY_TPC_11_B(chain)), 2668 AR_PHY_TPC_11_OLPC_GAIN_DELTA); 2669 2670 /* Compute temperature and voltage correction. */ 2671 tempcorr = (atemp * (temp - tempcal) + 128) / 256; 2672 voltcorr = (avolt * (volt - voltcal) + 64) / 128; 2673 2674 /* Compute desired Tx gain. */ 2675 return pow - delta - tempcorr - voltcorr + scale; 2676 } 2677 2678 Static void 2679 ar9003_force_txgain(struct athn_softc *sc, uint32_t txgain) 2680 { 2681 uint32_t reg; 2682 2683 reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN); 2684 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN, 2685 MS(txgain, AR_PHY_TXGAIN_TXBB1DBGAIN)); 2686 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN, 2687 MS(txgain, AR_PHY_TXGAIN_TXBB6DBGAIN)); 2688 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN, 2689 MS(txgain, AR_PHY_TXGAIN_TXMXRGAIN)); 2690 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA, 2691 MS(txgain, AR_PHY_TXGAIN_PADRVGNA)); 2692 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB, 2693 MS(txgain, AR_PHY_TXGAIN_PADRVGNB)); 2694 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC, 2695 MS(txgain, AR_PHY_TXGAIN_PADRVGNC)); 2696 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND, 2697 MS(txgain, AR_PHY_TXGAIN_PADRVGND)); 2698 reg &= ~AR_PHY_TX_FORCED_GAIN_ENABLE_PAL; 2699 reg &= ~AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN; 2700 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg); 2701 2702 reg = AR_READ(sc, AR_PHY_TPC_1); 2703 reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0); 2704 reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN; 2705 AR_WRITE(sc, AR_PHY_TPC_1, reg); 2706 AR_WRITE_BARRIER(sc); 2707 } 2708 2709 Static void 2710 ar9003_set_training_gain(struct athn_softc *sc, int chain) 2711 { 2712 size_t i; 2713 int gain; 2714 2715 /* 2716 * Get desired gain for training signal power (take into account 2717 * current temperature/voltage). 2718 */ 2719 gain = ar9003_get_desired_txgain(sc, chain, sc->sc_trainpow); 2720 /* Find entry in table. */ 2721 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE - 1; i++) 2722 if ((int)MS(sc->sc_txgain[i], AR_PHY_TXGAIN_INDEX) >= gain) 2723 break; 2724 ar9003_force_txgain(sc, sc->sc_txgain[i]); 2725 } 2726 2727 Static int 2728 ar9003_paprd_tx_tone(struct athn_softc *sc) 2729 { 2730 #define TONE_LEN 1800 2731 struct ieee80211com *ic = &sc->sc_ic; 2732 struct ieee80211_frame *wh; 2733 struct ieee80211_node *ni; 2734 struct mbuf *m; 2735 int error; 2736 2737 /* Build a Null (no data) frame of TONE_LEN bytes. */ 2738 m = MCLGETI(NULL, M_DONTWAIT, NULL, TONE_LEN); 2739 if (m == NULL) 2740 return ENOBUFS; 2741 memset(mtod(m, void *), 0, TONE_LEN); 2742 wh = mtod(m, struct ieee80211_frame *); 2743 wh->i_fc[0] = IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_NODATA; 2744 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 2745 *(uint16_t *)wh->i_dur = htole16(10); /* XXX */ 2746 IEEE80211_ADDR_COPY(wh->i_addr1, ic->ic_myaddr); 2747 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 2748 IEEE80211_ADDR_COPY(wh->i_addr3, ic->ic_myaddr); 2749 m->m_pkthdr.len = m->m_len = TONE_LEN; 2750 2751 /* Set gain of training signal. */ 2752 ar9003_set_training_gain(sc, sc->sc_paprd_curchain); 2753 2754 /* Transmit training signal. */ 2755 ni = ieee80211_ref_node(ic->ic_bss); 2756 if ((error = ar9003_tx(sc, m, ni, ATHN_TXFLAG_PAPRD)) != 0) 2757 ieee80211_free_node(ni); 2758 return error; 2759 #undef TONE_LEN 2760 } 2761 2762 static __inline int 2763 get_scale(int val) 2764 { 2765 int log = 0; 2766 2767 /* Find the log base 2 (position of highest bit set). */ 2768 while (val >>= 1) 2769 log++; 2770 2771 return (log > 10) ? log - 10 : 0; 2772 } 2773 2774 /* 2775 * Compute predistortion function to linearize power amplifier output based 2776 * on feedback from training signal. 2777 */ 2778 Static int 2779 ar9003_compute_predistortion(struct athn_softc *sc, const uint32_t *lo, 2780 const uint32_t *hi) 2781 { 2782 #define NBINS 23 2783 int chain = sc->sc_paprd_curchain; 2784 int x[NBINS + 1], y[NBINS + 1], t[NBINS + 1]; 2785 int b1[NBINS + 1], b2[NBINS + 1], xtilde[NBINS + 1]; 2786 int nsamples, txsum, rxsum, rosum, maxidx; 2787 int order, order5x, order5xrem, order3x, order3xrem, y5, y3; 2788 int icept, G, I, L, M, angle, xnonlin, y2, y4, sumy2, sumy4; 2789 int alpha, beta, scale, Qalpha, Qbeta, Qscale, Qx, Qb1, Qb2; 2790 int tavg, ttilde, maxb1abs, maxb2abs, maxxtildeabs, in; 2791 int tmp, i; 2792 2793 /* Set values at origin. */ 2794 x[0] = y[0] = t[0] = 0; 2795 2796 #define SCALE 32 2797 maxidx = 0; 2798 for (i = 0; i < NBINS; i++) { 2799 nsamples = lo[i] & 0xffff; 2800 /* Skip bins that contain 16 or less samples. */ 2801 if (nsamples <= 16) { 2802 x[i + 1] = y[i + 1] = t[i + 1] = 0; 2803 continue; 2804 } 2805 txsum = (hi[i] & 0x7ff) << 16 | lo[i] >> 16; 2806 rxsum = (lo[i + NBINS] & 0xffff) << 5 | 2807 ((hi[i] >> 11) & 0x1f); 2808 rosum = (hi[i + NBINS] & 0x7ff) << 16 | hi[i + NBINS] >> 16; 2809 /* Sign-extend 27-bit value. */ 2810 rosum = (rosum ^ 0x4000000) - 0x4000000; 2811 2812 txsum *= SCALE; 2813 rxsum *= SCALE; 2814 rosum *= SCALE; 2815 2816 x[i + 1] = ((txsum + nsamples) / nsamples + SCALE) / SCALE; 2817 y[i + 1] = ((rxsum + nsamples) / nsamples + SCALE) / SCALE + 2818 SCALE * maxidx + SCALE / 2; 2819 t[i + 1] = (rosum + nsamples) / nsamples; 2820 maxidx++; 2821 } 2822 #undef SCALE 2823 2824 #define SCALE_LOG 8 2825 #define SCALE (1 << SCALE_LOG) 2826 if (x[6] == x[3]) 2827 return 1; /* Prevent division by 0. */ 2828 G = ((y[6] - y[3]) * SCALE + (x[6] - x[3])) / (x[6] - x[3]); 2829 if (G == 0) 2830 return 1; /* Prevent division by 0. */ 2831 2832 sc->sc_gain1[chain] = G; /* Save low signal gain. */ 2833 2834 /* Find interception point. */ 2835 icept = (G * (x[0] - x[3]) + SCALE) / SCALE + y[3]; 2836 for (i = 0; i <= 3; i++) { 2837 y[i] = i * 32; 2838 x[i] = (y[i] * SCALE + G) / G; 2839 } 2840 for (i = 4; i <= maxidx; i++) 2841 y[i] -= icept; 2842 2843 xnonlin = x[maxidx] - (y[maxidx] * SCALE + G) / G; 2844 order = (xnonlin + y[maxidx]) / y[maxidx]; 2845 if (order == 0) 2846 M = 10; 2847 else if (order == 1) 2848 M = 9; 2849 else 2850 M = 8; 2851 2852 I = (maxidx >= 16) ? 7 : maxidx / 2; 2853 L = maxidx - I; 2854 2855 sumy2 = sumy4 = y2 = y4 = 0; 2856 for (i = 0; i <= L; i++) { 2857 if (y[i + I] == 0) 2858 return 1; /* Prevent division by 0. */ 2859 2860 xnonlin = x[i + I] - ((y[i + I] * SCALE) + G) / G; 2861 xtilde[i] = ((xnonlin << M) + y[i + I]) / y[i + I]; 2862 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2863 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2864 2865 y2 = (y[i + I] * y[i + I] + SCALE * SCALE) / (SCALE * SCALE); 2866 2867 sumy2 += y2; 2868 sumy4 += y2 * y2; 2869 2870 b1[i] = y2 * (L + 1); 2871 b2[i] = y2; 2872 } 2873 for (i = 0; i <= L; i++) { 2874 b1[i] -= sumy2; 2875 b2[i] = sumy4 - sumy2 * b2[i]; 2876 } 2877 2878 maxxtildeabs = maxb1abs = maxb2abs = 0; 2879 for (i = 0; i <= L; i++) { 2880 tmp = abs(xtilde[i]); 2881 if (tmp > maxxtildeabs) 2882 maxxtildeabs = tmp; 2883 2884 tmp = abs(b1[i]); 2885 if (tmp > maxb1abs) 2886 maxb1abs = tmp; 2887 2888 tmp = abs(b2[i]); 2889 if (tmp > maxb2abs) 2890 maxb2abs = tmp; 2891 } 2892 Qx = get_scale(maxxtildeabs); 2893 Qb1 = get_scale(maxb1abs); 2894 Qb2 = get_scale(maxb2abs); 2895 for (i = 0; i <= L; i++) { 2896 xtilde[i] /= 1 << Qx; 2897 b1[i] /= 1 << Qb1; 2898 b2[i] /= 1 << Qb2; 2899 } 2900 2901 alpha = beta = 0; 2902 for (i = 0; i <= L; i++) { 2903 alpha += b1[i] * xtilde[i]; 2904 beta += b2[i] * xtilde[i]; 2905 } 2906 2907 scale = ((y4 / SCALE_LOG) * (L + 1) - 2908 (y2 / SCALE_LOG) * sumy2) * SCALE_LOG; 2909 2910 Qscale = get_scale(abs(scale)); 2911 scale /= 1 << Qscale; 2912 Qalpha = get_scale(abs(alpha)); 2913 alpha /= 1 << Qalpha; 2914 Qbeta = get_scale(abs(beta)); 2915 beta /= 1 << Qbeta; 2916 2917 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale; 2918 order5x = 1 << (order / 5); 2919 order5xrem = 1 << (order % 5); 2920 2921 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale; 2922 order3x = 1 << (order / 3); 2923 order3xrem = 1 << (order % 3); 2924 2925 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2926 tmp = i * 32; 2927 2928 /* Fifth order. */ 2929 y5 = ((beta * tmp) / 64) / order5x; 2930 y5 = (y5 * tmp) / order5x; 2931 y5 = (y5 * tmp) / order5x; 2932 y5 = (y5 * tmp) / order5x; 2933 y5 = (y5 * tmp) / order5x; 2934 y5 = y5 / order5xrem; 2935 2936 /* Third oder. */ 2937 y3 = (alpha * tmp) / order3x; 2938 y3 = (y3 * tmp) / order3x; 2939 y3 = (y3 * tmp) / order3x; 2940 y3 = y3 / order3xrem; 2941 2942 in = y5 + y3 + (SCALE * tmp) / G; 2943 if (i >= 2 && in < sc->sc_pa_in[chain][i - 1]) { 2944 in = sc->sc_pa_in[chain][i - 1] + 2945 (sc->sc_pa_in[chain][i - 1] - 2946 sc->sc_pa_in[chain][i - 2]); 2947 } 2948 if (in > 1400) 2949 in = 1400; 2950 sc->sc_pa_in[chain][i] = in; 2951 } 2952 2953 /* Compute average theta of first 5 bins (linear region). */ 2954 tavg = 0; 2955 for (i = 1; i <= 5; i++) 2956 tavg += t[i]; 2957 tavg /= 5; 2958 for (i = 1; i <= 5; i++) 2959 t[i] = 0; 2960 for (i = 6; i <= maxidx; i++) 2961 t[i] -= tavg; 2962 2963 alpha = beta = 0; 2964 for (i = 0; i <= L; i++) { 2965 ttilde = ((t[i + I] << M) + y[i + I]) / y[i + I]; 2966 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2967 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2968 2969 alpha += b2[i] * ttilde; 2970 beta += b1[i] * ttilde; 2971 } 2972 2973 Qalpha = get_scale(abs(alpha)); 2974 alpha /= 1 << Qalpha; 2975 Qbeta = get_scale(abs(beta)); 2976 beta /= 1 << Qbeta; 2977 2978 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale + 5; 2979 order5x = 1 << (order / 5); 2980 order5xrem = 1 << (order % 5); 2981 2982 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale + 5; 2983 order3x = 1 << (order / 3); 2984 order3xrem = 1 << (order % 3); 2985 2986 for (i = 0; i <= 4; i++) 2987 sc->sc_angle[chain][i] = 0; /* Linear at that range. */ 2988 for (i = 5; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2989 tmp = i * 32; 2990 2991 /* Fifth order. */ 2992 if (beta > 0) 2993 y5 = (((beta * tmp - 64) / 64) - order5x) / order5x; 2994 else 2995 y5 = (((beta * tmp - 64) / 64) + order5x) / order5x; 2996 y5 = (y5 * tmp) / order5x; 2997 y5 = (y5 * tmp) / order5x; 2998 y5 = (y5 * tmp) / order5x; 2999 y5 = (y5 * tmp) / order5x; 3000 y5 = y5 / order5xrem; 3001 3002 /* Third oder. */ 3003 if (beta > 0) /* XXX alpha? */ 3004 y3 = (alpha * tmp - order3x) / order3x; 3005 else 3006 y3 = (alpha * tmp + order3x) / order3x; 3007 y3 = (y3 * tmp) / order3x; 3008 y3 = (y3 * tmp) / order3x; 3009 y3 = y3 / order3xrem; 3010 3011 angle = y5 + y3; 3012 if (angle < -150) 3013 angle = -150; 3014 else if (angle > 150) 3015 angle = 150; 3016 sc->sc_angle[chain][i] = angle; 3017 } 3018 /* Angle for entry 4 is derived from angle for entry 5. */ 3019 sc->sc_angle[chain][4] = (sc->sc_angle[chain][5] + 2) / 2; 3020 3021 return 0; 3022 #undef SCALE 3023 #undef SCALE_LOG 3024 #undef NBINS 3025 } 3026 3027 Static void 3028 ar9003_enable_predistorter(struct athn_softc *sc, int chain) 3029 { 3030 uint32_t reg; 3031 int i; 3032 3033 /* Write digital predistorter lookup table. */ 3034 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 3035 AR_WRITE(sc, AR_PHY_PAPRD_MEM_TAB_B(chain, i), 3036 SM(AR_PHY_PAPRD_PA_IN, sc->sc_pa_in[chain][i]) | 3037 SM(AR_PHY_PAPRD_ANGLE, sc->sc_angle[chain][i])); 3038 } 3039 3040 reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain)); 3041 reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->sc_gain1[chain]); 3042 AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg); 3043 3044 /* Indicate Tx power used for calibration (training signal). */ 3045 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain)); 3046 reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->sc_trainpow); 3047 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg); 3048 3049 /* Enable digital predistorter for this chain. */ 3050 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(chain), 3051 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 3052 AR_WRITE_BARRIER(sc); 3053 } 3054 3055 Static void 3056 ar9003_paprd_enable(struct athn_softc *sc) 3057 { 3058 int i; 3059 3060 /* Enable digital predistorters for all Tx chains. */ 3061 for (i = 0; i < AR9003_MAX_CHAINS; i++) 3062 if (sc->sc_txchainmask & (1 << i)) 3063 ar9003_enable_predistorter(sc, i); 3064 } 3065 3066 /* 3067 * This function is called when our training signal has been sent. 3068 */ 3069 Static void 3070 ar9003_paprd_tx_tone_done(struct athn_softc *sc) 3071 { 3072 uint32_t lo[48], hi[48]; 3073 size_t i; 3074 3075 /* Make sure training is complete. */ 3076 if (!(AR_READ(sc, AR_PHY_PAPRD_TRAINER_STAT1) & 3077 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE)) 3078 return; 3079 3080 /* Read feedback from training signal. */ 3081 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 3082 for (i = 0; i < __arraycount(lo); i++) 3083 lo[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 3084 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 3085 for (i = 0; i < __arraycount(hi); i++) 3086 hi[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 3087 3088 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 3089 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 3090 3091 /* Compute predistortion function based on this feedback. */ 3092 if (ar9003_compute_predistortion(sc, lo, hi) != 0) 3093 return; 3094 3095 /* Get next available Tx chain. */ 3096 while (++sc->sc_paprd_curchain < AR9003_MAX_CHAINS) 3097 if (sc->sc_txchainmask & (1 << sc->sc_paprd_curchain)) 3098 break; 3099 if (sc->sc_paprd_curchain == AR9003_MAX_CHAINS) { 3100 /* All Tx chains measured; enable digital predistortion. */ 3101 ar9003_paprd_enable(sc); 3102 } 3103 else /* Measure next Tx chain. */ 3104 ar9003_paprd_tx_tone(sc); 3105 } 3106 3107 PUBLIC void 3108 ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT]) 3109 { 3110 3111 /* Make sure forced gain is disabled. */ 3112 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, 0); 3113 3114 AR_WRITE(sc, AR_PHY_PWRTX_RATE1, 3115 (power[ATHN_POWER_OFDM18 ] & 0x3f) << 24 | 3116 (power[ATHN_POWER_OFDM12 ] & 0x3f) << 16 | 3117 (power[ATHN_POWER_OFDM9 ] & 0x3f) << 8 | 3118 (power[ATHN_POWER_OFDM6 ] & 0x3f)); 3119 AR_WRITE(sc, AR_PHY_PWRTX_RATE2, 3120 (power[ATHN_POWER_OFDM54 ] & 0x3f) << 24 | 3121 (power[ATHN_POWER_OFDM48 ] & 0x3f) << 16 | 3122 (power[ATHN_POWER_OFDM36 ] & 0x3f) << 8 | 3123 (power[ATHN_POWER_OFDM24 ] & 0x3f)); 3124 AR_WRITE(sc, AR_PHY_PWRTX_RATE3, 3125 (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 | 3126 (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 | 3127 /* NB: No eXtended Range for AR9003. */ 3128 (power[ATHN_POWER_CCK1_LP ] & 0x3f)); 3129 AR_WRITE(sc, AR_PHY_PWRTX_RATE4, 3130 (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 | 3131 (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 | 3132 (power[ATHN_POWER_CCK55_SP] & 0x3f) << 8 | 3133 (power[ATHN_POWER_CCK55_LP] & 0x3f)); 3134 /* 3135 * NB: AR_PHY_PWRTX_RATE5 needs to be written even if HT is disabled 3136 * because it is read by PA predistortion functions. 3137 */ 3138 AR_WRITE(sc, AR_PHY_PWRTX_RATE5, 3139 (power[ATHN_POWER_HT20( 5)] & 0x3f) << 24 | 3140 (power[ATHN_POWER_HT20( 4)] & 0x3f) << 16 | 3141 (power[ATHN_POWER_HT20( 1)] & 0x3f) << 8 | 3142 (power[ATHN_POWER_HT20( 0)] & 0x3f)); 3143 #ifndef IEEE80211_NO_HT 3144 AR_WRITE(sc, AR_PHY_PWRTX_RATE6, 3145 (power[ATHN_POWER_HT20(13)] & 0x3f) << 24 | 3146 (power[ATHN_POWER_HT20(12)] & 0x3f) << 16 | 3147 (power[ATHN_POWER_HT20( 7)] & 0x3f) << 8 | 3148 (power[ATHN_POWER_HT20( 6)] & 0x3f)); 3149 AR_WRITE(sc, AR_PHY_PWRTX_RATE7, 3150 (power[ATHN_POWER_HT40( 5)] & 0x3f) << 24 | 3151 (power[ATHN_POWER_HT40( 4)] & 0x3f) << 16 | 3152 (power[ATHN_POWER_HT40( 1)] & 0x3f) << 8 | 3153 (power[ATHN_POWER_HT40( 0)] & 0x3f)); 3154 AR_WRITE(sc, AR_PHY_PWRTX_RATE8, 3155 (power[ATHN_POWER_HT40(13)] & 0x3f) << 24 | 3156 (power[ATHN_POWER_HT40(12)] & 0x3f) << 16 | 3157 (power[ATHN_POWER_HT40( 7)] & 0x3f) << 8 | 3158 (power[ATHN_POWER_HT40( 6)] & 0x3f)); 3159 AR_WRITE(sc, AR_PHY_PWRTX_RATE10, 3160 (power[ATHN_POWER_HT20(21)] & 0x3f) << 24 | 3161 (power[ATHN_POWER_HT20(20)] & 0x3f) << 16 | 3162 (power[ATHN_POWER_HT20(15)] & 0x3f) << 8 | 3163 (power[ATHN_POWER_HT20(14)] & 0x3f)); 3164 AR_WRITE(sc, AR_PHY_PWRTX_RATE11, 3165 (power[ATHN_POWER_HT40(23)] & 0x3f) << 24 | 3166 (power[ATHN_POWER_HT40(22)] & 0x3f) << 16 | 3167 (power[ATHN_POWER_HT20(23)] & 0x3f) << 8 | 3168 (power[ATHN_POWER_HT20(22)] & 0x3f)); 3169 AR_WRITE(sc, AR_PHY_PWRTX_RATE12, 3170 (power[ATHN_POWER_HT40(21)] & 0x3f) << 24 | 3171 (power[ATHN_POWER_HT40(20)] & 0x3f) << 16 | 3172 (power[ATHN_POWER_HT40(15)] & 0x3f) << 8 | 3173 (power[ATHN_POWER_HT40(14)] & 0x3f)); 3174 #endif 3175 AR_WRITE_BARRIER(sc); 3176 } 3177 3178 Static void 3179 ar9003_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3180 { 3181 #define X(x) ((uint32_t)(x) << 2) 3182 const struct athn_gain *prog = sc->sc_rx_gain; 3183 const uint32_t *pvals; 3184 int i; 3185 3186 if (IEEE80211_IS_CHAN_2GHZ(c)) 3187 pvals = prog->vals_2g; 3188 else 3189 pvals = prog->vals_5g; 3190 for (i = 0; i < prog->nregs; i++) 3191 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3192 AR_WRITE_BARRIER(sc); 3193 #undef X 3194 } 3195 3196 Static void 3197 ar9003_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3198 { 3199 #define X(x) ((uint32_t)(x) << 2) 3200 const struct athn_gain *prog = sc->sc_tx_gain; 3201 const uint32_t *pvals; 3202 int i; 3203 3204 if (IEEE80211_IS_CHAN_2GHZ(c)) 3205 pvals = prog->vals_2g; 3206 else 3207 pvals = prog->vals_5g; 3208 for (i = 0; i < prog->nregs; i++) 3209 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3210 AR_WRITE_BARRIER(sc); 3211 #undef X 3212 } 3213 3214 Static void 3215 ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c, 3216 struct ieee80211_channel *extc) 3217 { 3218 #define X(x) ((uint32_t)(x) << 2) 3219 struct athn_ops *ops = &sc->sc_ops; 3220 const struct athn_ini *ini = sc->sc_ini; 3221 const uint32_t *pvals; 3222 uint32_t reg; 3223 int i; 3224 3225 /* 3226 * The common init values include the pre and core phases for the 3227 * SoC, MAC, BB and Radio subsystems. 3228 */ 3229 DPRINTFN(DBG_INIT, sc, "writing pre and core init vals\n"); 3230 for (i = 0; i < ini->ncmregs; i++) { 3231 AR_WRITE(sc, X(ini->cmregs[i]), ini->cmvals[i]); 3232 if (AR_IS_ANALOG_REG(X(ini->cmregs[i]))) 3233 DELAY(100); 3234 if ((i & 0x1f) == 0) 3235 DELAY(1); 3236 } 3237 3238 /* 3239 * The modal init values include the post phase for the SoC, MAC, 3240 * BB and Radio subsystems. 3241 */ 3242 #ifndef IEEE80211_NO_HT 3243 if (extc != NULL) { 3244 if (IEEE80211_IS_CHAN_2GHZ(c)) 3245 pvals = ini->vals_2g40; 3246 else 3247 pvals = ini->vals_5g40; 3248 } 3249 else 3250 #endif 3251 { 3252 if (IEEE80211_IS_CHAN_2GHZ(c)) 3253 pvals = ini->vals_2g20; 3254 else 3255 pvals = ini->vals_5g20; 3256 } 3257 DPRINTFN(DBG_INIT, sc, "writing post init vals\n"); 3258 for (i = 0; i < ini->nregs; i++) { 3259 AR_WRITE(sc, X(ini->regs[i]), pvals[i]); 3260 if (AR_IS_ANALOG_REG(X(ini->regs[i]))) 3261 DELAY(100); 3262 if ((i & 0x1f) == 0) 3263 DELAY(1); 3264 } 3265 3266 if (sc->sc_rx_gain != NULL) 3267 ar9003_reset_rx_gain(sc, c); 3268 if (sc->sc_tx_gain != NULL) 3269 ar9003_reset_tx_gain(sc, c); 3270 3271 if (IEEE80211_IS_CHAN_5GHZ(c) && 3272 (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 3273 /* Update modal values for fast PLL clock. */ 3274 #ifndef IEEE80211_NO_HT 3275 if (extc != NULL) 3276 pvals = ini->fastvals_5g40; 3277 else 3278 #endif 3279 pvals = ini->fastvals_5g20; 3280 DPRINTFN(DBG_INIT, sc, "writing fast pll clock init vals\n"); 3281 for (i = 0; i < ini->nfastregs; i++) { 3282 AR_WRITE(sc, X(ini->fastregs[i]), pvals[i]); 3283 if (AR_IS_ANALOG_REG(X(ini->fastregs[i]))) 3284 DELAY(100); 3285 if ((i & 0x1f) == 0) 3286 DELAY(1); 3287 } 3288 } 3289 3290 /* 3291 * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted 3292 * descriptor status. 3293 */ 3294 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 3295 3296 reg = AR_READ(sc, AR_PCU_MISC_MODE2); 3297 reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE; 3298 reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX; 3299 reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP; 3300 AR_WRITE(sc, AR_PCU_MISC_MODE2, reg); 3301 AR_WRITE_BARRIER(sc); 3302 3303 ar9003_set_phy(sc, c, extc); 3304 ar9003_init_chains(sc); 3305 3306 ops->set_txpower(sc, c, extc); 3307 #undef X 3308 } 3309 3310 PUBLIC void 3311 ar9003_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3312 uint8_t ctl, const uint8_t *fbins, 3313 const struct ar_cal_target_power_leg *tgt, int nchans, uint8_t tpow[4]) 3314 { 3315 uint8_t fbin; 3316 int i, delta, lo, hi; 3317 3318 lo = hi = -1; 3319 fbin = athn_chan2fbin(c); 3320 for (i = 0; i < nchans; i++) { 3321 delta = fbin - fbins[i]; 3322 /* Find the largest sample that is <= our frequency. */ 3323 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3324 lo = i; 3325 /* Find the smallest sample that is >= our frequency. */ 3326 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3327 hi = i; 3328 } 3329 if (lo == -1) 3330 lo = hi; 3331 else if (hi == -1) 3332 hi = lo; 3333 /* Interpolate values. */ 3334 for (i = 0; i < 4; i++) { 3335 tpow[i] = athn_interpolate(fbin, 3336 fbins[lo], tgt[lo].tPow2x[i], 3337 fbins[hi], tgt[hi].tPow2x[i]); 3338 } 3339 /* XXX Apply conformance test limit. */ 3340 } 3341 3342 PUBLIC void 3343 ar9003_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3344 uint8_t ctl, const uint8_t *fbins, 3345 const struct ar_cal_target_power_ht *tgt, int nchans, uint8_t tpow[14]) 3346 { 3347 uint8_t fbin; 3348 int i, delta, lo, hi; 3349 3350 lo = hi = -1; 3351 fbin = athn_chan2fbin(c); 3352 for (i = 0; i < nchans; i++) { 3353 delta = fbin - fbins[i]; 3354 /* Find the largest sample that is <= our frequency. */ 3355 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3356 lo = i; 3357 /* Find the smallest sample that is >= our frequency. */ 3358 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3359 hi = i; 3360 } 3361 if (lo == -1) 3362 lo = hi; 3363 else if (hi == -1) 3364 hi = lo; 3365 /* Interpolate values. */ 3366 for (i = 0; i < 14; i++) { 3367 tpow[i] = athn_interpolate(fbin, 3368 fbins[lo], tgt[lo].tPow2x[i], 3369 fbins[hi], tgt[hi].tPow2x[i]); 3370 } 3371 /* XXX Apply conformance test limit. */ 3372 } 3373 3374 /* 3375 * Adaptive noise immunity. 3376 */ 3377 Static void 3378 ar9003_set_noise_immunity_level(struct athn_softc *sc, int level) 3379 { 3380 int high = level == 4; 3381 uint32_t reg; 3382 3383 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 3384 reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55); 3385 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 3386 3387 reg = AR_READ(sc, AR_PHY_AGC); 3388 reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64); 3389 reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14); 3390 AR_WRITE(sc, AR_PHY_AGC, reg); 3391 3392 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3393 reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78); 3394 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3395 AR_WRITE_BARRIER(sc); 3396 } 3397 3398 Static void 3399 ar9003_enable_ofdm_weak_signal(struct athn_softc *sc) 3400 { 3401 uint32_t reg; 3402 3403 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3404 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50); 3405 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40); 3406 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48); 3407 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3408 3409 reg = AR_READ(sc, AR_PHY_SFCORR); 3410 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77); 3411 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64); 3412 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16); 3413 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3414 3415 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3416 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50); 3417 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40); 3418 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77); 3419 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64); 3420 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3421 3422 AR_SETBITS(sc, AR_PHY_SFCORR_LOW, 3423 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3424 AR_WRITE_BARRIER(sc); 3425 } 3426 3427 Static void 3428 ar9003_disable_ofdm_weak_signal(struct athn_softc *sc) 3429 { 3430 uint32_t reg; 3431 3432 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3433 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127); 3434 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127); 3435 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63); 3436 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3437 3438 reg = AR_READ(sc, AR_PHY_SFCORR); 3439 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127); 3440 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127); 3441 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31); 3442 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3443 3444 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3445 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127); 3446 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127); 3447 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127); 3448 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127); 3449 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3450 3451 AR_CLRBITS(sc, AR_PHY_SFCORR_LOW, 3452 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3453 AR_WRITE_BARRIER(sc); 3454 } 3455 3456 Static void 3457 ar9003_set_cck_weak_signal(struct athn_softc *sc, int high) 3458 { 3459 uint32_t reg; 3460 3461 reg = AR_READ(sc, AR_PHY_CCK_DETECT); 3462 reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8); 3463 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); 3464 AR_WRITE_BARRIER(sc); 3465 } 3466 3467 Static void 3468 ar9003_set_firstep_level(struct athn_softc *sc, int level) 3469 { 3470 uint32_t reg; 3471 3472 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3473 reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4); 3474 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3475 AR_WRITE_BARRIER(sc); 3476 } 3477 3478 Static void 3479 ar9003_set_spur_immunity_level(struct athn_softc *sc, int level) 3480 { 3481 uint32_t reg; 3482 3483 reg = AR_READ(sc, AR_PHY_TIMING5); 3484 reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2); 3485 AR_WRITE(sc, AR_PHY_TIMING5, reg); 3486 AR_WRITE_BARRIER(sc); 3487 } 3488
Indexes created Wed Oct 22 00:09:40 GMT 2025