1 /* $NetBSD: bt462reg.h,v 1.1 2010/06/24 03:30:36 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * register definitions for the Bt461/Bt462 RAMDAC 31 * 32 * There are four registers, how exactly to access them depends on the host so 33 * we don't provide constants for them. All registers are 8 bit wide: 34 * - register 0 provides the lower 8 index bits 35 * - register 1 provides the upper 2 index bits 36 * - register 2 accesses the alternate colour map ( 256 entries ), overlay 37 * colour map ( 32 enttries ) and control registers 38 * - register 3 accesses the main colour map ( 1024 entries ) 39 */ 40 41 #ifndef BT462REG_H 42 #define BT462REG_H 43 44 /* offsets for register 2 */ 45 #define BT462_ALT_CMAP 0x0000 46 #define BT462_OVL_CMAP 0x0100 47 #define BT462_ID 0x0200 48 #define ID_BT461 0x4d 49 #define ID_BT462 0x4c 50 51 #define BT462_CMD_0 0x0201 52 #define BT462_C0_BLINK_16_48 0x00 53 #define BT462_C0_BLINK_16_16 0x04 54 #define BT462_C0_BLINK_32_32 0x08 55 #define BT462_C0_BLINK_64_64 0x0c 56 #define BT462_C0_ALT_ENABLE 0x10 57 #define BT462_C0_OVL_OPAQUE 0x20 /* use ovl 0, not cmap */ 58 #define BT462_C0_MULT_3_1 0x00 59 #define BT462_C0_MULT_4_1 0x40 60 #define BT462_C0_MULT_5_1 0xc0 61 62 #define BT462_CMD_1 0x0202 63 #define BT462_C1_PAN_0 0x00 64 #define BT462_C1_PAN_1 0x20 65 #define BT462_C1_PAN_2 0x40 66 #define BT462_C1_PAN_3 0x80 67 #define BT462_C1_PAN_4 0xa0 68 69 #define BT462_CMD_2 0x0203 70 #define BT462_C2_TEST_ENABLE 0x01 71 #define BT462_C2_UNDERLAY_EN 0x04 /* Bt462 only */ 72 #define BT462_C2_PLL_USE_BLANK 0x08 /* SYNC otherwise */ 73 #define BT462_C2_LOAD_ALWAYS 0x00 74 #define BT462_C2_LOAD_ON_RED 0x10 75 #define BT462_C2_LOAD_ON_GREEN 0x20 76 #define BT462_C2_LOAD_ON_BLUE 0x30 77 #define BT462_C2_PEDESTAL_EN 0x40 78 #define BT462_C2_SYNC_ENABLE 0x80 79 80 #define BT462_PIXEL_READ_MSK_L 0x0204 81 #define BT462_PIXEL_READ_MSK_H 0x0205 82 #define BT462_PIXEL_BLNK_MSK_L 0x0206 83 #define BT462_PIXEL_BLNK_MSK_H 0x0207 84 #define BT462_OVL_READ_MSK 0x0208 85 #define BT462_OVL_BLNK_MSK 0x0209 86 #define BT462_TEST 0x020c 87 88 #endif /* BT462REG_H */ 89
Indexes created Sun Sep 21 20:09:37 GMT 2025