1 /* $NetBSD: bt463reg.h,v 1.2 2008/04/28 20:23:49 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Register definitions for the Brooktree Bt463 135MHz Monolithic 35 * CMOS TrueVu RAMDAC. 36 */ 37 38 /* 39 * Directly-accessible registers. Note the address register is 40 * auto-incrementing. 41 */ 42 #define BT463_REG_ADDR_LOW 0x00 /* C1,C0 == 0,0 */ 43 #define BT463_REG_ADDR_HIGH 0x01 /* C1,C0 == 0,1 */ 44 #define BT463_REG_IREG_DATA 0x02 /* C1,C0 == 1,0 */ 45 #define BT463_REG_CMAP_DATA 0x03 /* C1,C0 == 1,1 */ 46 47 #define BT463_REG_MAX BT463_REG_CMAP_DATA 48 49 /* 50 * All internal register access to the Bt463 is done indirectly via the 51 * Address Register (mapped into the host bus in a device-specific 52 * fashion). The following register definitions are in terms of 53 * their address register address values. 54 */ 55 56 /* C1,C0 must be 1,0 */ 57 #define BT463_IREG_CURSOR_COLOR_0 0x0100 /* 3 r/w cycles */ 58 #define BT463_IREG_CURSOR_COLOR_1 0x0101 /* 3 r/w cycles */ 59 #define BT463_IREG_ID 0x0200 60 #define BT463_IREG_COMMAND_0 0x0201 61 #define BT463_IREG_COMMAND_1 0x0202 62 #define BT463_IREG_COMMAND_2 0x0203 63 #define BT463_IREG_READ_MASK_P0_P7 0x0205 64 #define BT463_IREG_READ_MASK_P8_P15 0x0206 65 #define BT463_IREG_READ_MASK_P16_P23 0x0207 66 #define BT463_IREG_READ_MASK_P24_P27 0x0208 67 #define BT463_IREG_BLINK_MASK_P0_P7 0x0209 68 #define BT463_IREG_BLINK_MASK_P8_P15 0x020a 69 #define BT463_IREG_BLINK_MASK_P16_P23 0x020b 70 #define BT463_IREG_BLINK_MASK_P24_P27 0x020c 71 #define BT463_IREG_TEST 0x020d 72 #define BT463_IREG_INPUT_SIG 0x020e /* 2 of 3 r/w cycles */ 73 #define BT463_IREG_OUTPUT_SIG 0x020f /* 3 r/w cycles */ 74 #define BT463_IREG_REVISION 0x0220 75 #define BT463_IREG_WINDOW_TYPE_TABLE 0x0300 /* 3 r/w cycles */ 76 77 #define BT463_NWTYPE_ENTRIES 0x10 /* 16 window type entries */ 78 79 /* C1,C0 must be 1,1 */ 80 #define BT463_IREG_CPALETTE_RAM 0x0000 /* 3 r/w cycles */ 81 82 #define BT463_NCMAP_ENTRIES 0x210 /* 528 CMAP entries */ 83
Indexes created Sat Sep 20 22:09:52 GMT 2025