1 /* $NetBSD: clmpccreg.h,v 1.4 2008/04/28 20:23:49 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Register definitions for the Cirrus Logic CD2400/CD2401 34 * Four Channel Multi-Protocol Communications Controller. 35 * 36 * The values defined here are based on the August 1993 data book. 37 * At the present time, this driver supports non-DMA async. mode only. 38 */ 39 40 #ifndef __clmpccreg_h 41 #define __clmpccreg_h 42 43 /* 44 * Register offsets depend on the level on the chip's BYTESWAP pin. 45 * When BYTESWAP is low, Motorola byte alignment is in effect. 46 * Otherwise, Intel byte alignment is in effect. 47 * The values given here assume BYTESWAP is low. See 'sc_byteswap' 48 * <dev/ic/clmpccvar.h>. 49 */ 50 51 /* Number of bytes of FIFO (Rx & Tx) */ 52 #define CLMPCC_FIFO_DEPTH 16 53 54 /* Global Registers */ 55 #define CLMPCC_REG_GFRCR 0x81 /* Global Firmware Revision Code Register */ 56 #define CLMPCC_REG_CAR 0xee /* Channel Access Register */ 57 58 /* Option Registers */ 59 #define CLMPCC_REG_CMR 0x1b /* Channel Mode Register */ 60 #define CLMPCC_REG_COR1 0x10 /* Channel Option Register #1 */ 61 #define CLMPCC_REG_COR2 0x17 /* Channel Option Register #2 */ 62 #define CLMPCC_REG_COR3 0x16 /* Channel Option Register #3 */ 63 #define CLMPCC_REG_COR4 0x15 /* Channel Option Register #4 */ 64 #define CLMPCC_REG_COR5 0x14 /* Channel Option Register #5 */ 65 #define CLMPCC_REG_COR6 0x18 /* Channel Option Register #6 */ 66 #define CLMPCC_REG_COR7 0x07 /* Channel Option Register #7 */ 67 #define CLMPCC_REG_SCHR1 0x1f /* Special Character Register #1 */ 68 #define CLMPCC_REG_SCHR2 0x1e /* Special Character Register #2 */ 69 #define CLMPCC_REG_SCHR3 0x1d /* Special Character Register #3 */ 70 #define CLMPCC_REG_SCHR4 0x1c /* Special Character Register #4 */ 71 #define CLMPCC_REG_SCRl 0x23 /* Special Character Range (low) */ 72 #define CLMPCC_REG_SCRh 0x22 /* Special Character Range (high) */ 73 #define CLMPCC_REG_LNXT 0x2e /* LNext Character */ 74 #define CLMPCC_REG_RFAR1 0x1f /* Receive Frame Address Register #1 */ 75 #define CLMPCC_REG_RFAR2 0x1e /* Receive Frame Address Register #2 */ 76 #define CLMPCC_REG_RFAR3 0x1d /* Receive Frame Address Register #3 */ 77 #define CLMPCC_REG_RFAR4 0x1c /* Receive Frame Address Register #4 */ 78 #define CLMPCC_REG_CPSR 0xd6 /* CRC Polynomial Select Register */ 79 80 /* Bit Rate and Clock Option Registers */ 81 #define CLMPCC_REG_RBPR 0xcb /* Receive Baud Rate Period Register */ 82 #define CLMPCC_REG_RCOR 0xc8 /* Receive Clock Options Register */ 83 #define CLMPCC_REG_TBPR 0xc3 /* Transmit Baud Rate Period Register */ 84 #define CLMPCC_REG_TCOR 0xc0 /* Transmit Clock Options Register */ 85 86 /* Channel Command and Status Registers */ 87 #define CLMPCC_REG_CCR 0x13 /* Channel Command Register */ 88 #define CLMPCC_REG_STCR 0x12 /* Special Transmit Command Register */ 89 #define CLMPCC_REG_CSR 0x1a /* Channel Status Register */ 90 #define CLMPCC_REG_MSVR 0xde /* Modem Signal Value Register */ 91 #define CLMPCC_REG_MSVR_RTS 0xde /* Modem Signal Value Register (RTS) */ 92 #define CLMPCC_REG_MSVR_DTR 0xdf /* Modem Signal Value Register (DTR) */ 93 94 /* Interrupt Registers */ 95 #define CLMPCC_REG_LIVR 0x09 /* Local Interrupt Vector Register */ 96 #define CLMPCC_REG_IER 0x11 /* Interrupt Enable Register */ 97 #define CLMPCC_REG_LICR 0x26 /* Local Interrupting Channel Register */ 98 #define CLMPCC_REG_STK 0xe2 /* Stack Register */ 99 100 /* Receive Interrupt Registers */ 101 #define CLMPCC_REG_RPILR 0xe1 /* Receive Priority Interrupt Level Reg */ 102 #define CLMPCC_REG_RIR 0xed /* Receive Interrupt Register */ 103 #define CLMPCC_REG_RISR 0x88 /* Receive Interrupt Status Reg (16-bits) */ 104 #define CLMPCC_REG_RISRl 0x89 /* Receive Interrupt Status Reg (low) */ 105 #define CLMPCC_REG_RISRh 0x88 /* Receive Interrupt Status Reg (high) */ 106 #define CLMPCC_REG_RFOC 0x30 /* Receive FIFO Output Count */ 107 #define CLMPCC_REG_RDR 0xf8 /* Receive Data Register */ 108 #define CLMPCC_REG_REOIR 0x84 /* Receive End of Interrupt Register */ 109 110 /* Transmit Interrupt Registers */ 111 #define CLMPCC_REG_TPILR 0xe0 /* Transmit Priority Interrupt Level Reg */ 112 #define CLMPCC_REG_TIR 0xec /* Transmit Interrupt Register */ 113 #define CLMPCC_REG_TISR 0x8a /* Transmit Interrupt Status Register */ 114 #define CLMPCC_REG_TFTC 0x80 /* Transmit FIFO Transfer Count */ 115 #define CLMPCC_REG_TDR 0xf8 /* Transmit Data Register */ 116 #define CLMPCC_REG_TEOIR 0x85 /* Transmit End of Interrupt Register */ 117 118 /* Modem Interrupt Registers */ 119 #define CLMPCC_REG_MPILR 0xe3 /* Modem Priority Interrupt Level Reg */ 120 #define CLMPCC_REG_MIR 0xef /* Modem Interrupt Register */ 121 #define CLMPCC_REG_MISR 0x8b /* Modem (/Timer) Interrupt Status Reg */ 122 #define CLMPCC_REG_MEOIR 0x86 /* Modem End of Interrupt Register */ 123 124 /* DMA Registers */ 125 #define CLMPCC_REG_DMR 0xf6 /* DMA Mode Register (write only) */ 126 #define CLMPCC_REG_BERCNT 0x8e /* Bus Error Retry Count */ 127 #define CLMPCC_REG_DMABSTS 0x19 /* DMA Buffer Status */ 128 129 /* DMA Receive Registers */ 130 #define CLMPCC_REG_ARBADRL 0x42 /* A Receive Buffer Address Lower (word) */ 131 #define CLMPCC_REG_ARBADRU 0x40 /* A Receive Buffer Address Upper (word) */ 132 #define CLMPCC_REG_BRBADRL 0x46 /* B Receive Buffer Address Lower (word) */ 133 #define CLMPCC_REG_BRBADRU 0x44 /* B Receive Buffer Address Upper (16bit) */ 134 #define CLMPCC_REG_ARBCNT 0x4a /* A Receive Buffer Byte Count (word) */ 135 #define CLMPCC_REG_BRBCNT 0x48 /* B Receive Buffer Byte Count (word) */ 136 #define CLMPCC_REG_ARBSTS 0x4f /* A Receive Buffer Status */ 137 #define CLMPCC_REG_BRBSTS 0x4e /* B Receive Buffer Status */ 138 #define CLMPCC_REG_RCBADRL 0x3e /* Receive Current Buff Addr Lower (word) */ 139 #define CLMPCC_REG_RCBADRU 0x3c /* Receive Current Buff Addr Upper (word) */ 140 141 /* DMA Transmit Registers */ 142 #define CLMPCC_REG_ATBADRL 0x52 /* A Transmit Buffer Address Lower (word) */ 143 #define CLMPCC_REG_ATBADRU 0x50 /* A Transmit Buffer Address Upper (word) */ 144 #define CLMPCC_REG_BTBADRL 0x56 /* B Transmit Buffer Address Lower (word) */ 145 #define CLMPCC_REG_BTBADRU 0x54 /* B Transmit Buffer Address Upper (word) */ 146 #define CLMPCC_REG_ATBCNT 0x5a /* A Transmit Buffer Byte Count (word) */ 147 #define CLMPCC_REG_BTBCNT 0x58 /* B Transmit Buffer Byte Count (word) */ 148 #define CLMPCC_REG_ATBSTS 0x5f /* A Transmit Buffer Status */ 149 #define CLMPCC_REG_BTBSTS 0x5e /* B Transmit Buffer Status */ 150 #define CLMPCC_REG_TCBADRL 0x3a /* Transmit Current Buf Addr Lower (word) */ 151 #define CLMPCC_REG_TCBADRU 0x38 /* Transmit Current Buf Addr Upper (word) */ 152 153 /* Timer Registers */ 154 #define CLMPCC_REG_TPR 0xda /* Timer Period Register */ 155 #define CLMPCC_REG_RTPR 0x24 /* Receive Timeout Period Register (word) */ 156 #define CLMPCC_REG_RTPRl 0x25 /* Receive Timeout Period Register (low) */ 157 #define CLMPCC_REG_RTPRh 0x24 /* Receive Timeout Period Register (high) */ 158 #define CLMPCC_REG_GT1 0x2a /* General Timer 1 (word) */ 159 #define CLMPCC_REG_GT1l 0x2b /* General Timer 1 (low) */ 160 #define CLMPCC_REG_GT1h 0x2a /* General Timer 1 (high) */ 161 #define CLMPCC_REG_GT2 0x29 /* General Timer 2 */ 162 #define CLMPCC_REG_TTR 0x29 /* Transmit Timer Register */ 163 164 165 /* Channel Access Register */ 166 #define CLMPCC_CAR_MASK 0x03 /* Channel bit mask */ 167 168 /* Channel Mode Register */ 169 #define CLMPCC_CMR_RX_INT (0 << 7) /* Rx using interrupts */ 170 #define CLMPCC_CMR_RX_DMA (1 << 7) /* Rx using DMA */ 171 #define CLMPCC_CMR_TX_INT (0 << 6) /* Tx using interrupts */ 172 #define CLMPCC_CMR_TX_DMA (1 << 6) /* Tx using DMA */ 173 #define CLMPCC_CMR_HDLC 0x00 /* Select HDLC mode */ 174 #define CLMPCC_CMR_BISYNC 0x01 /* Select Bisync mode */ 175 #define CLMPCC_CMR_ASYNC 0x02 /* Select async mode */ 176 #define CLMPCC_CMR_X21 0x03 /* Select X.21 mode */ 177 178 /* Channel Option Register #1 (Async options) */ 179 #define CLMPCC_COR1_EVEN_PARITY (0 << 7) /* Even parity */ 180 #define CLMPCC_COR1_ODD_PARITY (1 << 7) /* Odd parity */ 181 #define CLMPCC_COR1_NO_PARITY (0 << 5) /* No parity */ 182 #define CLMPCC_COR1_FORCE_PAR (1 << 5) /* Force parity */ 183 #define CLMPCC_COR1_NORM_PARITY (2 << 5) /* Normal parity */ 184 #define CLMPCC_COR1_CHECK_PAR (0 << 4) /* Check parity */ 185 #define CLMPCC_COR1_IGNORE_PAR (1 << 4) /* Ignore parity */ 186 #define CLMPCC_COR1_CHAR_5BITS 0x04 /* 5 bits per character */ 187 #define CLMPCC_COR1_CHAR_6BITS 0x05 /* 6 bits per character */ 188 #define CLMPCC_COR1_CHAR_7BITS 0x06 /* 7 bits per character */ 189 #define CLMPCC_COR1_CHAR_8BITS 0x07 /* 8 bits per character */ 190 191 /* Channel Option Register #2 (Async options) */ 192 #define CLMPCC_COR2_IXM (1 << 7) /* Implied XON mode */ 193 #define CLMPCC_COR2_TxIBE (1 << 6) /* Transmit In-Band Flow Control */ 194 #define CLMPCC_COR2_ETC (1 << 5) /* Embedded Tx Command Enable */ 195 #define CLMPCC_COR2_RLM (1 << 3) /* Remote Loopback Mode */ 196 #define CLMPCC_COR2_RtsAO (1 << 2) /* RTS Automatic Output Enable */ 197 #define CLMPCC_COR2_CtsAE (1 << 1) /* CTS Automatic Enable */ 198 #define CLMPCC_COR2_DsrAE (1 << 1) /* DSR Automatic Enable */ 199 200 /* Embedded transmit commands */ 201 #define CLMPCC_ETC_MAGIC 0x00 /* Introduces a command */ 202 #define CLMPCC_ETC_SEND_BREAK 0x81 /* Send a BREAK character */ 203 #define CLMPCC_ETC_DELAY 0x82 /* Insert a delay */ 204 #define CLMPCC_ETC_STOP_BREAK 0x83 /* Stop sending BREAK */ 205 206 /* Channel Option Register #3 (Async options) */ 207 #define CLMPCC_COR3_ESCDE (1 << 7) /* Ext Special Char Detect Enab */ 208 #define CLMPCC_COR3_RngDE (1 << 6) /* Range Detect Enable */ 209 #define CLMPCC_COR3_FCT (1 << 5) /* Flow Ctrl Transparency Mode */ 210 #define CLMPCC_COR3_SCDE (1 << 4) /* Special Character Detection */ 211 #define CLMPCC_COR3_SpIstp (1 << 3) /* Special Character I Strip */ 212 #define CLMPCC_COR3_STOP_1 0x02 /* 1 Stop Bit */ 213 #define CLMPCC_COR3_STOP_1_5 0x03 /* 1.5 Stop Bits */ 214 #define CLMPCC_COR3_STOP_2 0x04 /* 2 Stop Bits */ 215 216 /* Channel Option Register #4 */ 217 #define CLMPCC_COR4_DSRzd (1 << 7) /* Detect 1->0 transition on DSR */ 218 #define CLMPCC_COR4_CDzd (1 << 6) /* Detect 1->0 transition on CD */ 219 #define CLMPCC_COR4_CTSzd (1 << 5) /* Detect 1->0 transition on CTS */ 220 #define CLMPCC_COR4_FIFO_MASK 0x0f /* FIFO Threshold bits */ 221 #define CLMPCC_COR4_FIFO_LOW 1 222 #define CLMPCC_COR4_FIFO_MED 4 223 #define CLMPCC_COR4_FIFO_HIGH 8 224 225 /* Channel Option Register #5 */ 226 #define CLMPCC_COR5_DSRod (1 << 7) /* Detect 0->1 transition on DSR */ 227 #define CLMPCC_COR5_CDod (1 << 6) /* Detect 0->1 transition on CD */ 228 #define CLMPCC_COR5_CTSod (1 << 5) /* Detect 0->1 transition on CTS */ 229 #define CLMPCC_COR5_FLOW_MASK 0x0f /* Rx Flow Control FIFO Threshold */ 230 #define CLMPCC_COR5_FLOW_NORM 8 231 232 /* Channel Option Register #6 (Async options) */ 233 #define CLMPCC_COR6_RX_CRNL 0x00 /* No special action on CR or NL */ 234 #define CLMPCC_COR6_BRK_EXCEPT (0 << 3) /* Exception interrupt on BREAK */ 235 #define CLMPCC_COR6_BRK_2_NULL (1 << 3) /* Translate BREAK to NULL char */ 236 #define CLMPCC_COR6_BRK_DISCARD (3 << 3) /* Discard BREAK characters */ 237 #define CLMPCC_COR6_PF_EXCEPT 0x00 /* Exception irq on parity/frame */ 238 #define CLMPCC_COR6_PF_2_NULL 0x01 /* Translate parity/frame to NULL */ 239 #define CLMPCC_COR6_PF_IGNORE 0x02 /* Ignore error */ 240 #define CLMPCC_COR6_PF_DISCARD 0x03 /* Discard character */ 241 #define CLMPCC_COR6_PF_TRANS 0x05 /* Translate to FF NULL + char */ 242 243 /* Channel Option Register #7 (Async options) */ 244 #define CLMPCC_COR7_ISTRIP (1 << 7) /* Strip MSB */ 245 #define CLMPCC_COR7_LNE (1 << 6) /* Enable LNext Option */ 246 #define CLMPCC_COR7_FCERR (1 << 5) /* Flow Control on Error Char */ 247 #define CLMPCC_COR7_TX_CRNL 0x00 /* No special action on NL or CR */ 248 249 /* Receive Clock Options Register */ 250 #define CLMPCC_RCOR_CLK(x) (x) 251 #define CLMPCC_RCOR_TLVAL (1 << 7) /* Transmit Line Value */ 252 #define CLMPCC_RCOR_DPLL_ENABLE (1 << 5) /* Phase Locked Loop Enable */ 253 #define CLMPCC_RCOR_DPLL_NRZ (0 << 3) /* PLL runs in NRZ mode */ 254 #define CLMPCC_RCOR_DPLL_NRZI (1 << 3) /* PLL runs in NRZI mode */ 255 #define CLMPCC_RCOR_DPLL_MAN (2 << 3) /* PLL runs in Manchester mode */ 256 #define CLMPCC_RCOR_CLK_0 0x0 /* Rx Clock Source 'Clk0' */ 257 #define CLMPCC_RCOR_CLK_1 0x1 /* Rx Clock Source 'Clk1' */ 258 #define CLMPCC_RCOR_CLK_2 0x2 /* Rx Clock Source 'Clk2' */ 259 #define CLMPCC_RCOR_CLK_3 0x3 /* Rx Clock Source 'Clk3' */ 260 #define CLMPCC_RCOR_CLK_4 0x4 /* Rx Clock Source 'Clk4' */ 261 #define CLMPCC_RCOR_CLK_EXT 0x6 /* Rx Clock Source 'External' */ 262 263 /* Transmit Clock Options Register */ 264 #define CLMPCC_TCOR_CLK(x) ((x) << 5) 265 #define CLMPCC_TCOR_CLK_0 (0 << 5) /* Tx Clock Source 'Clk0' */ 266 #define CLMPCC_TCOR_CLK_1 (1 << 5) /* Tx Clock Source 'Clk1' */ 267 #define CLMPCC_TCOR_CLK_2 (2 << 5) /* Tx Clock Source 'Clk2' */ 268 #define CLMPCC_TCOR_CLK_3 (3 << 5) /* Tx Clock Source 'Clk3' */ 269 #define CLMPCC_TCOR_CLK_4 (4 << 5) /* Tx Clock Source 'Clk4' */ 270 #define CLMPCC_TCOR_CLK_EXT (6 << 5) /* Tx Clock Source 'External' */ 271 #define CLMPCC_TCOR_CLK_RX (7 << 5) /* Tx Clock Source 'Same as Rx' */ 272 #define CLMPCC_TCOR_EXT_1X (1 << 3) /* Times 1 External Clock */ 273 #define CLMPCC_TCOR_LOCAL_LOOP (1 << 1) /* Enable Local Loopback */ 274 275 /* Special Transmit Command Register */ 276 #define CLMPCC_STCR_SSPC(n) ((n) & 0x7) /* Send special character 'n' */ 277 #define CLMPCC_STCR_SND_SPC (1 << 3) /* Initiate send special char */ 278 #define CLMPCC_STCR_APPEND_COMP (1 << 5) /* Append complete (Async DMA) */ 279 #define CLMPCC_STCR_ABORT_TX (1 << 6) /* Abort Tx (HDLC Mode only) */ 280 281 /* Channel Command Register */ 282 #define CLMPCC_CCR_T0_CLEAR 0x40 /* Type 0: Clear Channel */ 283 #define CLMPCC_CCR_T0_INIT 0x20 /* Type 0: Initialise Channel */ 284 #define CLMPCC_CCR_T0_RESET_ALL 0x10 /* Type 0: Reset All */ 285 #define CLMPCC_CCR_T0_TX_EN 0x08 /* Type 0: Transmitter Enable */ 286 #define CLMPCC_CCR_T0_TX_DIS 0x04 /* Type 0: Transmitter Disable */ 287 #define CLMPCC_CCR_T0_RX_EN 0x02 /* Type 0: Receiver Enable */ 288 #define CLMPCC_CCR_T0_RX_DIS 0x01 /* Type 0: Receiver Disable */ 289 #define CLMPCC_CCR_T1_CLR_TMR1 0xc0 /* Type 1: Clear Timer 1 */ 290 #define CLMPCC_CCR_T1_CLR_TMR2 0xa0 /* Type 1: Clear Timer 5 */ 291 #define CLMPCC_CCR_T1_CLR_RECV 0x90 /* Type 1: Clear Receiver */ 292 293 /* Channel Status Register (Async Mode) */ 294 #define CLMPCC_CSR_RX_ENABLED (1 << 7) /* Receiver Enabled */ 295 #define CLMPCC_CSR_RX_FLOW_OFF (1 << 6) /* Receive Flow Off */ 296 #define CLMPCC_CSR_RX_FLOW_ON (1 << 5) /* Receive Flow On */ 297 #define CLMPCC_CSR_TX_ENABLED (1 << 3) /* Transmitter Enabled */ 298 #define CLMPCC_CSR_TX_FLOW_OFF (1 << 2) /* Transmit Flow Off */ 299 #define CLMPCC_CSR_TX_FLOW_ON (1 << 1) /* Transmit Flow On */ 300 301 /* Modem Signal Value Register */ 302 #define CLMPCC_MSVR_DSR (1 << 7) /* Current State of DSR Input */ 303 #define CLMPCC_MSVR_CD (1 << 6) /* Current State of CD Input */ 304 #define CLMPCC_MSVR_CTS (1 << 5) /* Current State of CTS Input */ 305 #define CLMPCC_MSVR_DTR_OPT (1 << 4) /* DTR Option Select */ 306 #define CLMPCC_MSVR_PORT_ID (1 << 2) /* Device Type (2400 / 2401) */ 307 #define CLMPCC_MSVR_DTR (1 << 1) /* Current State of DTR Output */ 308 #define CLMPCC_MSVR_RTS (1 << 0) /* Current State of RTS Output */ 309 310 /* Local Interrupt Vector Register */ 311 #define CLMPCC_LIVR_TYPE_MASK 0x03 /* Type of Interrupt */ 312 #define CLMPCC_LIVR_EXCEPTION 0x0 /* Exception (DMA Completion) */ 313 #define CLMPCC_LIVR_MODEM 0x1 /* Modem Signal Change */ 314 #define CLMPCC_LIVR_TX 0x2 /* Transmit Data Interrupt */ 315 #define CLMPCC_LIVR_RX 0x3 /* Receive Data Interrupt */ 316 317 /* Interrupt Enable Register */ 318 #define CLMPCC_IER_MODEM (1 << 7) /* Modem Pin Change Detect */ 319 #define CLMPCC_IER_RET (1 << 5) /* Receive Exception Timeout */ 320 #define CLMPCC_IER_RX_FIFO (1 << 3) /* Rx FIFO Threshold Reached */ 321 #define CLMPCC_IER_TIMER (1 << 2) /* General Timer(s) Timeout */ 322 #define CLMPCC_IER_TX_EMPTY (1 << 1) /* Tx Empty */ 323 #define CLMPCC_IER_TX_FIFO (1 << 0) /* Tx FIFO Threshold Reached */ 324 325 /* Local Interrupting Channel Register */ 326 #define CLMPCC_LICR_MASK 0x0c /* Mask for channel number */ 327 #define CLMPCC_LICR_CHAN(v) (((v) & CLMPCC_LICR_MASK) >> 2) 328 329 /* Receive Interrupt Register */ 330 #define CLMPCC_RIR_REN (1 << 7) /* Receive Enable */ 331 #define CLMPCC_RIR_RACT (1 << 6) /* Receive Active */ 332 #define CLMPCC_RIR_REOI (1 << 5) /* Receive End of Interrupt */ 333 #define CLMPCC_RIR_RCVT_MASK 0x0c 334 #define CLMPCC_RIR_RCN_MASK 0x03 335 336 /* Receive Interrupt Status Register, Low (Async option) */ 337 #define CLMPCC_RISR_TIMEOUT (1 << 7) /* Rx FIFO Empty and Timeout */ 338 #define CLMPCC_RISR_OVERRUN (1 << 3) /* Rx Overrun Error */ 339 #define CLMPCC_RISR_PARITY (1 << 2) /* Rx Parity Error */ 340 #define CLMPCC_RISR_FRAMING (1 << 1) /* Rx Framing Error */ 341 #define CLMPCC_RISR_BREAK (1 << 0) /* BREAK Detected */ 342 343 /* Receive FIFO Counter Register */ 344 #define CLMPCC_RFOC_MASK 0x1f /* Mask for valid bits */ 345 346 /* Receive End of Interrupt Register */ 347 #define CLMPCC_REOIR_TERMBUFF (1 << 7) /* Terminate Current DMA Buffer */ 348 #define CLMPCC_REOIR_DIS_EX_CHR (1 << 6) /* Discard Exception Char (DMA) */ 349 #define CLMPCC_REOIR_TMR2_SYNC (1 << 5) /* Set Timer 2 in Sync Mode */ 350 #define CLMPCC_REOIR_TMR1_SYNC (1 << 4) /* Set Timer 1 in Sync Mode */ 351 #define CLMPCC_REOIR_NO_TRANS (1 << 3) /* No Transfer of Data */ 352 353 /* Transmit Interrupt Register */ 354 #define CLMPCC_TIR_TEN (1 << 7) /* Transmit Enable */ 355 #define CLMPCC_TIR_TACT (1 << 6) /* Transmit Active */ 356 #define CLMPCC_TIR_TEOI (1 << 5) /* Transmit End of Interrupt */ 357 #define CLMPCC_TIR_TCVT_MASK 0x0c 358 #define CLMPCC_TIR_TCN_MASK 0x03 359 360 /* Transmit Interrupt Status Register (Async option) */ 361 #define CLMPCC_TISR_BERR (1 << 7) /* Bus Error (DMA) */ 362 #define CLMPCC_TISR_EOF (1 << 6) /* Transmit End of Frame (DMA) */ 363 #define CLMPCC_TISR_EOB (1 << 5) /* Transmit End of Buffer (DMA) */ 364 #define CLMPCC_TISR_UNDERRUN (1 << 4) /* Transmit Underrun (sync only) */ 365 #define CLMPCC_TISR_BUFF_ID (1 << 3) /* Buffer that has exception */ 366 #define CLMPCC_TISR_TX_EMPTY (1 << 1) /* Transmitter Empty */ 367 #define CLMPCC_TISR_TX_FIFO (1 << 0) /* Transmit FIFO Below Threshold */ 368 369 /* Transmit FIFO Transfer Count Register */ 370 #define CLMPCC_TFTC_MASK 0x1f /* Mask for valid bits */ 371 372 /* Transmit End of Interrupt Register */ 373 #define CLMPCC_TEOIR_TERMBUFF (1 << 7) /* Terminate Current DMA Buffer */ 374 #define CLMPCC_TEOIR_END_OF_FRM (1 << 6) /* End of Frame (sync mode) */ 375 #define CLMPCC_TEOIR_TMR2_SYNC (1 << 5) /* Set Timer 2 in Sync Mode */ 376 #define CLMPCC_TEOIR_TMR1_SYNC (1 << 4) /* Set Timer 1 in Sync Mode */ 377 #define CLMPCC_TEOIR_NO_TRANS (1 << 3) /* No Transfer of Data */ 378 379 /* Modem Interrupt Register */ 380 #define CLMPCC_MIR_MEN (1 << 7) /* Modem Enable */ 381 #define CLMPCC_MIR_MACT (1 << 6) /* Modem Active */ 382 #define CLMPCC_MIR_MEOI (1 << 5) /* Modem End of Interrupt */ 383 #define CLMPCC_MIR_MCVT_MASK 0x0c 384 #define CLMPCC_MIR_MCN_MASK 0x03 385 386 /* Modem/Timer Interrupt Status Register */ 387 #define CLMPCC_MISR_DSR (1 << 7) /* DSR Changed State */ 388 #define CLMPCC_MISR_CD (1 << 6) /* CD Changed State */ 389 #define CLMPCC_MISR_CTS (1 << 5) /* CTS Changed State */ 390 #define CLMPCC_MISR_TMR2 (1 << 1) /* Timer 2 Timed Out */ 391 #define CLMPCC_MISR_TMR1 (1 << 0) /* Timer 1 Timed Out */ 392 393 /* Modem End of Interrupt Register */ 394 #define CLMPCC_MEOIR_TMR2_SYNC (1 << 5) /* Set Timer 2 in Sync Mode */ 395 #define CLMPCC_MEOIR_TMR1_SYNC (1 << 4) /* Set Timer 1 in Sync Mode */ 396 397 /* Default value for CLMPCC_REG_RTPRl */ 398 #define CLMPCC_RTPR_DEFAULT 2 /* 2mS timeout period */ 399 400 /* 401 * Return a value for the Receive Timer Prescaler register 402 * for a given clock rate and number of milliseconds. 403 * The minimum recommended value for this register is 0x0a. 404 */ 405 #define CLMPCC_MSEC_TO_TPR(c,m) (((((c)/2048)/(1000/(m))) > 0x0a) ? \ 406 (((c)/2048)/(1000/(m))) : 0x0a) 407 408 #endif /* __clmpccreg_h */ 409
Indexes created Mon Sep 22 13:09:51 GMT 2025