dw_hdmi.c revision 1.1
1 /* $NetBSD: dw_hdmi.c,v 1.1 2019/01/30 01:19:49 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dw_hdmi.c,v 1.1 2019/01/30 01:19:49 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/conf.h> 39 40 #include <dev/ic/dw_hdmi.h> 41 42 #include <dev/i2c/i2cvar.h> 43 #include <dev/i2c/ddcvar.h> 44 #include <dev/i2c/ddcreg.h> 45 #include <dev/videomode/videomode.h> 46 #include <dev/videomode/edidvar.h> 47 48 #include <drm/drmP.h> 49 #include <drm/drm_crtc.h> 50 #include <drm/drm_crtc_helper.h> 51 #include <drm/drm_edid.h> 52 53 #define HDMI_IH_I2CM_STAT0 0x0105 54 #define HDMI_IH_I2CM_STAT0_DONE __BIT(1) 55 #define HDMI_IH_I2CM_STAT0_ERROR __BIT(0) 56 #define HDMI_IH_MUTE 0x01ff 57 #define HDMI_IH_MUTE_WAKEUP_INTERRUPT __BIT(1) 58 #define HDMI_IH_MUTE_ALL_INTERRUPT __BIT(0) 59 60 #define HDMI_TX_INVID0 0x0200 61 #define HDMI_TX_INVID0_VIDEO_MAPPING __BITS(4,0) 62 #define HDMI_TX_INVID0_VIDEO_MAPPING_DEFAULT 1 63 #define HDMI_TX_INSTUFFING 0x0201 64 #define HDMI_TX_INSTUFFING_BCBDATA_STUFFING __BIT(2) 65 #define HDMI_TX_INSTUFFING_RCRDATA_STUFFING __BIT(1) 66 #define HDMI_TX_INSTUFFING_GYDATA_STUFFING __BIT(0) 67 #define HDMI_TX_GYDATA0 0x0202 68 #define HDMI_TX_GYDATA1 0x0203 69 #define HDMI_TX_RCRDATA0 0x0204 70 #define HDMI_TX_RCRDATA1 0x0205 71 #define HDMI_TX_BCBDATA0 0x0206 72 #define HDMI_TX_BCBDATA1 0x0207 73 74 #define HDMI_VP_STATUS 0x0800 75 #define HDMI_VP_PR_CD 0x0801 76 #define HDMI_VP_PR_CD_COLOR_DEPTH __BITS(7,4) 77 #define HDMI_VP_PR_CD_COLOR_DEPTH_24 0 78 #define HDMI_VP_PR_CD_DESIRED_PR_FACTOR __BITS(3,0) 79 #define HDMI_VP_PR_CD_DESIRED_PR_FACTOR_NONE 0 80 #define HDMI_VP_STUFF 0x0802 81 #define HDMI_VP_STUFF_IDEFAULT_PHASE __BIT(5) 82 #define HDMI_VP_STUFF_YCC422_STUFFING __BIT(2) 83 #define HDMI_VP_STUFF_PP_STUFFING __BIT(1) 84 #define HDMI_VP_STUFF_PR_STUFFING __BIT(0) 85 #define HDMI_VP_REMAP 0x0803 86 #define HDMI_VP_REMAP_YCC422_SIZE __BITS(1,0) 87 #define HDMI_VP_REMAP_YCC422_SIZE_16 0 88 #define HDMI_VP_CONF 0x0804 89 #define HDMI_VP_CONF_BYPASS_EN __BIT(6) 90 #define HDMI_VP_CONF_BYPASS_SELECT __BIT(2) 91 #define HDMI_VP_CONF_OUTPUT_SELECT __BITS(1,0) 92 #define HDMI_VP_CONF_OUTPUT_SELECT_BYPASS 2 93 #define HDMI_VP_STAT 0x0805 94 #define HDMI_VP_INT 0x0806 95 #define HDMI_VP_MASK 0x0807 96 #define HDMI_VP_POL 0x0808 97 98 #define HDMI_FC_INVIDCONF 0x1000 99 #define HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY __BIT(6) 100 #define HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY __BIT(5) 101 #define HDMI_FC_INVIDCONF_DE_IN_POLARITY __BIT(4) 102 #define HDMI_FC_INVIDCONF_DVI_MODE __BIT(3) 103 #define HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC __BIT(1) 104 #define HDMI_FC_INVIDCONF_IN_I_P __BIT(0) 105 #define HDMI_FC_INHACTIV0 0x1001 106 #define HDMI_FC_INHACTIV1 0x1002 107 #define HDMI_FC_INHBLANK0 0x1003 108 #define HDMI_FC_INHBLANK1 0x1004 109 #define HDMI_FC_INVACTIV0 0x1005 110 #define HDMI_FC_INVACTIV1 0x1006 111 #define HDMI_FC_INVBLANK 0x1007 112 #define HDMI_FC_HSYNCINDELAY0 0x1008 113 #define HDMI_FC_HSYNCINDELAY1 0x1009 114 #define HDMI_FC_HSYNCINWIDTH0 0x100a 115 #define HDMI_FC_HSYNCINWIDTH1 0x100b 116 #define HDMI_FC_VSYNCINDELAY 0x100c 117 #define HDMI_FC_VSYNCINWIDTH 0x100d 118 #define HDMI_FC_CTRLDUR 0x1011 119 #define HDMI_FC_CTRLDUR_DEFAULT 12 120 #define HDMI_FC_EXCTRLDUR 0x1012 121 #define HDMI_FC_EXCTRLDUR_DEFAULT 32 122 #define HDMI_FC_EXCTRLSPAC 0x1013 123 #define HDMI_FC_EXCTRLSPAC_DEFAULT 1 124 #define HDMI_FC_CH0PREAM 0x1014 125 #define HDMI_FC_CH0PREAM_DEFAULT 0x0b 126 #define HDMI_FC_CH1PREAM 0x1015 127 #define HDMI_FC_CH1PREAM_DEFAULT 0x16 128 #define HDMI_FC_CH2PREAM 0x1016 129 #define HDMI_FC_CH2PREAM_DEFAULT 0x21 130 131 #define HDMI_MC_CLKDIS 0x4001 132 #define HDMI_MC_CLKDIS_HDCPCLK_DISABLE __BIT(6) 133 #define HDMI_MC_CLKDIS_CECCLK_DISABLE __BIT(5) 134 #define HDMI_MC_CLKDIS_CSCCLK_DISABLE __BIT(4) 135 #define HDMI_MC_CLKDIS_AUDCLK_DISABLE __BIT(3) 136 #define HDMI_MC_CLKDIS_PREPCLK_DISABLE __BIT(2) 137 #define HDMI_MC_CLKDIS_TMDSCLK_DISABLE __BIT(1) 138 #define HDMI_MC_CLKDIS_PIXELCLK_DISABLE __BIT(0) 139 #define HDMI_MC_SWRSTZREQ 0x4002 140 #define HDMI_MC_SWRSTZREQ_CECSWRST_REQ __BIT(6) 141 #define HDMI_MC_SWRSTZREQ_PREPSWRST_REQ __BIT(2) 142 #define HDMI_MC_SWRSTZREQ_TMDSSWRST_REQ __BIT(1) 143 #define HDMI_MC_SWRSTZREQ_PIXELSWRST_REQ __BIT(0) 144 #define HDMI_MC_FLOWCTRL 0x4004 145 #define HDMI_MC_PHYRSTZ 0x4005 146 #define HDMI_MC_LOCKONCLOCK 0x4006 147 #define HDMI_MC_HEACPHY_RST 0x4007 148 149 #define HDMI_I2CM_SLAVE 0x7e00 150 #define HDMI_I2CM_ADDRESS 0x7e01 151 #define HDMI_I2CM_DATAO 0x7e02 152 #define HDMI_I2CM_DATAI 0x7e03 153 #define HDMI_I2CM_OPERATION 0x7e04 154 #define HDMI_I2CM_OPERATION_WR __BIT(4) 155 #define HDMI_I2CM_OPERATION_RD_EXT __BIT(1) 156 #define HDMI_I2CM_OPERATION_RD __BIT(0) 157 #define HDMI_I2CM_INT 0x7e05 158 #define HDMI_I2CM_INT_DONE_POL __BIT(3) 159 #define HDMI_I2CM_INT_DONE_MASK __BIT(2) 160 #define HDMI_I2CM_INT_DONE_INTERRUPT __BIT(1) 161 #define HDMI_I2CM_INT_DONE_STATUS __BIT(0) 162 #define HDMI_I2CM_INT_DEFAULT \ 163 (HDMI_I2CM_INT_DONE_POL| \ 164 HDMI_I2CM_INT_DONE_INTERRUPT| \ 165 HDMI_I2CM_INT_DONE_STATUS) 166 #define HDMI_I2CM_CTLINT 0x7e06 167 #define HDMI_I2CM_CTLINT_NACK_POL __BIT(7) 168 #define HDMI_I2CM_CTLINT_NACK_MASK __BIT(6) 169 #define HDMI_I2CM_CTLINT_NACK_INTERRUPT __BIT(5) 170 #define HDMI_I2CM_CTLINT_NACK_STATUS __BIT(4) 171 #define HDMI_I2CM_CTLINT_ARB_POL __BIT(3) 172 #define HDMI_I2CM_CTLINT_ARB_MASK __BIT(2) 173 #define HDMI_I2CM_CTLINT_ARB_INTERRUPT __BIT(1) 174 #define HDMI_I2CM_CTLINT_ARB_STATUS __BIT(0) 175 #define HDMI_I2CM_CTLINT_DEFAULT \ 176 (HDMI_I2CM_CTLINT_NACK_POL| \ 177 HDMI_I2CM_CTLINT_NACK_INTERRUPT| \ 178 HDMI_I2CM_CTLINT_NACK_STATUS| \ 179 HDMI_I2CM_CTLINT_ARB_POL| \ 180 HDMI_I2CM_CTLINT_ARB_INTERRUPT| \ 181 HDMI_I2CM_CTLINT_ARB_STATUS) 182 #define HDMI_I2CM_DIV 0x7e07 183 #define HDMI_I2CM_DIV_FAST_STD_MODE __BIT(3) 184 #define HDMI_I2CM_SEGADDR 0x7e08 185 #define HDMI_I2CM_SEGADDR_SEGADDR __BITS(6,0) 186 #define HDMI_I2CM_SOFTRSTZ 0x7e09 187 #define HDMI_I2CM_SOFTRSTZ_I2C_SOFTRST __BIT(0) 188 #define HDMI_I2CM_SEGPTR 0x7e0a 189 190 static int 191 dwhdmi_ddc_acquire_bus(void *priv, int flags) 192 { 193 struct dwhdmi_softc * const sc = priv; 194 195 mutex_enter(&sc->sc_ic_lock); 196 197 return 0; 198 } 199 200 static void 201 dwhdmi_ddc_release_bus(void *priv, int flags) 202 { 203 struct dwhdmi_softc * const sc = priv; 204 205 mutex_exit(&sc->sc_ic_lock); 206 } 207 208 static int 209 dwhdmi_ddc_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 210 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 211 { 212 struct dwhdmi_softc * const sc = priv; 213 uint8_t block, operation, val; 214 uint8_t *pbuf = buf; 215 int off, n, retry; 216 217 KASSERT(mutex_owned(&sc->sc_ic_lock)); 218 219 if (addr != DDC_ADDR || op != I2C_OP_READ_WITH_STOP || cmdlen == 0 || buf == NULL) { 220 printf("dwhdmi_ddc_exec: bad args addr=%#x op=%#x cmdlen=%d buf=%p\n", 221 addr, op, (int)cmdlen, buf); 222 return ENXIO; 223 } 224 if (len > 256) { 225 printf("dwhdmi_ddc_exec: bad len %d\n", (int)len); 226 return ERANGE; 227 } 228 229 dwhdmi_write(sc, HDMI_I2CM_SOFTRSTZ, 0); 230 dwhdmi_write(sc, HDMI_IH_I2CM_STAT0, dwhdmi_read(sc, HDMI_IH_I2CM_STAT0)); 231 dwhdmi_write(sc, HDMI_I2CM_DIV, 0); 232 dwhdmi_write(sc, HDMI_I2CM_SLAVE, DDC_ADDR); 233 dwhdmi_write(sc, HDMI_I2CM_SEGADDR, DDC_SEGMENT_ADDR); 234 235 block = *(const uint8_t *)cmdbuf; 236 operation = block ? HDMI_I2CM_OPERATION_RD_EXT : HDMI_I2CM_OPERATION_RD; 237 off = (block & 1) ? 128 : 0; 238 239 for (n = 0; n < len; n++) { 240 dwhdmi_write(sc, HDMI_I2CM_ADDRESS, n + off); 241 dwhdmi_write(sc, HDMI_I2CM_OPERATION, operation); 242 for (retry = 10000; retry > 0; retry--) { 243 val = dwhdmi_read(sc, HDMI_IH_I2CM_STAT0); 244 if (val & HDMI_IH_I2CM_STAT0_ERROR) { 245 return EIO; 246 } 247 if (val & HDMI_IH_I2CM_STAT0_DONE) { 248 dwhdmi_write(sc, HDMI_IH_I2CM_STAT0, val); 249 break; 250 } 251 delay(1); 252 } 253 if (retry == 0) { 254 printf("dwhdmi_ddc_exec: timeout waiting for xfer, stat0=%#x\n", dwhdmi_read(sc, HDMI_IH_I2CM_STAT0)); 255 return ETIMEDOUT; 256 } 257 258 pbuf[n] = dwhdmi_read(sc, HDMI_I2CM_DATAI); 259 } 260 261 return 0; 262 } 263 264 uint8_t 265 dwhdmi_read(struct dwhdmi_softc *sc, bus_size_t reg) 266 { 267 uint8_t val; 268 269 switch (sc->sc_reg_width) { 270 case 1: 271 val = bus_space_read_1(sc->sc_bst, sc->sc_bsh, reg); 272 break; 273 case 4: 274 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg * 4) & 0xff; 275 break; 276 default: 277 val = 0; 278 break; 279 } 280 281 return val; 282 } 283 284 void 285 dwhdmi_write(struct dwhdmi_softc *sc, bus_size_t reg, uint8_t val) 286 { 287 switch (sc->sc_reg_width) { 288 case 1: 289 bus_space_write_1(sc->sc_bst, sc->sc_bsh, reg, val); 290 break; 291 case 4: 292 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg * 4, val); 293 break; 294 } 295 } 296 297 static void 298 dwhdmi_vp_init(struct dwhdmi_softc *sc) 299 { 300 uint8_t val; 301 302 /* Select 24-bits per pixel video, 8-bit packing mode and disable pixel repetition */ 303 val = __SHIFTIN(HDMI_VP_PR_CD_COLOR_DEPTH_24, HDMI_VP_PR_CD_COLOR_DEPTH) | 304 __SHIFTIN(HDMI_VP_PR_CD_DESIRED_PR_FACTOR_NONE, HDMI_VP_PR_CD_DESIRED_PR_FACTOR); 305 dwhdmi_write(sc, HDMI_VP_PR_CD, val); 306 307 /* Configure stuffing */ 308 val = HDMI_VP_STUFF_IDEFAULT_PHASE | 309 HDMI_VP_STUFF_YCC422_STUFFING | 310 HDMI_VP_STUFF_PP_STUFFING | 311 HDMI_VP_STUFF_PR_STUFFING; 312 dwhdmi_write(sc, HDMI_VP_STUFF, val); 313 314 /* Set YCC422 remap to 16-bit input video */ 315 val = __SHIFTIN(HDMI_VP_REMAP_YCC422_SIZE_16, HDMI_VP_REMAP_YCC422_SIZE); 316 dwhdmi_write(sc, HDMI_VP_REMAP, val); 317 318 /* Configure video packetizer */ 319 val = HDMI_VP_CONF_BYPASS_EN | 320 HDMI_VP_CONF_BYPASS_SELECT | 321 __SHIFTIN(HDMI_VP_CONF_OUTPUT_SELECT_BYPASS, HDMI_VP_CONF_OUTPUT_SELECT); 322 dwhdmi_write(sc, HDMI_VP_CONF, val); 323 } 324 325 static void 326 dwhdmi_tx_init(struct dwhdmi_softc *sc) 327 { 328 uint8_t val; 329 330 /* Disable internal data enable generator and set default video mapping */ 331 val = __SHIFTIN(HDMI_TX_INVID0_VIDEO_MAPPING_DEFAULT, HDMI_TX_INVID0_VIDEO_MAPPING); 332 dwhdmi_write(sc, HDMI_TX_INVID0, val); 333 334 /* Enable video sampler stuffing */ 335 val = HDMI_TX_INSTUFFING_BCBDATA_STUFFING | 336 HDMI_TX_INSTUFFING_RCRDATA_STUFFING | 337 HDMI_TX_INSTUFFING_GYDATA_STUFFING; 338 dwhdmi_write(sc, HDMI_TX_INSTUFFING, val); 339 } 340 341 static bool 342 dwhdmi_cea_mode_uses_fractional_vblank(uint8_t vic) 343 { 344 const uint8_t match[] = { 5, 6, 7, 10, 11, 20, 21, 22 }; 345 u_int n; 346 347 for (n = 0; n < __arraycount(match); n++) 348 if (match[n] == vic) 349 return true; 350 351 return false; 352 } 353 354 static void 355 dwhdmi_fc_init(struct dwhdmi_softc *sc, struct drm_display_mode *mode) 356 { 357 struct dwhdmi_connector *dwhdmi_connector = &sc->sc_connector; 358 uint8_t val; 359 360 const uint8_t vic = drm_match_cea_mode(mode); 361 const uint16_t inhactiv = mode->hdisplay; 362 const uint16_t inhblank = mode->htotal - mode->hdisplay; 363 const uint16_t invactiv = mode->vdisplay; 364 const uint8_t invblank = mode->vtotal - mode->vdisplay; 365 const uint16_t hsyncindelay = mode->hsync_start - mode->hdisplay; 366 const uint16_t hsyncinwidth = mode->hsync_end - mode->hsync_start; 367 const uint8_t vsyncindelay = mode->vsync_start - mode->vdisplay; 368 const uint8_t vsyncinwidth = mode->vsync_end - mode->vsync_start; 369 370 /* Input video configuration for frame composer */ 371 val = HDMI_FC_INVIDCONF_DE_IN_POLARITY; 372 if ((mode->flags & DRM_MODE_FLAG_PVSYNC) != 0) 373 val |= HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY; 374 if ((mode->flags & DRM_MODE_FLAG_PHSYNC) != 0) 375 val |= HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY; 376 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) != 0) 377 val |= HDMI_FC_INVIDCONF_IN_I_P; 378 if (dwhdmi_connector->hdmi_monitor) 379 val |= HDMI_FC_INVIDCONF_DVI_MODE; 380 if (dwhdmi_cea_mode_uses_fractional_vblank(vic)) 381 val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC; 382 dwhdmi_write(sc, HDMI_FC_INVIDCONF, val); 383 384 /* Input video mode timings */ 385 dwhdmi_write(sc, HDMI_FC_INHACTIV0, inhactiv & 0xff); 386 dwhdmi_write(sc, HDMI_FC_INHACTIV1, inhactiv >> 8); 387 dwhdmi_write(sc, HDMI_FC_INHBLANK0, inhblank & 0xff); 388 dwhdmi_write(sc, HDMI_FC_INHBLANK1, inhblank >> 8); 389 dwhdmi_write(sc, HDMI_FC_INVACTIV0, invactiv & 0xff); 390 dwhdmi_write(sc, HDMI_FC_INVACTIV1, invactiv >> 8); 391 dwhdmi_write(sc, HDMI_FC_INVBLANK, invblank); 392 dwhdmi_write(sc, HDMI_FC_HSYNCINDELAY0, hsyncindelay & 0xff); 393 dwhdmi_write(sc, HDMI_FC_HSYNCINDELAY1, hsyncindelay >> 8); 394 dwhdmi_write(sc, HDMI_FC_HSYNCINWIDTH0, hsyncinwidth & 0xff); 395 dwhdmi_write(sc, HDMI_FC_HSYNCINWIDTH1, hsyncinwidth >> 8); 396 dwhdmi_write(sc, HDMI_FC_VSYNCINDELAY, vsyncindelay); 397 dwhdmi_write(sc, HDMI_FC_VSYNCINWIDTH, vsyncinwidth); 398 399 /* Setup control period minimum durations */ 400 dwhdmi_write(sc, HDMI_FC_CTRLDUR, HDMI_FC_CTRLDUR_DEFAULT); 401 dwhdmi_write(sc, HDMI_FC_EXCTRLDUR, HDMI_FC_EXCTRLDUR_DEFAULT); 402 dwhdmi_write(sc, HDMI_FC_EXCTRLSPAC, HDMI_FC_EXCTRLSPAC_DEFAULT); 403 404 /* Setup channel preamble filters */ 405 dwhdmi_write(sc, HDMI_FC_CH0PREAM, HDMI_FC_CH0PREAM_DEFAULT); 406 dwhdmi_write(sc, HDMI_FC_CH1PREAM, HDMI_FC_CH1PREAM_DEFAULT); 407 dwhdmi_write(sc, HDMI_FC_CH2PREAM, HDMI_FC_CH2PREAM_DEFAULT); 408 } 409 410 static void 411 dwhdmi_mc_init(struct dwhdmi_softc *sc) 412 { 413 struct dwhdmi_connector *dwhdmi_connector = &sc->sc_connector; 414 uint8_t val; 415 u_int n; 416 417 /* Bypass colour space converter */ 418 dwhdmi_write(sc, HDMI_MC_FLOWCTRL, 0); 419 420 /* Enable TMDS, pixel, and (if required) audio sampler clocks */ 421 val = HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 422 HDMI_MC_CLKDIS_CECCLK_DISABLE | 423 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 424 HDMI_MC_CLKDIS_PREPCLK_DISABLE; 425 if (!dwhdmi_connector->monitor_audio) 426 val |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 427 dwhdmi_write(sc, HDMI_MC_CLKDIS, val); 428 429 /* Soft reset TMDS */ 430 val = 0xff & ~HDMI_MC_SWRSTZREQ_TMDSSWRST_REQ; 431 dwhdmi_write(sc, HDMI_MC_SWRSTZREQ, val); 432 433 val = dwhdmi_read(sc, HDMI_FC_INVIDCONF); 434 for (n = 0; n < 4; n++) 435 dwhdmi_write(sc, HDMI_FC_INVIDCONF, val); 436 } 437 438 static void 439 dwhdmi_mc_disable(struct dwhdmi_softc *sc) 440 { 441 /* Disable clocks */ 442 dwhdmi_write(sc, HDMI_MC_CLKDIS, 0xff); 443 } 444 445 static enum drm_connector_status 446 dwhdmi_connector_detect(struct drm_connector *connector, bool force) 447 { 448 struct dwhdmi_connector *dwhdmi_connector = to_dwhdmi_connector(connector); 449 struct dwhdmi_softc * const sc = dwhdmi_connector->sc; 450 451 if (sc->sc_detect != NULL) 452 return sc->sc_detect(sc, force); 453 454 return connector_status_connected; 455 } 456 457 static void 458 dwhdmi_connector_destroy(struct drm_connector *connector) 459 { 460 drm_connector_unregister(connector); 461 drm_connector_cleanup(connector); 462 } 463 464 static const struct drm_connector_funcs dwhdmi_connector_funcs = { 465 .dpms = drm_helper_connector_dpms, 466 .detect = dwhdmi_connector_detect, 467 .fill_modes = drm_helper_probe_single_connector_modes, 468 .destroy = dwhdmi_connector_destroy, 469 }; 470 471 static int 472 dwhdmi_connector_get_modes(struct drm_connector *connector) 473 { 474 struct dwhdmi_connector *dwhdmi_connector = to_dwhdmi_connector(connector); 475 struct dwhdmi_softc * const sc = dwhdmi_connector->sc; 476 char edid[EDID_LENGTH * 4]; 477 struct edid *pedid = NULL; 478 int error, block; 479 480 memset(edid, 0, sizeof(edid)); 481 for (block = 0; block < 4; block++) { 482 error = ddc_read_edid_block(&sc->sc_ic, 483 &edid[block * EDID_LENGTH], EDID_LENGTH, block); 484 if (error != 0) 485 break; 486 if (block == 0) { 487 pedid = (struct edid *)edid; 488 if (edid[0x7e] == 0) 489 break; 490 } 491 } 492 493 if (pedid) { 494 dwhdmi_connector->hdmi_monitor = drm_detect_hdmi_monitor(pedid); 495 dwhdmi_connector->monitor_audio = drm_detect_monitor_audio(pedid); 496 } else { 497 dwhdmi_connector->hdmi_monitor = false; 498 dwhdmi_connector->monitor_audio = false; 499 } 500 501 drm_mode_connector_update_edid_property(connector, pedid); 502 if (pedid == NULL) 503 return 0; 504 505 error = drm_add_edid_modes(connector, pedid); 506 drm_edid_to_eld(connector, pedid); 507 508 return error; 509 } 510 511 static struct drm_encoder * 512 dwhdmi_connector_best_encoder(struct drm_connector *connector) 513 { 514 int enc_id = connector->encoder_ids[0]; 515 struct drm_mode_object *obj; 516 struct drm_encoder *encoder = NULL; 517 518 if (enc_id) { 519 obj = drm_mode_object_find(connector->dev, enc_id, 520 DRM_MODE_OBJECT_ENCODER); 521 if (obj == NULL) 522 return NULL; 523 encoder = obj_to_encoder(obj); 524 } 525 526 return encoder; 527 } 528 529 static const struct drm_connector_helper_funcs dwhdmi_connector_helper_funcs = { 530 .get_modes = dwhdmi_connector_get_modes, 531 .best_encoder = dwhdmi_connector_best_encoder, 532 }; 533 534 static int 535 dwhdmi_bridge_attach(struct drm_bridge *bridge) 536 { 537 struct dwhdmi_softc * const sc = bridge->driver_private; 538 struct dwhdmi_connector *dwhdmi_connector = &sc->sc_connector; 539 struct drm_connector *connector = &dwhdmi_connector->base; 540 int error; 541 542 dwhdmi_connector->sc = sc; 543 544 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 545 connector->interlace_allowed = 0; 546 connector->doublescan_allowed = 0; 547 548 drm_connector_init(bridge->dev, connector, &dwhdmi_connector_funcs, 549 DRM_MODE_CONNECTOR_HDMIA); 550 drm_connector_helper_add(connector, &dwhdmi_connector_helper_funcs); 551 552 error = drm_mode_connector_attach_encoder(connector, bridge->encoder); 553 if (error != 0) 554 return error; 555 556 return drm_connector_register(connector); 557 } 558 559 static void 560 dwhdmi_bridge_enable(struct drm_bridge *bridge) 561 { 562 struct dwhdmi_softc * const sc = bridge->driver_private; 563 564 dwhdmi_vp_init(sc); 565 dwhdmi_fc_init(sc, &sc->sc_curmode); 566 567 if (sc->sc_enable) 568 sc->sc_enable(sc); 569 570 dwhdmi_tx_init(sc); 571 dwhdmi_mc_init(sc); 572 } 573 574 static void 575 dwhdmi_bridge_pre_enable(struct drm_bridge *bridge) 576 { 577 } 578 579 static void 580 dwhdmi_bridge_disable(struct drm_bridge *bridge) 581 { 582 struct dwhdmi_softc * const sc = bridge->driver_private; 583 584 if (sc->sc_disable) 585 sc->sc_disable(sc); 586 587 dwhdmi_mc_disable(sc); 588 } 589 590 static void 591 dwhdmi_bridge_post_disable(struct drm_bridge *bridge) 592 { 593 } 594 595 static void 596 dwhdmi_bridge_mode_set(struct drm_bridge *bridge, 597 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 598 { 599 struct dwhdmi_softc * const sc = bridge->driver_private; 600 601 if (sc->sc_mode_set) 602 sc->sc_mode_set(sc, mode, adjusted_mode); 603 604 sc->sc_curmode = *adjusted_mode; 605 } 606 607 static bool 608 dwhdmi_bridge_mode_fixup(struct drm_bridge *bridge, 609 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 610 { 611 return true; 612 } 613 614 static const struct drm_bridge_funcs dwhdmi_bridge_funcs = { 615 .attach = dwhdmi_bridge_attach, 616 .enable = dwhdmi_bridge_enable, 617 .pre_enable = dwhdmi_bridge_pre_enable, 618 .disable = dwhdmi_bridge_disable, 619 .post_disable = dwhdmi_bridge_post_disable, 620 .mode_set = dwhdmi_bridge_mode_set, 621 .mode_fixup = dwhdmi_bridge_mode_fixup, 622 }; 623 624 int 625 dwhdmi_attach(struct dwhdmi_softc *sc) 626 { 627 struct i2c_controller *ic = &sc->sc_ic; 628 629 if (sc->sc_reg_width != 1 && sc->sc_reg_width != 4) { 630 aprint_error_dev(sc->sc_dev, "unsupported register width %d\n", sc->sc_reg_width); 631 return EINVAL; 632 } 633 634 mutex_init(&sc->sc_ic_lock, MUTEX_DEFAULT, IPL_NONE); 635 636 ic->ic_cookie = sc; 637 ic->ic_acquire_bus = dwhdmi_ddc_acquire_bus; 638 ic->ic_release_bus = dwhdmi_ddc_release_bus; 639 ic->ic_exec = dwhdmi_ddc_exec; 640 641 return 0; 642 } 643 644 int 645 dwhdmi_bind(struct dwhdmi_softc *sc, struct drm_encoder *encoder) 646 { 647 int error; 648 649 sc->sc_bridge.driver_private = sc; 650 sc->sc_bridge.funcs = &dwhdmi_bridge_funcs; 651 sc->sc_bridge.encoder = encoder; 652 653 error = drm_bridge_attach(encoder->dev, &sc->sc_bridge); 654 if (error != 0) 655 return EIO; 656 657 encoder->bridge = &sc->sc_bridge; 658 659 return 0; 660 } 661
Indexes created Thu Sep 25 16:09:42 GMT 2025