| History log of /src/sys/dev/ic/dw_hdmi.c |
| Revision | | Date | Author | Comments |
| 1.12 |
| 09-Feb-2024 |
skrll | Trailing whitespace
|
| 1.11 |
| 11-Dec-2023 |
mlelstv | Output is always 16bit, the internal audio data type may differ.
|
| 1.10 |
| 25-Mar-2022 |
tnn | dwhdmi: properly initialize connector atomic helper funcs (PR port-evbarm/56766)
|
| 1.9 |
| 19-Dec-2021 |
riastradh | Sort includes.
|
| 1.8 |
| 19-Dec-2021 |
riastradh | Get drm to build on arm64 again.
Author: Jared McNeill <jmcneill@NetBSD.org>
Committer: Taylor R Campbell <riastradh@NetBSD.org>
|
| 1.7 |
| 22-Dec-2019 |
thorpej | Cleanup i2c bus acquire / release, centralizing all of the logic into
iic_acquire_bus() / iic_release_bus(). "acquire" and "release" hooks
no longer need to be provided by back-end controller drivers (only if
they need special handling, e.g. powering on the i2c controller).
This results in the removal of a bunch of rendundant code from each
back-end controller driver.
Assert that we are not in hard interrupt context in iic_acquire_bus(),
iic_exec(), and iic_release_bus().
|
| 1.6 |
| 23-Nov-2019 |
jmcneill | Use actual hw mode, not proposed mode.
|
| 1.5 |
| 23-Nov-2019 |
jmcneill | Allow bus glue to setup DDC clocks
|
| 1.4 |
| 16-Nov-2019 |
jmcneill | Add software volume controls.
|
| 1.3 |
| 16-Nov-2019 |
jmcneill | Add I2S audio input support.
|
| 1.2 |
| 09-Nov-2019 |
jmcneill | Add support for internal DesignWare HDMI PHYs
|
| 1.1 |
| 30-Jan-2019 |
jmcneill | branches: 1.1.4; 1.1.6;
Add driver for Designware HDMI TX controller.
|
| 1.1.6.2 |
| 25-Nov-2019 |
martin | Pull up following revision(s) (requested by jmcneill in ticket #470):
sys/arch/arm/sunxi/sunxi_hdmiphy.c: revision 1.4
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.16
sys/dev/ic/dw_hdmi.c: revision 1.5
sys/arch/arm/sunxi/sunxi_hdmiphy.h: revision 1.2
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.17
sys/dev/ic/dw_hdmi.c: revision 1.6
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.18
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.19
sys/dev/ic/dw_hdmi.h: revision 1.5
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.8
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.9
sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.22
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.5
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.6
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.7
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.8
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.20
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.10
sys/arch/arm/dts/sun50i-a64-pinebook.dts: revision 1.17
sys/arch/arm/sunxi/sunxi_platform.c: revision 1.38
sys/dev/fdt/fdt_port.c: revision 1.3
sys/dev/fdt/fdt_port.c: revision 1.4
sys/arch/arm/sunxi/sunxi_ccu_fractional.c: revision 1.5
sys/arch/arm/sunxi/sunxi_lcdc.c: revision 1.7
sys/arch/arm/sunxi/sunxi_ccu_fractional.c: revision 1.6
sys/arch/arm/sunxi/sunxi_hdmiphy.c: revision 1.3
Fix CLK_BUS_HDMI bit
Enable TMDS clock
Store the flags passed to SUNXI_CCU_FRACTIONAL macro.
Previously the macro dropped the flags argument entirely, and did not
initialize the structure with it.
Allow bus glue to setup DDC clocks
Add TCON0 clock
HDMI PHY and TX share the same clocks. Do not enable clocks until both
reset resources have been deasserted. Explicitly set DDC clock dividers.
Honour SUNXI_CCU_FRACTIONAL_SET_ENABLE in fractional mode
Use fdtbus_get_reg to read "reg" property
Need to initialize the PHY before HPD sense and DDC will work
Set pixel clock on mode set
Set TCON1 parent to PLL_VIDEO1(1X)
Do not assume that an fb's pitch is width * 4 bytes.
Use actual hw mode, not proposed mode.
Set pre-divider M to 0 in fractional mode, as noted in user manual. Spotted by jak.
Support non-zero fb start pixels.
Set video PLLs to 297MHz
Do not assume the cursor pitch is the same as the primary fb
Enable HDMI and HDMI audio
Try to avoid changing hardware settings when the "nomodeset" kernel arg
is present.
|
| 1.1.6.1 |
| 16-Nov-2019 |
martin | Pull up following revision(s) (requested by jmcneill in ticket #427):
sys/dev/ic/dw_hdmi_phy.c: revision 1.2
sys/dev/ic/dw_hdmi.c: revision 1.4
sys/dev/fdt/ausoc.c: revision 1.5
sys/dev/ic/dw_hdmi.h: revision 1.2
sys/dev/ic/dw_hdmi.h: revision 1.3
sys/dev/ic/dw_hdmi.h: revision 1.4
sys/conf/files: revision 1.1242
sys/dev/fdt/fdtvar.h: revision 1.57
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.11
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.12
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.13
sys/arch/evbarm/conf/GENERIC64: revision 1.110
sys/arch/arm/rockchip/rk_drm.c: revision 1.1
sys/arch/arm/rockchip/rk_drm.c: revision 1.2
sys/arch/evbarm/conf/GENERIC64: revision 1.112
sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.1
sys/dev/fdt/fdt_clock.c: revision 1.10
sys/arch/evbarm/conf/GENERIC64: revision 1.113
sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.2
sys/arch/arm/rockchip/rk_drm.h: revision 1.1
sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.3
sys/arch/arm/rockchip/rk_fb.c: revision 1.1
sys/arch/arm/dts/rk3399-rockpro64.dts: revision 1.9
sys/arch/arm/rockchip/rk_vop.c: revision 1.1
sys/arch/arm/rockchip/rk_vop.c: revision 1.2
sys/arch/arm/rockchip/rk_i2c.c: revision 1.6
sys/arch/arm/rockchip/rk_cru.h: revision 1.6
sys/arch/arm/rockchip/rk_cru.h: revision 1.7
sys/arch/arm/rockchip/rk_cru_composite.c: revision 1.4
sys/arch/arm/rockchip/rk_cru_composite.c: revision 1.5
sys/arch/arm/rockchip/files.rockchip: revision 1.21
sys/arch/arm/rockchip/rk_i2s.c: revision 1.1
sys/arch/arm/rockchip/files.rockchip: revision 1.22
sys/dev/ic/dw_hdmi.c: revision 1.2
sys/dev/ic/dw_hdmi_phy.c: revision 1.1
sys/dev/ic/dw_hdmi.c: revision 1.3
Support reads of more than 32 bytes in a single xfer.
Add support for internal DesignWare HDMI PHYs
Add fdtbus_clock_enable and fdtbus_clock_enable_index shortcuts
Add HDMI and VOP clocks
WIP display driver for Rockchip RK3399
Add (commented out) Rockchip display support
Select the correct MPLL and PHY settings for the requested pixel clock
Force DCLK_VOP0/1 dividers to 1 and select closest match when setting PLL
rates.
Fix typo in phy config table
Fix a few swapped fields
Remove debug output
Enable Rockchip display support
Set sysclk rate at set_format time, so the link set_format callback can read the new sysclk
Add I2S audio input support.
Add software volume controls.
Add support for I2S clocks.
Add driver for Rockchip I2S/PCM controller.
Enable HDMI audio on ROCKPro64
Add rki2s
Add audio support
|
| 1.1.4.3 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.1.4.2 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.1.4.1 |
| 30-Jan-2019 |
christos | file dw_hdmi.c was added on branch phil-wifi on 2019-06-10 22:07:10 +0000
|
