dw_hdmi.c revision 1.2
1 /* $NetBSD: dw_hdmi.c,v 1.2 2019/11/09 23:27:50 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dw_hdmi.c,v 1.2 2019/11/09 23:27:50 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/conf.h> 39 40 #include <dev/ic/dw_hdmi.h> 41 42 #include <dev/i2c/i2cvar.h> 43 #include <dev/i2c/ddcvar.h> 44 #include <dev/i2c/ddcreg.h> 45 #include <dev/videomode/videomode.h> 46 #include <dev/videomode/edidvar.h> 47 48 #include <drm/drmP.h> 49 #include <drm/drm_crtc.h> 50 #include <drm/drm_crtc_helper.h> 51 #include <drm/drm_edid.h> 52 53 #define HDMI_DESIGN_ID 0x0000 54 #define HDMI_REVISION_ID 0x0001 55 #define HDMI_CONFIG2_ID 0x0006 56 57 #define HDMI_IH_I2CM_STAT0 0x0105 58 #define HDMI_IH_I2CM_STAT0_DONE __BIT(1) 59 #define HDMI_IH_I2CM_STAT0_ERROR __BIT(0) 60 #define HDMI_IH_MUTE 0x01ff 61 #define HDMI_IH_MUTE_WAKEUP_INTERRUPT __BIT(1) 62 #define HDMI_IH_MUTE_ALL_INTERRUPT __BIT(0) 63 64 #define HDMI_TX_INVID0 0x0200 65 #define HDMI_TX_INVID0_VIDEO_MAPPING __BITS(4,0) 66 #define HDMI_TX_INVID0_VIDEO_MAPPING_DEFAULT 1 67 #define HDMI_TX_INSTUFFING 0x0201 68 #define HDMI_TX_INSTUFFING_BCBDATA_STUFFING __BIT(2) 69 #define HDMI_TX_INSTUFFING_RCRDATA_STUFFING __BIT(1) 70 #define HDMI_TX_INSTUFFING_GYDATA_STUFFING __BIT(0) 71 #define HDMI_TX_GYDATA0 0x0202 72 #define HDMI_TX_GYDATA1 0x0203 73 #define HDMI_TX_RCRDATA0 0x0204 74 #define HDMI_TX_RCRDATA1 0x0205 75 #define HDMI_TX_BCBDATA0 0x0206 76 #define HDMI_TX_BCBDATA1 0x0207 77 78 #define HDMI_VP_STATUS 0x0800 79 #define HDMI_VP_PR_CD 0x0801 80 #define HDMI_VP_PR_CD_COLOR_DEPTH __BITS(7,4) 81 #define HDMI_VP_PR_CD_COLOR_DEPTH_24 0 82 #define HDMI_VP_PR_CD_DESIRED_PR_FACTOR __BITS(3,0) 83 #define HDMI_VP_PR_CD_DESIRED_PR_FACTOR_NONE 0 84 #define HDMI_VP_STUFF 0x0802 85 #define HDMI_VP_STUFF_IDEFAULT_PHASE __BIT(5) 86 #define HDMI_VP_STUFF_YCC422_STUFFING __BIT(2) 87 #define HDMI_VP_STUFF_PP_STUFFING __BIT(1) 88 #define HDMI_VP_STUFF_PR_STUFFING __BIT(0) 89 #define HDMI_VP_REMAP 0x0803 90 #define HDMI_VP_REMAP_YCC422_SIZE __BITS(1,0) 91 #define HDMI_VP_REMAP_YCC422_SIZE_16 0 92 #define HDMI_VP_CONF 0x0804 93 #define HDMI_VP_CONF_BYPASS_EN __BIT(6) 94 #define HDMI_VP_CONF_BYPASS_SELECT __BIT(2) 95 #define HDMI_VP_CONF_OUTPUT_SELECT __BITS(1,0) 96 #define HDMI_VP_CONF_OUTPUT_SELECT_BYPASS 2 97 #define HDMI_VP_STAT 0x0805 98 #define HDMI_VP_INT 0x0806 99 #define HDMI_VP_MASK 0x0807 100 #define HDMI_VP_POL 0x0808 101 102 #define HDMI_FC_INVIDCONF 0x1000 103 #define HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY __BIT(6) 104 #define HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY __BIT(5) 105 #define HDMI_FC_INVIDCONF_DE_IN_POLARITY __BIT(4) 106 #define HDMI_FC_INVIDCONF_DVI_MODE __BIT(3) 107 #define HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC __BIT(1) 108 #define HDMI_FC_INVIDCONF_IN_I_P __BIT(0) 109 #define HDMI_FC_INHACTIV0 0x1001 110 #define HDMI_FC_INHACTIV1 0x1002 111 #define HDMI_FC_INHBLANK0 0x1003 112 #define HDMI_FC_INHBLANK1 0x1004 113 #define HDMI_FC_INVACTIV0 0x1005 114 #define HDMI_FC_INVACTIV1 0x1006 115 #define HDMI_FC_INVBLANK 0x1007 116 #define HDMI_FC_HSYNCINDELAY0 0x1008 117 #define HDMI_FC_HSYNCINDELAY1 0x1009 118 #define HDMI_FC_HSYNCINWIDTH0 0x100a 119 #define HDMI_FC_HSYNCINWIDTH1 0x100b 120 #define HDMI_FC_VSYNCINDELAY 0x100c 121 #define HDMI_FC_VSYNCINWIDTH 0x100d 122 #define HDMI_FC_CTRLDUR 0x1011 123 #define HDMI_FC_CTRLDUR_DEFAULT 12 124 #define HDMI_FC_EXCTRLDUR 0x1012 125 #define HDMI_FC_EXCTRLDUR_DEFAULT 32 126 #define HDMI_FC_EXCTRLSPAC 0x1013 127 #define HDMI_FC_EXCTRLSPAC_DEFAULT 1 128 #define HDMI_FC_CH0PREAM 0x1014 129 #define HDMI_FC_CH0PREAM_DEFAULT 0x0b 130 #define HDMI_FC_CH1PREAM 0x1015 131 #define HDMI_FC_CH1PREAM_DEFAULT 0x16 132 #define HDMI_FC_CH2PREAM 0x1016 133 #define HDMI_FC_CH2PREAM_DEFAULT 0x21 134 135 #define HDMI_PHY_CONF0 0x3000 136 #define HDMI_PHY_CONF0_PDZ __BIT(7) 137 #define HDMI_PHY_CONF0_ENTMDS __BIT(6) 138 #define HDMI_PHY_CONF0_SVSRET __BIT(5) 139 #define HDMI_PHY_CONF0_PDDQ __BIT(4) 140 #define HDMI_PHY_CONF0_TXPWRON __BIT(3) 141 #define HDMI_PHY_CONF0_ENHPDRXSENSE __BIT(2) 142 #define HDMI_PHY_CONF0_SELDATAENPOL __BIT(1) 143 #define HDMI_PHY_CONF0_SELDIPIF __BIT(0) 144 #define HDMI_PHY_STAT0 0x3004 145 #define HDMI_PHY_STAT0_RX_SENSE_3 __BIT(7) 146 #define HDMI_PHY_STAT0_RX_SENSE_2 __BIT(6) 147 #define HDMI_PHY_STAT0_RX_SENSE_1 __BIT(5) 148 #define HDMI_PHY_STAT0_RX_SENSE_0 __BIT(4) 149 #define HDMI_PHY_STAT0_HPD __BIT(1) 150 #define HDMI_PHY_STAT0_TX_PHY_LOCK __BIT(0) 151 152 #define HDMI_MC_CLKDIS 0x4001 153 #define HDMI_MC_CLKDIS_HDCPCLK_DISABLE __BIT(6) 154 #define HDMI_MC_CLKDIS_CECCLK_DISABLE __BIT(5) 155 #define HDMI_MC_CLKDIS_CSCCLK_DISABLE __BIT(4) 156 #define HDMI_MC_CLKDIS_AUDCLK_DISABLE __BIT(3) 157 #define HDMI_MC_CLKDIS_PREPCLK_DISABLE __BIT(2) 158 #define HDMI_MC_CLKDIS_TMDSCLK_DISABLE __BIT(1) 159 #define HDMI_MC_CLKDIS_PIXELCLK_DISABLE __BIT(0) 160 #define HDMI_MC_SWRSTZREQ 0x4002 161 #define HDMI_MC_SWRSTZREQ_CECSWRST_REQ __BIT(6) 162 #define HDMI_MC_SWRSTZREQ_PREPSWRST_REQ __BIT(2) 163 #define HDMI_MC_SWRSTZREQ_TMDSSWRST_REQ __BIT(1) 164 #define HDMI_MC_SWRSTZREQ_PIXELSWRST_REQ __BIT(0) 165 #define HDMI_MC_FLOWCTRL 0x4004 166 #define HDMI_MC_PHYRSTZ 0x4005 167 #define HDMI_MC_PHYRSTZ_ASSERT __BIT(0) 168 #define HDMI_MC_PHYRSTZ_DEASSERT 0 169 #define HDMI_MC_LOCKONCLOCK 0x4006 170 #define HDMI_MC_HEACPHY_RST 0x4007 171 172 #define HDMI_I2CM_SLAVE 0x7e00 173 #define HDMI_I2CM_ADDRESS 0x7e01 174 #define HDMI_I2CM_DATAO 0x7e02 175 #define HDMI_I2CM_DATAI 0x7e03 176 #define HDMI_I2CM_OPERATION 0x7e04 177 #define HDMI_I2CM_OPERATION_WR __BIT(4) 178 #define HDMI_I2CM_OPERATION_RD_EXT __BIT(1) 179 #define HDMI_I2CM_OPERATION_RD __BIT(0) 180 #define HDMI_I2CM_INT 0x7e05 181 #define HDMI_I2CM_INT_DONE_POL __BIT(3) 182 #define HDMI_I2CM_INT_DONE_MASK __BIT(2) 183 #define HDMI_I2CM_INT_DONE_INTERRUPT __BIT(1) 184 #define HDMI_I2CM_INT_DONE_STATUS __BIT(0) 185 #define HDMI_I2CM_INT_DEFAULT \ 186 (HDMI_I2CM_INT_DONE_POL| \ 187 HDMI_I2CM_INT_DONE_INTERRUPT| \ 188 HDMI_I2CM_INT_DONE_STATUS) 189 #define HDMI_I2CM_CTLINT 0x7e06 190 #define HDMI_I2CM_CTLINT_NACK_POL __BIT(7) 191 #define HDMI_I2CM_CTLINT_NACK_MASK __BIT(6) 192 #define HDMI_I2CM_CTLINT_NACK_INTERRUPT __BIT(5) 193 #define HDMI_I2CM_CTLINT_NACK_STATUS __BIT(4) 194 #define HDMI_I2CM_CTLINT_ARB_POL __BIT(3) 195 #define HDMI_I2CM_CTLINT_ARB_MASK __BIT(2) 196 #define HDMI_I2CM_CTLINT_ARB_INTERRUPT __BIT(1) 197 #define HDMI_I2CM_CTLINT_ARB_STATUS __BIT(0) 198 #define HDMI_I2CM_CTLINT_DEFAULT \ 199 (HDMI_I2CM_CTLINT_NACK_POL| \ 200 HDMI_I2CM_CTLINT_NACK_INTERRUPT| \ 201 HDMI_I2CM_CTLINT_NACK_STATUS| \ 202 HDMI_I2CM_CTLINT_ARB_POL| \ 203 HDMI_I2CM_CTLINT_ARB_INTERRUPT| \ 204 HDMI_I2CM_CTLINT_ARB_STATUS) 205 #define HDMI_I2CM_DIV 0x7e07 206 #define HDMI_I2CM_DIV_FAST_STD_MODE __BIT(3) 207 #define HDMI_I2CM_SEGADDR 0x7e08 208 #define HDMI_I2CM_SEGADDR_SEGADDR __BITS(6,0) 209 #define HDMI_I2CM_SOFTRSTZ 0x7e09 210 #define HDMI_I2CM_SOFTRSTZ_I2C_SOFTRST __BIT(0) 211 #define HDMI_I2CM_SEGPTR 0x7e0a 212 213 static int 214 dwhdmi_ddc_acquire_bus(void *priv, int flags) 215 { 216 struct dwhdmi_softc * const sc = priv; 217 218 mutex_enter(&sc->sc_ic_lock); 219 220 return 0; 221 } 222 223 static void 224 dwhdmi_ddc_release_bus(void *priv, int flags) 225 { 226 struct dwhdmi_softc * const sc = priv; 227 228 mutex_exit(&sc->sc_ic_lock); 229 } 230 231 static int 232 dwhdmi_ddc_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 233 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 234 { 235 struct dwhdmi_softc * const sc = priv; 236 uint8_t block, operation, val; 237 uint8_t *pbuf = buf; 238 int off, n, retry; 239 240 KASSERT(mutex_owned(&sc->sc_ic_lock)); 241 242 if (addr != DDC_ADDR || op != I2C_OP_READ_WITH_STOP || cmdlen == 0 || buf == NULL) { 243 printf("dwhdmi_ddc_exec: bad args addr=%#x op=%#x cmdlen=%d buf=%p\n", 244 addr, op, (int)cmdlen, buf); 245 return ENXIO; 246 } 247 if (len > 256) { 248 printf("dwhdmi_ddc_exec: bad len %d\n", (int)len); 249 return ERANGE; 250 } 251 252 dwhdmi_write(sc, HDMI_I2CM_SOFTRSTZ, 0); 253 dwhdmi_write(sc, HDMI_IH_I2CM_STAT0, dwhdmi_read(sc, HDMI_IH_I2CM_STAT0)); 254 dwhdmi_write(sc, HDMI_I2CM_DIV, 0); 255 dwhdmi_write(sc, HDMI_I2CM_SLAVE, DDC_ADDR); 256 dwhdmi_write(sc, HDMI_I2CM_SEGADDR, DDC_SEGMENT_ADDR); 257 258 block = *(const uint8_t *)cmdbuf; 259 operation = block ? HDMI_I2CM_OPERATION_RD_EXT : HDMI_I2CM_OPERATION_RD; 260 off = (block & 1) ? 128 : 0; 261 262 for (n = 0; n < len; n++) { 263 dwhdmi_write(sc, HDMI_I2CM_ADDRESS, n + off); 264 dwhdmi_write(sc, HDMI_I2CM_OPERATION, operation); 265 for (retry = 10000; retry > 0; retry--) { 266 val = dwhdmi_read(sc, HDMI_IH_I2CM_STAT0); 267 if (val & HDMI_IH_I2CM_STAT0_ERROR) { 268 return EIO; 269 } 270 if (val & HDMI_IH_I2CM_STAT0_DONE) { 271 dwhdmi_write(sc, HDMI_IH_I2CM_STAT0, val); 272 break; 273 } 274 delay(1); 275 } 276 if (retry == 0) { 277 printf("dwhdmi_ddc_exec: timeout waiting for xfer, stat0=%#x\n", dwhdmi_read(sc, HDMI_IH_I2CM_STAT0)); 278 return ETIMEDOUT; 279 } 280 281 pbuf[n] = dwhdmi_read(sc, HDMI_I2CM_DATAI); 282 } 283 284 return 0; 285 } 286 287 uint8_t 288 dwhdmi_read(struct dwhdmi_softc *sc, bus_size_t reg) 289 { 290 uint8_t val; 291 292 switch (sc->sc_reg_width) { 293 case 1: 294 val = bus_space_read_1(sc->sc_bst, sc->sc_bsh, reg); 295 break; 296 case 4: 297 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg * 4) & 0xff; 298 break; 299 default: 300 val = 0; 301 break; 302 } 303 304 return val; 305 } 306 307 void 308 dwhdmi_write(struct dwhdmi_softc *sc, bus_size_t reg, uint8_t val) 309 { 310 switch (sc->sc_reg_width) { 311 case 1: 312 bus_space_write_1(sc->sc_bst, sc->sc_bsh, reg, val); 313 break; 314 case 4: 315 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg * 4, val); 316 break; 317 } 318 } 319 320 static void 321 dwhdmi_vp_init(struct dwhdmi_softc *sc) 322 { 323 uint8_t val; 324 325 /* Select 24-bits per pixel video, 8-bit packing mode and disable pixel repetition */ 326 val = __SHIFTIN(HDMI_VP_PR_CD_COLOR_DEPTH_24, HDMI_VP_PR_CD_COLOR_DEPTH) | 327 __SHIFTIN(HDMI_VP_PR_CD_DESIRED_PR_FACTOR_NONE, HDMI_VP_PR_CD_DESIRED_PR_FACTOR); 328 dwhdmi_write(sc, HDMI_VP_PR_CD, val); 329 330 /* Configure stuffing */ 331 val = HDMI_VP_STUFF_IDEFAULT_PHASE | 332 HDMI_VP_STUFF_YCC422_STUFFING | 333 HDMI_VP_STUFF_PP_STUFFING | 334 HDMI_VP_STUFF_PR_STUFFING; 335 dwhdmi_write(sc, HDMI_VP_STUFF, val); 336 337 /* Set YCC422 remap to 16-bit input video */ 338 val = __SHIFTIN(HDMI_VP_REMAP_YCC422_SIZE_16, HDMI_VP_REMAP_YCC422_SIZE); 339 dwhdmi_write(sc, HDMI_VP_REMAP, val); 340 341 /* Configure video packetizer */ 342 val = HDMI_VP_CONF_BYPASS_EN | 343 HDMI_VP_CONF_BYPASS_SELECT | 344 __SHIFTIN(HDMI_VP_CONF_OUTPUT_SELECT_BYPASS, HDMI_VP_CONF_OUTPUT_SELECT); 345 dwhdmi_write(sc, HDMI_VP_CONF, val); 346 } 347 348 static void 349 dwhdmi_tx_init(struct dwhdmi_softc *sc) 350 { 351 uint8_t val; 352 353 /* Disable internal data enable generator and set default video mapping */ 354 val = __SHIFTIN(HDMI_TX_INVID0_VIDEO_MAPPING_DEFAULT, HDMI_TX_INVID0_VIDEO_MAPPING); 355 dwhdmi_write(sc, HDMI_TX_INVID0, val); 356 357 /* Enable video sampler stuffing */ 358 val = HDMI_TX_INSTUFFING_BCBDATA_STUFFING | 359 HDMI_TX_INSTUFFING_RCRDATA_STUFFING | 360 HDMI_TX_INSTUFFING_GYDATA_STUFFING; 361 dwhdmi_write(sc, HDMI_TX_INSTUFFING, val); 362 } 363 364 static bool 365 dwhdmi_cea_mode_uses_fractional_vblank(uint8_t vic) 366 { 367 const uint8_t match[] = { 5, 6, 7, 10, 11, 20, 21, 22 }; 368 u_int n; 369 370 for (n = 0; n < __arraycount(match); n++) 371 if (match[n] == vic) 372 return true; 373 374 return false; 375 } 376 377 static void 378 dwhdmi_fc_init(struct dwhdmi_softc *sc, struct drm_display_mode *mode) 379 { 380 struct dwhdmi_connector *dwhdmi_connector = &sc->sc_connector; 381 uint8_t val; 382 383 const uint8_t vic = drm_match_cea_mode(mode); 384 const uint16_t inhactiv = mode->hdisplay; 385 const uint16_t inhblank = mode->htotal - mode->hdisplay; 386 const uint16_t invactiv = mode->vdisplay; 387 const uint8_t invblank = mode->vtotal - mode->vdisplay; 388 const uint16_t hsyncindelay = mode->hsync_start - mode->hdisplay; 389 const uint16_t hsyncinwidth = mode->hsync_end - mode->hsync_start; 390 const uint8_t vsyncindelay = mode->vsync_start - mode->vdisplay; 391 const uint8_t vsyncinwidth = mode->vsync_end - mode->vsync_start; 392 393 /* Input video configuration for frame composer */ 394 val = HDMI_FC_INVIDCONF_DE_IN_POLARITY; 395 if ((mode->flags & DRM_MODE_FLAG_PVSYNC) != 0) 396 val |= HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY; 397 if ((mode->flags & DRM_MODE_FLAG_PHSYNC) != 0) 398 val |= HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY; 399 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) != 0) 400 val |= HDMI_FC_INVIDCONF_IN_I_P; 401 if (dwhdmi_connector->hdmi_monitor) 402 val |= HDMI_FC_INVIDCONF_DVI_MODE; 403 if (dwhdmi_cea_mode_uses_fractional_vblank(vic)) 404 val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC; 405 dwhdmi_write(sc, HDMI_FC_INVIDCONF, val); 406 407 /* Input video mode timings */ 408 dwhdmi_write(sc, HDMI_FC_INHACTIV0, inhactiv & 0xff); 409 dwhdmi_write(sc, HDMI_FC_INHACTIV1, inhactiv >> 8); 410 dwhdmi_write(sc, HDMI_FC_INHBLANK0, inhblank & 0xff); 411 dwhdmi_write(sc, HDMI_FC_INHBLANK1, inhblank >> 8); 412 dwhdmi_write(sc, HDMI_FC_INVACTIV0, invactiv & 0xff); 413 dwhdmi_write(sc, HDMI_FC_INVACTIV1, invactiv >> 8); 414 dwhdmi_write(sc, HDMI_FC_INVBLANK, invblank); 415 dwhdmi_write(sc, HDMI_FC_HSYNCINDELAY0, hsyncindelay & 0xff); 416 dwhdmi_write(sc, HDMI_FC_HSYNCINDELAY1, hsyncindelay >> 8); 417 dwhdmi_write(sc, HDMI_FC_HSYNCINWIDTH0, hsyncinwidth & 0xff); 418 dwhdmi_write(sc, HDMI_FC_HSYNCINWIDTH1, hsyncinwidth >> 8); 419 dwhdmi_write(sc, HDMI_FC_VSYNCINDELAY, vsyncindelay); 420 dwhdmi_write(sc, HDMI_FC_VSYNCINWIDTH, vsyncinwidth); 421 422 /* Setup control period minimum durations */ 423 dwhdmi_write(sc, HDMI_FC_CTRLDUR, HDMI_FC_CTRLDUR_DEFAULT); 424 dwhdmi_write(sc, HDMI_FC_EXCTRLDUR, HDMI_FC_EXCTRLDUR_DEFAULT); 425 dwhdmi_write(sc, HDMI_FC_EXCTRLSPAC, HDMI_FC_EXCTRLSPAC_DEFAULT); 426 427 /* Setup channel preamble filters */ 428 dwhdmi_write(sc, HDMI_FC_CH0PREAM, HDMI_FC_CH0PREAM_DEFAULT); 429 dwhdmi_write(sc, HDMI_FC_CH1PREAM, HDMI_FC_CH1PREAM_DEFAULT); 430 dwhdmi_write(sc, HDMI_FC_CH2PREAM, HDMI_FC_CH2PREAM_DEFAULT); 431 } 432 433 static void 434 dwhdmi_mc_init(struct dwhdmi_softc *sc) 435 { 436 struct dwhdmi_connector *dwhdmi_connector = &sc->sc_connector; 437 uint8_t val; 438 u_int n, iter; 439 440 /* Bypass colour space converter */ 441 dwhdmi_write(sc, HDMI_MC_FLOWCTRL, 0); 442 443 /* Enable TMDS, pixel, and (if required) audio sampler clocks */ 444 val = HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 445 HDMI_MC_CLKDIS_CECCLK_DISABLE | 446 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 447 HDMI_MC_CLKDIS_PREPCLK_DISABLE; 448 if (!dwhdmi_connector->monitor_audio) 449 val |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 450 dwhdmi_write(sc, HDMI_MC_CLKDIS, val); 451 452 /* Soft reset TMDS */ 453 val = 0xff & ~HDMI_MC_SWRSTZREQ_TMDSSWRST_REQ; 454 dwhdmi_write(sc, HDMI_MC_SWRSTZREQ, val); 455 456 iter = sc->sc_version == 0x130a ? 4 : 1; 457 458 val = dwhdmi_read(sc, HDMI_FC_INVIDCONF); 459 for (n = 0; n < iter; n++) 460 dwhdmi_write(sc, HDMI_FC_INVIDCONF, val); 461 } 462 463 static void 464 dwhdmi_mc_disable(struct dwhdmi_softc *sc) 465 { 466 /* Disable clocks */ 467 dwhdmi_write(sc, HDMI_MC_CLKDIS, 0xff); 468 } 469 470 static enum drm_connector_status 471 dwhdmi_connector_detect(struct drm_connector *connector, bool force) 472 { 473 struct dwhdmi_connector *dwhdmi_connector = to_dwhdmi_connector(connector); 474 struct dwhdmi_softc * const sc = dwhdmi_connector->sc; 475 476 if (sc->sc_detect != NULL) 477 return sc->sc_detect(sc, force); 478 479 return connector_status_connected; 480 } 481 482 static void 483 dwhdmi_connector_destroy(struct drm_connector *connector) 484 { 485 drm_connector_unregister(connector); 486 drm_connector_cleanup(connector); 487 } 488 489 static const struct drm_connector_funcs dwhdmi_connector_funcs = { 490 .dpms = drm_helper_connector_dpms, 491 .detect = dwhdmi_connector_detect, 492 .fill_modes = drm_helper_probe_single_connector_modes, 493 .destroy = dwhdmi_connector_destroy, 494 }; 495 496 static int 497 dwhdmi_connector_get_modes(struct drm_connector *connector) 498 { 499 struct dwhdmi_connector *dwhdmi_connector = to_dwhdmi_connector(connector); 500 struct dwhdmi_softc * const sc = dwhdmi_connector->sc; 501 char edid[EDID_LENGTH * 4]; 502 struct edid *pedid = NULL; 503 int error, block; 504 505 memset(edid, 0, sizeof(edid)); 506 for (block = 0; block < 4; block++) { 507 error = ddc_read_edid_block(sc->sc_ic, 508 &edid[block * EDID_LENGTH], EDID_LENGTH, block); 509 if (error != 0) 510 break; 511 if (block == 0) { 512 pedid = (struct edid *)edid; 513 if (edid[0x7e] == 0) 514 break; 515 } 516 } 517 518 if (pedid) { 519 dwhdmi_connector->hdmi_monitor = drm_detect_hdmi_monitor(pedid); 520 dwhdmi_connector->monitor_audio = drm_detect_monitor_audio(pedid); 521 } else { 522 dwhdmi_connector->hdmi_monitor = false; 523 dwhdmi_connector->monitor_audio = false; 524 } 525 526 drm_mode_connector_update_edid_property(connector, pedid); 527 if (pedid == NULL) 528 return 0; 529 530 error = drm_add_edid_modes(connector, pedid); 531 drm_edid_to_eld(connector, pedid); 532 533 return error; 534 } 535 536 static struct drm_encoder * 537 dwhdmi_connector_best_encoder(struct drm_connector *connector) 538 { 539 int enc_id = connector->encoder_ids[0]; 540 struct drm_mode_object *obj; 541 struct drm_encoder *encoder = NULL; 542 543 if (enc_id) { 544 obj = drm_mode_object_find(connector->dev, enc_id, 545 DRM_MODE_OBJECT_ENCODER); 546 if (obj == NULL) 547 return NULL; 548 encoder = obj_to_encoder(obj); 549 } 550 551 return encoder; 552 } 553 554 static const struct drm_connector_helper_funcs dwhdmi_connector_helper_funcs = { 555 .get_modes = dwhdmi_connector_get_modes, 556 .best_encoder = dwhdmi_connector_best_encoder, 557 }; 558 559 static int 560 dwhdmi_bridge_attach(struct drm_bridge *bridge) 561 { 562 struct dwhdmi_softc * const sc = bridge->driver_private; 563 struct dwhdmi_connector *dwhdmi_connector = &sc->sc_connector; 564 struct drm_connector *connector = &dwhdmi_connector->base; 565 int error; 566 567 dwhdmi_connector->sc = sc; 568 569 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 570 connector->interlace_allowed = 0; 571 connector->doublescan_allowed = 0; 572 573 drm_connector_init(bridge->dev, connector, &dwhdmi_connector_funcs, 574 DRM_MODE_CONNECTOR_HDMIA); 575 drm_connector_helper_add(connector, &dwhdmi_connector_helper_funcs); 576 577 error = drm_mode_connector_attach_encoder(connector, bridge->encoder); 578 if (error != 0) 579 return error; 580 581 return drm_connector_register(connector); 582 } 583 584 static void 585 dwhdmi_bridge_enable(struct drm_bridge *bridge) 586 { 587 struct dwhdmi_softc * const sc = bridge->driver_private; 588 589 dwhdmi_vp_init(sc); 590 dwhdmi_fc_init(sc, &sc->sc_curmode); 591 592 if (sc->sc_enable) 593 sc->sc_enable(sc); 594 595 dwhdmi_tx_init(sc); 596 dwhdmi_mc_init(sc); 597 } 598 599 static void 600 dwhdmi_bridge_pre_enable(struct drm_bridge *bridge) 601 { 602 } 603 604 static void 605 dwhdmi_bridge_disable(struct drm_bridge *bridge) 606 { 607 struct dwhdmi_softc * const sc = bridge->driver_private; 608 609 if (sc->sc_disable) 610 sc->sc_disable(sc); 611 612 dwhdmi_mc_disable(sc); 613 } 614 615 static void 616 dwhdmi_bridge_post_disable(struct drm_bridge *bridge) 617 { 618 } 619 620 static void 621 dwhdmi_bridge_mode_set(struct drm_bridge *bridge, 622 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 623 { 624 struct dwhdmi_softc * const sc = bridge->driver_private; 625 626 if (sc->sc_mode_set) 627 sc->sc_mode_set(sc, mode, adjusted_mode); 628 629 sc->sc_curmode = *adjusted_mode; 630 } 631 632 static bool 633 dwhdmi_bridge_mode_fixup(struct drm_bridge *bridge, 634 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 635 { 636 return true; 637 } 638 639 static const struct drm_bridge_funcs dwhdmi_bridge_funcs = { 640 .attach = dwhdmi_bridge_attach, 641 .enable = dwhdmi_bridge_enable, 642 .pre_enable = dwhdmi_bridge_pre_enable, 643 .disable = dwhdmi_bridge_disable, 644 .post_disable = dwhdmi_bridge_post_disable, 645 .mode_set = dwhdmi_bridge_mode_set, 646 .mode_fixup = dwhdmi_bridge_mode_fixup, 647 }; 648 649 int 650 dwhdmi_attach(struct dwhdmi_softc *sc) 651 { 652 uint8_t val; 653 654 if (sc->sc_reg_width != 1 && sc->sc_reg_width != 4) { 655 aprint_error_dev(sc->sc_dev, "unsupported register width %d\n", sc->sc_reg_width); 656 return EINVAL; 657 } 658 659 mutex_init(&sc->sc_ic_lock, MUTEX_DEFAULT, IPL_NONE); 660 661 sc->sc_version = dwhdmi_read(sc, HDMI_DESIGN_ID); 662 sc->sc_version <<= 8; 663 sc->sc_version |= dwhdmi_read(sc, HDMI_REVISION_ID); 664 665 sc->sc_phytype = dwhdmi_read(sc, HDMI_CONFIG2_ID); 666 667 aprint_normal_dev(sc->sc_dev, "version %x.%03x, phytype 0x%02x\n", 668 sc->sc_version >> 12, sc->sc_version & 0xfff, 669 sc->sc_phytype); 670 671 /* 672 * If a DDC i2c bus tag is provided by the caller, use it. Otherwise, 673 * use the I2C master built-in to DWC HDMI. 674 */ 675 if (sc->sc_ic == NULL) { 676 struct i2c_controller *ic = &sc->sc_ic_builtin; 677 ic->ic_cookie = sc; 678 ic->ic_acquire_bus = dwhdmi_ddc_acquire_bus; 679 ic->ic_release_bus = dwhdmi_ddc_release_bus; 680 ic->ic_exec = dwhdmi_ddc_exec; 681 sc->sc_ic = ic; 682 } 683 684 /* 685 * Enable HPD on internal PHY 686 */ 687 if ((sc->sc_flags & DWHDMI_USE_INTERNAL_PHY) != 0) { 688 val = dwhdmi_read(sc, HDMI_PHY_CONF0); 689 val |= HDMI_PHY_CONF0_ENHPDRXSENSE; 690 dwhdmi_write(sc, HDMI_PHY_CONF0, val); 691 } 692 693 return 0; 694 } 695 696 int 697 dwhdmi_bind(struct dwhdmi_softc *sc, struct drm_encoder *encoder) 698 { 699 int error; 700 701 sc->sc_bridge.driver_private = sc; 702 sc->sc_bridge.funcs = &dwhdmi_bridge_funcs; 703 sc->sc_bridge.encoder = encoder; 704 705 error = drm_bridge_attach(encoder->dev, &sc->sc_bridge); 706 if (error != 0) 707 return EIO; 708 709 encoder->bridge = &sc->sc_bridge; 710 711 return 0; 712 } 713
Indexes created Wed Sep 24 15:09:51 GMT 2025