dwc_eqos_reg.h revision 1.1
1 /* $NetBSD: dwc_eqos_reg.h,v 1.1 2022/01/03 17:19:41 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2022 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * DesignWare Ethernet Quality-of-Service controller 31 */ 32 33 #ifndef _DWC_EQOS_REG_H 34 #define _DWC_EQOS_REG_H 35 36 #define GMAC_MAC_CONFIGURATION 0x0000 37 #define GMAC_MAC_CONFIGURATION_CST (1U << 21) 38 #define GMAC_MAC_CONFIGURATION_ACS (1U << 20) 39 #define GMAC_MAC_CONFIGURATION_BE (1U << 18) 40 #define GMAC_MAC_CONFIGURATION_JD (1U << 17) 41 #define GMAC_MAC_CONFIGURATION_JE (1U << 16) 42 #define GMAC_MAC_CONFIGURATION_PS (1U << 15) 43 #define GMAC_MAC_CONFIGURATION_FES (1U << 14) 44 #define GMAC_MAC_CONFIGURATION_DM (1U << 13) 45 #define GMAC_MAC_CONFIGURATION_DCRS (1U << 9) 46 #define GMAC_MAC_CONFIGURATION_TE (1U << 1) 47 #define GMAC_MAC_CONFIGURATION_RE (1U << 0) 48 #define GMAC_MAC_EXT_CONFIGURATION 0x0004 49 #define GMAC_MAC_PACKET_FILTER 0x0008 50 #define GMAC_MAC_PACKET_FILTER_HPF (1U << 10) 51 #define GMAC_MAC_PACKET_FILTER_PCF_MASK (3U << 6) 52 #define GMAC_MAC_PACKET_FILTER_PCF_ALL (2U << 6) 53 #define GMAC_MAC_PACKET_FILTER_DBF (1U << 5) 54 #define GMAC_MAC_PACKET_FILTER_PM (1U << 4) 55 #define GMAC_MAC_PACKET_FILTER_HMC (1U << 2) 56 #define GMAC_MAC_PACKET_FILTER_HUC (1U << 1) 57 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0) 58 #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C 59 #define GMAC_MAC_HASH_TABLE_REG0 0x0010 60 #define GMAC_MAC_HASH_TABLE_REG1 0x0014 61 #define GMAC_MAC_VLAN_TAG 0x0050 62 #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070 63 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 64 #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE (1U << 1) 65 #define GMAC_MAC_RX_FLOW_CTRL 0x0090 66 #define GMAC_MAC_RX_FLOW_CTRL_RFE (1U << 0) 67 #define GMAC_RXQ_CTRL0 0x00A0 68 #define GMAC_RXQ_CTRL0_EN_MASK 0x3 69 #define GMAC_RXQ_CTRL0_EN_DCB 0x2 70 #define GMAC_RXQ_CTRL1 0x00A4 71 #define GMAC_MAC_INTERRUPT_STATUS 0x00B0 72 #define GMAC_MAC_INTERRUPT_ENABLE 0x00B4 73 #define GMAC_MAC_RX_TX_STATUS 0x00B8 74 #define GMAC_MAC_PMT_CONTROL_STATUS 0x00C0 75 #define GMAC_MAC_RWK_PACKET_FILTER 0x00C4 76 #define GMAC_MAC_LPI_CONTROL_STATUS 0x00D0 77 #define GMAC_MAC_LPI_TIMERS_CONTROL 0x00D4 78 #define GMAC_MAC_LPI_ENTRY_TIMER 0x00D8 79 #define GMAC_MAC_1US_TIC_COUNTER 0x00DC 80 #define GMAC_MAC_PHYIF_CONTROL_STATUS 0x00F8 81 #define GMAC_MAC_VERSION 0x0110 82 #define GMAC_MAC_VERSION_USERVER_SHIFT 8 83 #define GMAC_MAC_VERSION_USERVER_MASK (0xFFU << GMAC_MAC_VERSION_USERVER_SHIFT) 84 #define GMAC_MAC_VERSION_SNPSVER_MASK 0xFFU 85 #define GMAC_MAC_DEBUG 0x0114 86 #define GMAC_MAC_HW_FEATURE(n) (0x011C + 0x4 * (n)) 87 #define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT 14 88 #define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) 89 #define GMAC_MAC_HW_FEATURE1_ADDR64_32BIT (0x0U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) 90 #define GMAC_MAC_MDIO_ADDRESS 0x0200 91 #define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT 21 92 #define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT 16 93 #define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT 8 94 #define GMAC_MAC_MDIO_ADDRESS_CR_MASK (0x7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 95 #define GMAC_MAC_MDIO_ADDRESS_CR_60_100 (0U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 96 #define GMAC_MAC_MDIO_ADDRESS_CR_100_150 (1U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 97 #define GMAC_MAC_MDIO_ADDRESS_CR_20_35 (2U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 98 #define GMAC_MAC_MDIO_ADDRESS_CR_35_60 (3U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 99 #define GMAC_MAC_MDIO_ADDRESS_CR_150_250 (4U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 100 #define GMAC_MAC_MDIO_ADDRESS_CR_250_300 (5U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 101 #define GMAC_MAC_MDIO_ADDRESS_CR_300_500 (6U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 102 #define GMAC_MAC_MDIO_ADDRESS_CR_500_800 (7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 103 #define GMAC_MAC_MDIO_ADDRESS_SKAP (1U << 4) 104 #define GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT 2 105 #define GMAC_MAC_MDIO_ADDRESS_GOC_READ (3U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT) 106 #define GMAC_MAC_MDIO_ADDRESS_GOC_WRITE (1U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT) 107 #define GMAC_MAC_MDIO_ADDRESS_C45E (1U << 1) 108 #define GMAC_MAC_MDIO_ADDRESS_GB (1U << 0) 109 #define GMAC_MAC_MDIO_DATA 0x0204 110 #define GMAC_MAC_CSR_SW_CTRL 0x0230 111 #define GMAC_MAC_ADDRESS0_HIGH 0x0300 112 #define GMAC_MAC_ADDRESS0_LOW 0x0304 113 #define GMAC_MMC_CONTROL 0x0700 114 #define GMAC_MMC_RX_INTERRUPT 0x0704 115 #define GMAC_MMC_TX_INTERRUPT 0x0708 116 #define GMAC_MMC_RX_INTERRUPT_MASK 0x070C 117 #define GMAC_MMC_TX_INTERRUPT_MASK 0x0710 118 #define GMAC_TX_OCTET_COUNT_GOOD_BAD 0x0714 119 #define GMAC_TX_PACKET_COUNT_GOOD_BAD 0x0718 120 #define GMAC_TX_UNDERFLOW_ERROR_PACKETS 0x0748 121 #define GMAC_TX_CARRIER_ERROR_PACKETS 0x0760 122 #define GMAC_TX_OCTET_COUNT_GOOD 0x0764 123 #define GMAC_TX_PACKET_COUNT_GOOD 0x0768 124 #define GMAC_RX_PACKETS_COUNT_GOOD_BAD 0x0780 125 #define GMAC_RX_OCTET_COUNT_GOOD_BAD 0x0784 126 #define GMAC_RX_OCTET_COUNT_GOOD 0x0788 127 #define GMAC_RX_MULTICAST_PACKETS_GOOD 0x0790 128 #define GMAC_RX_CRC_ERROR_PACKETS 0x0794 129 #define GMAC_RX_LENGTH_ERROR_PACKETS 0x07C8 130 #define GMAC_RX_FIFO_OVERFLOW_PACKETS 0x07D4 131 #define GMAC_MMC_IPC_RX_INTERRUPT_MASK 0x0800 132 #define GMAC_MMC_IPC_RX_INTERRUPT 0x0808 133 #define GMAC_RXIPV4_GOOD_PACKETS 0x0810 134 #define GMAC_RXIPV4_HEADER_ERROR_PACKETS 0x0814 135 #define GMAC_RXIPV6_GOOD_PACKETS 0x0824 136 #define GMAC_RXIPV6_HEADER_ERROR_PACKETS 0x0828 137 #define GMAC_RXUDP_ERROR_PACKETS 0x0834 138 #define GMAC_RXTCP_ERROR_PACKETS 0x083C 139 #define GMAC_RXICMP_ERROR_PACKETS 0x0844 140 #define GMAC_RXIPV4_HEADER_ERROR_OCTETS 0x0854 141 #define GMAC_RXIPV6_HEADER_ERROR_OCTETS 0x0868 142 #define GMAC_RXUDP_ERROR_OCTETS 0x0874 143 #define GMAC_RXTCP_ERROR_OCTETS 0x087C 144 #define GMAC_RXICMP_ERROR_OCTETS 0x0884 145 #define GMAC_MAC_TIMESTAMP_CONTROL 0x0B00 146 #define GMAC_MAC_SUB_SECOND_INCREMENT 0x0B04 147 #define GMAC_MAC_SYSTEM_TIME_SECS 0x0B08 148 #define GMAC_MAC_SYSTEM_TIME_NS 0x0B0C 149 #define GMAC_MAC_SYS_TIME_SECS_UPDATE 0x0B10 150 #define GMAC_MAC_SYS_TIME_NS_UPDATE 0x0B14 151 #define GMAC_MAC_TIMESTAMP_ADDEND 0x0B18 152 #define GMAC_MAC_TIMESTAMP_STATUS 0x0B20 153 #define GMAC_MAC_TX_TS_STATUS_NS 0x0B30 154 #define GMAC_MAC_TX_TS_STATUS_SECS 0x0B34 155 #define GMAC_MAC_AUXILIARY_CONTROL 0x0B40 156 #define GMAC_MAC_AUXILIARY_TS_NS 0x0B48 157 #define GMAC_MAC_AUXILIARY_TS_SECS 0x0B4C 158 #define GMAC_MAC_TS_INGRESS_CORR_NS 0x0B58 159 #define GMAC_MAC_TS_EGRESS_CORR_NS 0x0B5C 160 #define GMAC_MAC_TS_INGRESS_LATENCY 0x0B68 161 #define GMAC_MAC_TS_EGRESS_LATENCY 0x0B6C 162 #define GMAC_MAC_PPS_CONTROL 0x0B70 163 #define GMAC_MTL_DBG_CTL 0x0C08 164 #define GMAC_MTL_DBG_STS 0x0C0C 165 #define GMAC_MTL_FIFO_DEBUG_DATA 0x0C10 166 #define GMAC_MTL_INTERRUPT_STATUS 0x0C20 167 #define GMAC_MTL_TXQ0_OPERATION_MODE 0x0D00 168 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 169 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0x3U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) 170 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN (2U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) 171 #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF (1U << 1) 172 #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ (1U << 0) 173 #define GMAC_MTL_TXQ0_UNDERFLOW 0x0D04 174 #define GMAC_MTL_TXQ0_DEBUG 0x0D08 175 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS 0x0D2C 176 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE (1U << 24) 177 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS (1U << 16) 178 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE (1U << 8) 179 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS (1U << 0) 180 #define GMAC_MTL_RXQ0_OPERATION_MODE 0x0D30 181 #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF (1U << 5) 182 #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP (1U << 4) 183 #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP (1U << 3) 184 #define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT 0x0D34 185 #define GMAC_MTL_RXQ0_DEBUG 0x0D38 186 #define GMAC_DMA_MODE 0x1000 187 #define GMAC_DMA_MODE_SWR (1U << 0) 188 #define GMAC_DMA_SYSBUS_MODE 0x1004 189 #define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24 190 #define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0x3U << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) 191 #define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 192 #define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0x7U << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) 193 #define GMAC_DMA_SYSBUS_MODE_MB (1U << 14) 194 #define GMAC_DMA_SYSBUS_MODE_EAME (1U << 11) 195 #define GMAC_DMA_SYSBUS_MODE_BLEN16 (1U << 3) 196 #define GMAC_DMA_SYSBUS_MODE_BLEN8 (1U << 2) 197 #define GMAC_DMA_SYSBUS_MODE_BLEN4 (1U << 1) 198 #define GMAC_DMA_SYSBUS_MODE_FB (1U << 0) 199 #define GMAC_DMA_INTERRUPT_STATUS 0x1008 200 #define GMAC_DMA_DEBUG_STATUS0 0x100C 201 #define GMAC_AXI_LPI_ENTRY_INTERVAL 0x1040 202 #define GMAC_RWK_FILTERn_BYTE_MASK(n) (0x10C0 + 0x4 * (n)) 203 #define GMAC_RWK_FILTER01_CRC 0x10D0 204 #define GMAC_RWK_FILTER23_CRC 0x10D4 205 #define GMAC_RWK_FILTER_OFFSET 0x10D8 206 #define GMAC_RWK_FILTER_COMMAND 0x10DC 207 #define GMAC_DMA_CHAN0_CONTROL 0x1100 208 #define GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT 18 209 #define GMAC_DMA_CHAN0_CONTROL_DSL_MASK (0x7U << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT) 210 #define GMAC_DMA_CHAN0_CONTROL_PBLX8 (1U << 16) 211 #define GMAC_DMA_CHAN0_TX_CONTROL 0x1104 212 #define GMAC_DMA_CHAN0_TX_CONTROL_OSP (1U << 4) 213 #define GMAC_DMA_CHAN0_TX_CONTROL_START (1U << 0) 214 #define GMAC_DMA_CHAN0_RX_CONTROL 0x1108 215 #define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT 1 216 #define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK (0x3FFFU << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT) 217 #define GMAC_DMA_CHAN0_RX_CONTROL_START (1U << 0) 218 #define GMAC_DMA_CHAN0_TX_BASE_ADDR_HI 0x1110 219 #define GMAC_DMA_CHAN0_TX_BASE_ADDR 0x1114 220 #define GMAC_DMA_CHAN0_RX_BASE_ADDR_HI 0x1118 221 #define GMAC_DMA_CHAN0_RX_BASE_ADDR 0x111C 222 #define GMAC_DMA_CHAN0_TX_END_ADDR 0x1120 223 #define GMAC_DMA_CHAN0_RX_END_ADDR 0x1128 224 #define GMAC_DMA_CHAN0_TX_RING_LEN 0x112C 225 #define GMAC_DMA_CHAN0_RX_RING_LEN 0x1130 226 #define GMAC_DMA_CHAN0_INTR_ENABLE 0x1134 227 #define GMAC_DMA_CHAN0_INTR_ENABLE_NIE (1U << 15) 228 #define GMAC_DMA_CHAN0_INTR_ENABLE_AIE (1U << 14) 229 #define GMAC_DMA_CHAN0_INTR_ENABLE_FBE (1U << 12) 230 #define GMAC_DMA_CHAN0_INTR_ENABLE_RIE (1U << 6) 231 #define GMAC_DMA_CHAN0_INTR_ENABLE_TIE (1U << 0) 232 #define GMAC_DMA_CHAN0_RX_WATCHDOG 0x1138 233 #define GMAC_DMA_CHAN0_SLOT_CTRL_STATUS 0x113C 234 #define GMAC_DMA_CHAN0_CUR_TX_DESC 0x1144 235 #define GMAC_DMA_CHAN0_CUR_RX_DESC 0x114C 236 #define GMAC_DMA_CHAN0_CUR_TX_BUF_ADDR 0x1154 237 #define GMAC_DMA_CHAN0_CUR_RX_BUF_ADDR 0x115C 238 #define GMAC_DMA_CHAN0_STATUS 0x1160 239 #define GMAC_DMA_CHAN0_STATUS_NIS (1U << 15) 240 #define GMAC_DMA_CHAN0_STATUS_AIS (1U << 14) 241 #define GMAC_DMA_CHAN0_STATUS_FB (1U << 12) 242 #define GMAC_DMA_CHAN0_STATUS_RI (1U << 6) 243 #define GMAC_DMA_CHAN0_STATUS_TI (1U << 0) 244 245 struct eqos_dma_desc { 246 uint32_t tdes0; 247 uint32_t tdes1; 248 uint32_t tdes2; 249 #define EQOS_TDES2_IOC (1U << 31) /* TX */ 250 uint32_t tdes3; 251 #define EQOS_TDES3_OWN (1U << 31) /* TX and RX */ 252 #define EQOS_TDES3_IOC (1U << 30) /* RX */ 253 #define EQOS_TDES3_FD (1U << 29) /* TX */ 254 #define EQOS_TDES3_LD (1U << 28) /* TX */ 255 #define EQOS_TDES3_BUF1V (1U << 24) /* RX */ 256 #define EQOS_TDES3_DE (1U << 23) /* TX (WB) */ 257 #define EQOS_TDES3_ES (1U << 15) /* TX (WB) */ 258 #define EQOS_TDES3_LENGTH_MASK 0x7FFFU /* RX */ 259 } __aligned (64); 260 261 #endif /* !_DWC_EQOS_REG_H */ 262
Indexes created Tue Sep 30 11:09:46 GMT 2025