1 /* $NetBSD: mb86950reg.h,v 1.3 2005/12/11 12:21:27 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mika Kortelainen 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Mika Kortelainen 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Adapted from if_qnreg.h for the amiga port of NetBSD by Dave J. Barnes, 2004. 35 */ 36 37 /* 38 * The Fujitsu mb86950, "EtherStar", is the predecessor to the mb8696x 39 * NICE supported by the ate driver. While similar in function and 40 * programming to the mb8696x, the register offset differences and 41 * quirks make it nearly impossible to have one driver for both the 42 * EtherStar and NICE chips. 43 * 44 * Definitions from Fujitsu documentation. 45 */ 46 47 #define ESTAR_DLCR0 0 /* Transmit status */ 48 #define DLCR_TX_STAT ESTAR_DLCR0 49 50 #define ESTAR_DLCR1 1 /* Transmit masks */ 51 #define DLCR_TX_INT_EN ESTAR_DLCR1 52 53 /* DLCR0/1 - Transmit Status & Masks */ 54 #define TX_DONE 0x80 /* Transmit okay */ 55 /* bit 6 - Net Busy, carrier sense ? */ 56 /* bit 5 - Transmit packet received ? */ 57 #define TX_CR_LOST 0x10 /* Carrier lost while attempting to transmit */ 58 #define TX_UNDERFLO 0x08 /* fifo underflow */ 59 #define TX_COL 0x04 /* Collision */ 60 #define TX_16COL 0x02 /* 16 collision */ 61 #define TX_BUS_WR_ERR 0x01 /* Bus write error, fifo overflo */ 62 #define CLEAR_TX_ERR (TX_UNDERFLO | TX_COL | TX_16COL | TX_BUS_WR_ERR) /* Clear transmit errors */ 63 #define TX_MASK (TX_DONE | TX_16COL) 64 65 #define ESTAR_DLCR2 2 /* Receive status */ 66 #define DLCR_RX_STAT ESTAR_DLCR2 67 68 #define ESTAR_DLCR3 3 /* Receive masks */ 69 #define DLCR_RX_INT_EN ESTAR_DLCR3 70 71 /* DLCR2/3 - Receive Status & Masks */ 72 #define RX_PKT 0x80 /* Packet ready */ 73 #define RX_BUS_RD_ERR 0x40 /* fifo underflow, harmless, normally masked off */ 74 /* bit 5 - DMA end of process ? */ 75 /* bit 4 - remote control packet rx ? */ 76 #define RX_SHORT_ERR 0x08 /* Short packet */ 77 #define RX_ALIGN_ERR 0x04 /* Alignment error */ 78 #define RX_CRC_ERR 0x02 /* CRC error */ 79 #define RX_OVERFLO 0x01 /* Receive buf overflow */ 80 #define CLEAR_RX_ERR RX_MASK /* Clear receive and errors */ 81 #define RX_MASK (RX_PKT | RX_SHORT_ERR | RX_ALIGN_ERR | RX_CRC_ERR | RX_OVERFLO | RX_BUS_RD_ERR) 82 #define RX_ERR_MASK (RX_SHORT_ERR | RX_ALIGN_ERR | RX_CRC_ERR | RX_OVERFLO | RX_BUS_RD_ERR) 83 84 #define ESTAR_DLCR4 4 /* Transmit mode */ 85 #define DLCR_TX_MODE ESTAR_DLCR4 86 87 /* DLCR4 - Transmit Mode */ 88 /* bits 7, 6, 5, 4 - collision count ? */ 89 #define COL_MASK 0xf0 90 /* bit 3 - nc */ 91 /* bit 2 - gen output ? */ 92 #define LBC 0x02 /* Loopback control */ 93 /* bit 0 - defer ?, normally 0 */ 94 95 #define ESTAR_DLCR5 5 /* Receive mode */ 96 #define DLCR_RX_MODE ESTAR_DLCR5 97 98 /* DLCR5 - Receive Mode */ 99 /* Normal mode: accept physical address, broadcast address. 100 */ 101 /* bit 7 - Disable CRC test mode */ 102 #define RX_BUF_EMTY 0x40 /* Buffer empty */ 103 /* bit 5 - accept packet with errors or nc ?, normally set to 0 */ 104 /* bit 4 - 40 bit address ?, normally set to 0 */ 105 /* bit 3 - accept runts ?, normally set to 0 */ 106 /* bit 2 - remote reset ? normally set to 0 */ 107 /* bit 1 & 0 - address filter mode */ 108 109 /* 00 = reject */ 110 /* 01 = normal mode */ 111 #define NORMAL_MODE 0x01 112 /* 10 = ? */ 113 /* 11 = promiscuous mode */ 114 #define PROMISCUOUS_MODE 0x03 /* Accept all packets */ 115 116 #define ESTAR_DLCR6 6 /* Software reset */ 117 #define DLCR_CONFIG ESTAR_DLCR6 118 119 /* DLCR6 - Enable Data Link Controller */ 120 #define DISABLE_DLC 0x80 /* Disable data link controller */ 121 #define ENABLE_DLC 0x00 /* Enable data link controller */ 122 123 #define ESTAR_DLCR7 7 /* TDR (LSB) */ 124 125 #define ESTAR_DLCR8 8 /* Node ID0 */ 126 #define DLCR_NODE_ID ESTAR_DLCR8 127 128 #define ESTAR_DLCR9 9 /* Node ID1 */ 129 #define ESTAR_DLCR10 10 /* Node ID2 */ 130 #define ESTAR_DLCR11 11 /* Node ID3 */ 131 #define ESTAR_DLCR12 12 /* Node ID4 */ 132 #define ESTAR_DLCR13 13 /* Node ID5 */ 133 134 #define ESTAR_DLCR15 15 /* TDR (MSB) */ 135 136 /* The next three are usually accessed as words */ 137 #define ESTAR_BMPR0 16 /* Buffer memory port (FIFO) */ 138 #define BMPR_FIFO ESTAR_BMPR0 139 140 #define ESTAR_BMPR2 18 /* Packet length */ 141 #define BMPR_TX_LENGTH ESTAR_BMPR2 142 /* BMPR2:BMPR3 - Packet Length Registers (Write-only) */ 143 #define TRANSMIT_START 0x8000 144 145 #define ESTAR_BMPR4 20 /* DMA enable */ 146 #define BMPR_DMA ESTAR_BMPR4 147
Indexes created Sat Sep 20 22:09:52 GMT 2025