1 /* $NetBSD: mc68450reg.h,v 1.6 2024/10/05 20:20:38 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Motorola MC68450 DMAC register definition. 34 */ 35 36 #define DMAC_NCHAN 4 /* Number of channels */ 37 #define DMAC_CHAN_SIZE 0x40 /* I/O area size per channel */ 38 39 /* register location per channel */ 40 #define DMAC_REG_CSR 0x00 /* Channel Status Register */ 41 #define DMAC_REG_CER 0x01 /* Channel Error Register */ 42 #define DMAC_REG_DCR 0x04 /* Device Control Register */ 43 #define DMAC_REG_OCR 0x05 /* Operation Control Register */ 44 #define DMAC_REG_SCR 0x06 /* Sequence Control Register */ 45 #define DMAC_REG_CCR 0x07 /* Channel Control Register */ 46 #define DMAC_REG_MTCR 0x0a /* Memory Transfer Count Register */ 47 #define DMAC_REG_MAR 0x0c /* Memory Address Register */ 48 #define DMAC_REG_DAR 0x14 /* Device Address Register */ 49 #define DMAC_REG_BTCR 0x1a /* Base Transfer Count Register */ 50 #define DMAC_REG_BAR 0x1c /* Base Address Register */ 51 #define DMAC_REG_NIVR 0x25 /* Normal Interrupt Vector Register */ 52 #define DMAC_REG_EIVR 0x27 /* Error Interrupt Vector Register */ 53 #define DMAC_REG_MFCR 0x29 /* Memory Function Code Register */ 54 #define DMAC_REG_CPR 0x2d /* Channel Priority Register */ 55 #define DMAC_REG_DFCR 0x31 /* Device Function Code Register */ 56 #define DMAC_REG_BFCR 0x39 /* Base Function Code Register */ 57 #define DMAC_REG_GCR 0x3f /* General Control Register */ 58 59 /* CSR bits */ 60 #define DMAC_CSR_COC 0x80 /* Channel Operation Complete */ 61 #define DMAC_CSR_BTC 0x40 /* Block Transfer Complete */ 62 #define DMAC_CSR_NDT 0x20 /* Normal Device Termination */ 63 #define DMAC_CSR_ERR 0x10 /* Error */ 64 #define DMAC_CSR_ACT 0x08 /* Channel Active */ 65 #define DMAC_CSR_PCT 0x02 /* PCL Transition */ 66 #define DMAC_CSR_PCS 0x01 /* PCL Level */ 67 68 /* CER meanings */ 69 /* 70 * 0x00: No error 71 * 0x01: Configuration error 72 * 0x02: Operation timing error 73 * 0x05: Address error in memory transfer 74 * 0x06: Address error in device transfer 75 * 0x07: Address error in base address reading 76 * 0x09: Bus error in memory transfer 77 * 0x0a: Bus error in device transfer 78 * 0x0b: Bus error in base address reading 79 * 0x0d: Count error in memory transfer count 80 * 0x0e: Count error in device transfer count 81 * 0x0f: Count error in base address 82 * 0x10: External abort 83 * 0x11: Software abort 84 */ 85 86 /* DCR bits */ 87 #define DMAC_DCR_XRM_MASK 0xc0 88 #define DMAC_DCR_XRM_BURST 0x00 /* Burst mode */ 89 #define DMAC_DCR_XRM_CSWOH 0x80 /* Cycle steal w/o hold */ 90 #define DMAC_DCR_XRM_CSWH 0xc0 /* Cycle steal w/ hold */ 91 #define DMAC_DCR_OTYP_MASK 0x30 92 #define DMAC_DCR_OTYP_EASYNC 0x00 /* Explicit M68000 */ 93 #define DMAC_DCR_OTYP_ESYNC 0x10 /* Explicit M6800 */ 94 #define DMAC_DCR_OTYP_IA 0x20 /* Implicit with ack */ 95 #define DMAC_DCR_OTYP_IAR 0x30 /* Implicit with ack and rdy */ 96 #define DMAC_DCR_OPS_MASK 0x08 97 #define DMAC_DCR_OPS_8BIT 0x00 /* 8bit */ 98 #define DMAC_DCR_OPS_16BIT 0x08 /* 16bit */ 99 #define DMAC_DCR_PCL_MASK 0x03 100 #define DMAC_DCR_PCL_STATUS 0x00 101 #define DMAC_DCR_PCL_INTERRUPT 0x01 102 #define DMAC_DCR_PCL_STARTPLS 0x02 103 #define DMAC_DCR_PCL_ABORT 0x03 104 105 /* OCR bits */ 106 #define DMAC_OCR_DIR_MASK 0x80 107 #define DMAC_OCR_DIR_MTD 0x00 /* Direction: memory to device */ 108 #define DMAC_OCR_DIR_DTM 0x80 /* Direction: device to memory */ 109 #define DMAC_OCR_SIZE_MASK 0x30 110 #define DMAC_OCR_SIZE_BYTE 0x00 /* Size: byte */ 111 #define DMAC_OCR_SIZE_WORD 0x10 /* Size: word */ 112 #define DMAC_OCR_SIZE_LONGWORD 0x20 /* Size: longword */ 113 #define DMAC_OCR_SIZE_BYTE_NOPACK 0x30 /* Size: byte, no packing */ 114 #define DMAC_OCR_CHAIN_MASK 0x0c 115 #define DMAC_OCR_CHAIN_DISABLED 0x00 /* Chain mode disabled */ 116 #define DMAC_OCR_CHAIN_ARRAY 0x08 /* Array chain mode */ 117 #define DMAC_OCR_CHAIN_LINKARRAY 0x0c /* Linked array chain mode */ 118 #define DMAC_OCR_REQG_MASK 0x03 119 #define DMAC_OCR_REQG_LIMITED_RATE 0x00 /* Internal limited rate */ 120 #define DMAC_OCR_REQG_MAXIMUM_RATE 0x01 /* Internal maximum rate */ 121 #define DMAC_OCR_REQG_EXTERNAL 0x02 /* External */ 122 #define DMAC_OCR_REQG_AUTO_START 0x03 /* Auto start, external */ 123 124 /* SCR bits */ 125 #define DMAC_SCR_MAC_MASK 0x0c 126 #define DMAC_SCR_MAC_NO_COUNT 0x00 /* Fixed memory address */ 127 #define DMAC_SCR_MAC_COUNT_UP 0x04 /* Memory address count up */ 128 #define DMAC_SCR_MAC_COUNT_DOWN 0x08 /* Memory address count down */ 129 #define DMAC_SCR_DAC_MASK 0x03 130 #define DMAC_SCR_DAC_NO_COUNT 0x00 /* Fixed device address */ 131 #define DMAC_SCR_DAC_COUNT_UP 0x01 /* Device address count up */ 132 #define DMAC_SCR_DAC_COUNT_DOWN 0x02 /* Device address count down */ 133 134 /* CCR bits */ 135 #define DMAC_CCR_STR 0x80 /* Start channel */ 136 #define DMAC_CCR_CNT 0x40 /* Continue operation */ 137 #define DMAC_CCR_HLT 0x20 /* Software halt */ 138 #define DMAC_CCR_SAB 0x10 /* Software abort */ 139 #define DMAC_CCR_INT 0x08 /* Interrupt enable */ 140 141 /* GCR bits */ 142 #define DMAC_GCR_BT_MASK 0x0c 143 #define DMAC_GCR_BT_16 0x00 /* 16clocks */ 144 #define DMAC_GCR_BT_32 0x04 /* 32clocks */ 145 #define DMAC_GCR_BT_64 0x08 /* 64clocks */ 146 #define DMAC_GCR_BT_128 0x0c /* 128clocks */ 147 #define DMAC_GCR_BR_MASK 0x03 148 #define DMAC_GCR_BR_50 0x00 /* 50% bandwidth */ 149 #define DMAC_GCR_BR_25 0x01 /* 25% bandwidth */ 150 #define DMAC_GCR_BR_12 0x02 /* 12.5% bandwidth */ 151 #define DMAC_GCR_BR_6 0x03 /* 6.25% bandwidth */ 152 153 /* MFC/DFC function codes */ 154 #define DMAC_FC_USER_DATA 0x01 155 #define DMAC_FC_USER_PROGRAM 0x02 156 #define DMAC_FC_KERNEL_DATA 0x05 157 #define DMAC_FC_KERNEL_PROGRAM 0x06 158 #define DMAC_FC_CPU 0x07 159 160 /* 161 * An element of the array used in DMAC scatter-gather transfer 162 * (array chaining mode) 163 */ 164 struct dmac_sg_array { 165 u_int32_t da_addr; 166 u_int16_t da_count; 167 }; 168
Indexes created Sat Sep 20 22:09:52 GMT 2025