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      1 /* $NetBSD: nec71071reg.h,v 1.1 2006/10/01 12:39:35 bjh21 Exp $ */
      2 
      3 /*
      4  * Ben Harris 2006
      5  *
      6  * This file is in the public domain.
      7  */
      8 
      9 /*
     10  * NEC uPD71071 DMA Controller
     11  * register definitions
     12  */
     13 
     14 /*
     15  * This chip is suspiciously much like the Intel 8237, but not actually
     16  * compatible with it.
     17  */
     18 
     19 /* Register offsets */
     20 
     21 #define NEC71071_INIT		0x0  /* Initialize */
     22 #define		 INIT_RES	0x01 /* Reset */
     23 #define		 INIT_16B	0x02 /* 16-bit data bus */
     24 #define NEC71071_CHANNEL	0x1  /* Channel Register Read/Write */
     25 #define		 CHANNEL_SEL0	0x01 /* Channel 0 selected (R) */
     26 #define		 CHANNEL_SEL1	0x02 /* Channel 1 selected (R) */
     27 #define		 CHANNEL_SEL2	0x04 /* Channel 2 selected (R) */
     28 #define		 CHANNEL_SEL3	0x08 /* Channel 3 selected (R) */
     29 #define		 CHANNEL_RBASE	0x10 /* Only base registers may be accessed */
     30 #define		 CHANNEL_SELCH	0x03 /* Channel to select (W) */
     31 #define		 CHANNEL_WBASE	0x04 /* Only base registers may be accessed */
     32 #define NEC71071_COUNTLO	0x2  /* Count register, low byte */
     33 #define NEC71071_COUNTHI	0x3  /* Count register, high byte */
     34 #define NEC71071_ADDRLO		0x4  /* Address register, low byte */
     35 #define NEC71071_ADDRMID	0x5  /* Address register, middle byte */
     36 #define NEC71071_ADDRHI		0x6  /* Address register, high byte */
     37 #define NEC71071_DCTRL1		0x8  /* Device control register, low byte */
     38 #define		 DCTRL1_MTM	0x01 /* Memory-to-Memory */
     39 #define		 DCTRL1_AHLD	0x02 /* Fixed Address */
     40 #define		 DCTRL1_DDMA	0x04 /* Disable DMA Operation */
     41 #define		 DCTRL1_CMP	0x08 /* Compressed Timing */
     42 #define		 DCTRL1_ROT	0x10 /* Rotational Priority */
     43 #define		 DCTRL1_EXW	0x20 /* Extended Writing */
     44 #define		 DCTRL1_RQL	0x40 /* DMARQ active low */
     45 #define		 DCTRL1_AKL	0x80 /* DMAAK active high */
     46 #define NEC71071_DCTRL2		0x9  /* Device control register, high byte */
     47 #define		 DCTRL2_BHLD	0x01 /* Bus Hold mode */
     48 #define		 DCTRL2_WEV	0x02 /* Write Enable During Verify */
     49 #define NEC71071_MODE		0xA  /* Mode control register */
     50 #define		 MODE_WNB	0x01 /* Word (not byte) transfer */
     51 #define		 MODE_TDIR	0x0c /* Transfer direction */
     52 #define		 MODE_TDIR_VRFY	0x00 /* Verify */
     53 #define		 MODE_TDIR_IOTM	0x04 /* I/O to memory */
     54 #define		 MODE_TDIR_MTIO	0x08 /* memory to I/O */
     55 #define		 MODE_AUTI	0x10 /* Autoinitialize */
     56 #define		 MODE_ADIR	0x20 /* Address direction (decrement) */
     57 #define		 MODE_TMODE	0xc0 /* Transfer mode */
     58 #define		 MODE_TMODE_DMD	0x00 /* Demand mode */
     59 #define		 MODE_TMODE_SGL 0x40 /* Single mode */
     60 #define		 MODE_TMODE_BLK	0x80 /* Block mode */
     61 #define		 MODE_TMODE_CAS 0xc0 /* Cascade mode */
     62 #define NEC71071_STATUS		0xB  /* Status register */
     63 #define		 STATUS_TC	0x0f /* Terminal count (one per channel) */
     64 #define		 STATUS_RQ	0xf0 /* DMA Request active (one per channel) */
     65 #define NEC71071_TEMPLO		0xC  /* Temporary register (low byte) */
     66 #define NEC71071_TEMPHI		0xD  /* Temporary register (high byte) */
     67 #define NEC71071_REQUEST	0xE  /* Request register (one bit/channel) */
     68 #define NEC71071_MASK		0xF  /* Mask register (one bit/channel) */
     69 
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