1 /* $NetBSD: ns8477reg.h,v 1.3 2008/04/28 20:23:50 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Christos Zoulas. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Register descriptions of the National Semiconductor PC8477B 34 * floppy controller 35 */ 36 37 #define FDC_SRA 0 /* (R) Status Register A */ 38 39 #define FDC_SRB 1 /* (R) Status Register B */ 40 41 #define FDC_DOR 2 /* (R/W) Digital Output Register */ 42 43 # define FDC_DOR_SEL0 0x01 /* Drive Select 0 */ 44 # define FDC_DOR_SEL1 0x02 /* Drive Select 1 */ 45 # define FDC_DOR_RESET 0x04 /* Reset Controller */ 46 # define FDC_DOR_DMAEN 0x08 /* Dma Enable */ 47 # define FDC_DOR_MTR0 0x10 /* Motor Enable 0 */ 48 # define FDC_DOR_MTR1 0x20 /* Motor Enable 1 */ 49 # define FDC_DOR_MTR2 0x40 /* Motor Enable 2 */ 50 # define FDC_DOR_MTR3 0x80 /* Motor Enable 3 */ 51 # define FDC_DOR_MTR(a) (1 << (n + 4)) 52 53 #define FDC_TDR 3 /* (R/W) Tape Drive Register */ 54 # define FDC_TDR_SEL0 0x01 /* Tape Select 0 */ 55 # define FDC_TDR_SEL1 0x02 /* Tape Select 1 */ 56 57 #define FDC_MSR 4 /* (R) Main Status Register */ 58 # define FDC_MSR_BUSY0 0x01 /* Drive 0 Busy */ 59 # define FDC_MSR_BUSY1 0x02 /* Drive 1 Busy */ 60 # define FDC_MSR_BUSY2 0x04 /* Drive 2 Busy */ 61 # define FDC_MSR_BUSY3 0x08 /* Drive 3 Busy */ 62 # define FDC_MSR_CMDPRG 0x10 /* Command In Progress */ 63 # define FDC_MSR_NONDMA 0x20 /* Non DMA Execution */ 64 # define FDC_MSR_DIO 0x40 /* Data I/O Direction */ 65 # define FDC_MSR_RQM 0x80 /* Reguest for Master */ 66 67 #define FDC_DSR 4 /* (W) Data Rate Select Register */ 68 # define FDC_DSR_DRATE0 0x01 /* Data Rate Select 0 */ 69 # define FDC_DSR_DRATE1 0x02 /* Data Rate Select 0 */ 70 /* 71 * bit MFM FM 72 * 00 500Kb/s 250Kb/s 73 * 01 300Kb/s 150Kb/s 74 * 10 250Kb/s 125Kb/s 75 * 11 1Mb/s illegal 76 */ 77 # define FDC_DSR_500KBPS 0x00 /* 500KBPS MFM drive transfer rate */ 78 # define FDC_DSR_300KBPS 0x01 /* 300KBPS MFM drive transfer rate */ 79 # define FDC_DSR_250KBPS 0x02 /* 250KBPS MFM drive transfer rate */ 80 # define FDC_DSR_1MBPS 0x03 /* 1MBPS MFM drive transfer rate */ 81 82 # define FDC_DSR_PREC0 0x04 /* Precompensation bit 0*/ 83 # define FDC_DSR_PREC1 0x08 /* Precompensation bit 1*/ 84 # define FDC_DSR_PREC2 0x10 /* Precompensation bit 2*/ 85 /* 86 * bit Precomp Data Rate 87 * 000 default 88 * 001 41.7ns 1Mb/s 89 * 010 83.3ns 90 * 011 125.0ns 500Kb/s, 300Kb/s, 250Kb/s 91 * 100 168.7ns 92 * 101 208.3ns 93 * 110 208.3ns 94 * 111 0.0ns 95 */ 96 # define FDC_DSR_ZERO 0x20 /* Undef; should be 0 */ 97 # define FDC_DSR_LOWPWR 0x40 /* Low Power Mode */ 98 # define FDC_DSR_SWRST 0x80 /* Software Reset */ 99 100 #define FDC_FIFO 5 /* (R/W) Data Register (FIFO) */ 101 102 /* 103 * Commands 104 */ 105 #define FDC_CMD_MODE (0x01) 106 #define FDC_CMD_READ_TRACK(mfm) (0x02|mfm) 107 #define FDC_CMD_SPECIFY (0x03) 108 #define FDC_CMD_SENSE_DRIVE_STATUS (0x04) 109 #define FDC_CMD_WRITE_DATA(mt,mfm) (0x05|mt|mfm) 110 #define FDC_CMD_READ_DATA(mt,mfm,sk) (0x06|mt|mfm|sk) 111 #define FDC_CMD_RECALIBRATE (0x07) 112 #define FDC_CMD_SENSE_INTERRUPT (0x08) 113 #define FDC_CMD_WRITE_DEL_DATA(mt,mfm) (0x09|mt|mfm) 114 #define FDC_CMD_READ_ID(mfm) (0x0a|mfm) 115 #define FDC_CMD_READ_DEL_DATA(mt,mfm,sk) (0x0c|mt|mfm|sk) 116 #define FDC_CMD_FORMAT_TRACK(mfm) (0x0d|mfm) 117 #define FDC_CMD_DUMPREG (0x0e) 118 #define FDC_CMD_SEEK (0x0f) 119 #define FDC_CMD_VERSION (0x10) 120 #define FDC_CMD_SCAN_EQUAL(mt,mfm,sk) (0x11|mt|mfm|sk) 121 #define FDC_CMD_PERPENDICULAR (0x12) 122 #define FDC_CMD_CONFIGURE (0x13) 123 #define FDC_CMD_LOCK(lock) (0x14|lock) 124 #define FDC_CMD_VERIFY(mt,mfm,sk) (0x16|mt|mfm|sk) 125 #define FDC_CMD_NSC (0x18) 126 #define FDC_CMD_SCAN_LO_EQUAL(mt,mfm,sk) (0x19|mt|mfm|sk) 127 #define FDC_CMD_SCAN_HI_EQUAL(mt,mfm,sk) (0x1d|mt|mfm|sk) 128 #define FDC_CMD_SET_TRACK(wnr) (0x21|wnr) 129 #define FDC_CMD_REL_SEEK(dir) (0x8f|dir) 130 131 #define FDC_CMD_CONFIGURE_FLAGS_POLL 0x10 132 #define FDC_CMD_CONFIGURE_FLAGS_FIFO 0x20 133 #define FDC_CMD_CONFIGURE_FLAGS_EIS 0x40 134 #define FDC_CMD_FLAGS_LOCK 0x80 135 #define FDC_CMD_FLAGS_MT 0x80 136 #define FDC_CMD_FLAGS_MFM 0x40 137 #define FDC_CMD_FLAGS_SK 0x20 138 #define FDC_CMD_FLAGS_DIR 0x40 139 #define FDC_CMD_FLAGS_WNR 0x40 140 /* 141 * Command Status 142 */ 143 /* Status register ST0 */ 144 #define FDC_ST0BITS "\020\010invld\007abnrml\006seek_cmplt\005drv_chck\004drive_rdy\003top_head\002ds1\001ds0" 145 # define FDC_ST0_DS0 0x01 /* Drive Select 0 */ 146 # define FDC_ST0_DS1 0x02 /* Drive Select 1 */ 147 # define FDC_ST0_HDS 0x04 /* Head select */ 148 # define FDC_ST0_ZERO 0x08 /* Undef; should be 0 */ 149 # define FDC_ST0_EC 0x10 /* Equipment check */ 150 # define FDC_ST0_SE 0x20 /* Seek completed */ 151 # define FDC_ST0_IC0 0x40 /* Interrupt code 0 */ 152 # define FDC_ST0_IC1 0x80 /* Interrupt code 1 */ 153 # define FDC_ST0(a) (a & ~(FDC_ST0_DS0|FDC_ST0_DS1|FDC_ST0_HDS)) 154 # define FDC_ST0_NRML 0x00 /* Normal Completion */ 155 # define FDC_ST0_ABNR 0x40 /* Abnormal Termination */ 156 # define FDC_ST0_INVL 0x80 /* Invalid Command */ 157 # define FDC_ST0_CHGD 0xc0 /* Drive status changed */ 158 159 /* Status register ST1 */ 160 #define FDC_ST1BITS "\020\010end_of_cyl\006bad_crc\005data_overrun\003sec_not_fnd\002write_protect\001no_am" 161 # define FDC_ST1_MA 0x01 /* Missing address mark */ 162 # define FDC_ST1_NW 0x02 /* Write Protect */ 163 # define FDC_ST1_ND 0x04 /* No Data */ 164 # define FDC_ST1_ZERO0 0x08 /* Undef; should be 0 */ 165 # define FDC_ST1_OR 0x10 /* Overrun error */ 166 # define FDC_ST1_CE 0x20 /* CRC error */ 167 # define FDC_ST1_ZERO1 0x40 /* Undef; should be 0 */ 168 # define FDC_ST1_ET 0x80 /* End of Track */ 169 170 /* Status register ST2 */ 171 #define FDC_ST2BITS "\020\007ctrl_mrk\006bad_crc\005wrong_cyl\004scn_eq\003scn_not_fnd\002bad_cyl\001no_dam" 172 # define FDC_ST2_MD 0x01 /* Missing Address Mark */ 173 # define FDC_ST2_BT 0x02 /* Bad Track */ 174 # define FDC_ST2_SNS 0x04 /* Scan Not Satisfied */ 175 # define FDC_ST2_SEH 0x08 /* Scan Equal Hit */ 176 # define FDC_ST2_WT 0x10 /* Wrong Track */ 177 # define FDC_ST2_CD 0x20 /* CRC Error in Data */ 178 # define FDC_ST2_CM 0x40 /* Control Mark */ 179 # define FDC_ST2_ZERO 0x80 /* Undef; should be 0 */ 180 181 /* Status register ST3 */ 182 #define FDC_ST3BITS "\020\010fault\007write_protect\006drdy\005tk0\004two_side\003side_sel\002ds1\001ds0" 183 # define FDC_ST3_DS0 0x01 /* Drive Select 0 */ 184 # define FDC_ST3_DS1 0x02 /* Drive Select 1 */ 185 # define FDC_ST3_HDS 0x04 /* Head Select */ 186 # define FDC_ST3_ONE0 0x08 /* Undef; should be 0 */ 187 # define FDC_ST3_TK0 0x10 /* Track 0 */ 188 # define FDC_ST3_ONE1 0x20 /* Undef; should be 0 */ 189 # define FDC_ST3_WP 0x40 /* Write Protect */ 190 # define FDC_ST3_ZERO 0x80 /* Undef; should be 0 */ 191 192 #define FDC_NONE 6 /* (X) None (Bus TRI-STATE) */ 193 194 #define FDC_DIR 7 /* (R) Digital Input Register */ 195 # define FDC_DIR_DSKCHG 0x80 /* Disk Changed */ 196 197 #define FDC_CCR 7 /* (W) Configuration Register */ 198 # define FDC_CCR_DRATE0 0x01 /* Data Rate Select 0 */ 199 # define FDC_CCR_DRATE1 0x02 /* Data Rate Select 0 */ 200 # define FDC_CCR_ZERO0 0x04 /* Undef; should be 0 */ 201 # define FDC_CCR_ZERO1 0x08 /* Undef; should be 0 */ 202 # define FDC_CCR_ZERO2 0x10 /* Undef; should be 0 */ 203 # define FDC_CCR_ZERO3 0x20 /* Undef; should be 0 */ 204 # define FDC_CCR_ZERO4 0x40 /* Undef; should be 0 */ 205 # define FDC_CCR_ZERO5 0x80 /* Undef; should be 0 */ 206 207 #define FDC_NPORT 8 208
Indexes created Sat Sep 20 22:09:52 GMT 2025