ns8477reg.h revision 1.2
1 /* $NetBSD: ns8477reg.h,v 1.2 1998/09/05 14:20:01 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Christos Zoulas. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Register descriptions of the National Semiconductor PC8477B 41 * floppy controller 42 */ 43 44 #define FDC_SRA 0 /* (R) Status Register A */ 45 46 #define FDC_SRB 1 /* (R) Status Register B */ 47 48 #define FDC_DOR 2 /* (R/W) Digital Output Register */ 49 50 # define FDC_DOR_SEL0 0x01 /* Drive Select 0 */ 51 # define FDC_DOR_SEL1 0x02 /* Drive Select 1 */ 52 # define FDC_DOR_RESET 0x04 /* Reset Controller */ 53 # define FDC_DOR_DMAEN 0x08 /* Dma Enable */ 54 # define FDC_DOR_MTR0 0x10 /* Motor Enable 0 */ 55 # define FDC_DOR_MTR1 0x20 /* Motor Enable 1 */ 56 # define FDC_DOR_MTR2 0x40 /* Motor Enable 2 */ 57 # define FDC_DOR_MTR3 0x80 /* Motor Enable 3 */ 58 # define FDC_DOR_MTR(a) (1 << (n + 4)) 59 60 #define FDC_TDR 3 /* (R/W) Tape Drive Register */ 61 # define FDC_TDR_SEL0 0x01 /* Tape Select 0 */ 62 # define FDC_TDR_SEL1 0x02 /* Tape Select 1 */ 63 64 #define FDC_MSR 4 /* (R) Main Status Register */ 65 # define FDC_MSR_BUSY0 0x01 /* Drive 0 Busy */ 66 # define FDC_MSR_BUSY1 0x02 /* Drive 1 Busy */ 67 # define FDC_MSR_BUSY2 0x04 /* Drive 2 Busy */ 68 # define FDC_MSR_BUSY3 0x08 /* Drive 3 Busy */ 69 # define FDC_MSR_CMDPRG 0x10 /* Command In Progress */ 70 # define FDC_MSR_NONDMA 0x20 /* Non DMA Execution */ 71 # define FDC_MSR_DIO 0x40 /* Data I/O Direction */ 72 # define FDC_MSR_RQM 0x80 /* Reguest for Master */ 73 74 #define FDC_DSR 4 /* (W) Data Rate Select Register */ 75 # define FDC_DSR_DRATE0 0x01 /* Data Rate Select 0 */ 76 # define FDC_DSR_DRATE1 0x02 /* Data Rate Select 0 */ 77 /* 78 * bit MFM FM 79 * 00 500Kb/s 250Kb/s 80 * 01 300Kb/s 150Kb/s 81 * 10 250Kb/s 125Kb/s 82 * 11 1Mb/s illegal 83 */ 84 # define FDC_DSR_500KBPS 0x00 /* 500KBPS MFM drive transfer rate */ 85 # define FDC_DSR_300KBPS 0x01 /* 300KBPS MFM drive transfer rate */ 86 # define FDC_DSR_250KBPS 0x02 /* 250KBPS MFM drive transfer rate */ 87 # define FDC_DSR_1MBPS 0x03 /* 1MBPS MFM drive transfer rate */ 88 89 # define FDC_DSR_PREC0 0x04 /* Precompensation bit 0*/ 90 # define FDC_DSR_PREC1 0x08 /* Precompensation bit 1*/ 91 # define FDC_DSR_PREC2 0x10 /* Precompensation bit 2*/ 92 /* 93 * bit Precomp Data Rate 94 * 000 default 95 * 001 41.7ns 1Mb/s 96 * 010 83.3ns 97 * 011 125.0ns 500Kb/s, 300Kb/s, 250Kb/s 98 * 100 168.7ns 99 * 101 208.3ns 100 * 110 208.3ns 101 * 111 0.0ns 102 */ 103 # define FDC_DSR_ZERO 0x20 /* Undef; should be 0 */ 104 # define FDC_DSR_LOWPWR 0x40 /* Low Power Mode */ 105 # define FDC_DSR_SWRST 0x80 /* Software Reset */ 106 107 #define FDC_FIFO 5 /* (R/W) Data Register (FIFO) */ 108 109 /* 110 * Commands 111 */ 112 #define FDC_CMD_MODE (0x01) 113 #define FDC_CMD_READ_TRACK(mfm) (0x02|mfm) 114 #define FDC_CMD_SPECIFY (0x03) 115 #define FDC_CMD_SENSE_DRIVE_STATUS (0x04) 116 #define FDC_CMD_WRITE_DATA(mt,mfm) (0x05|mt|mfm) 117 #define FDC_CMD_READ_DATA(mt,mfm,sk) (0x06|mt|mfm|sk) 118 #define FDC_CMD_RECALIBRATE (0x07) 119 #define FDC_CMD_SENSE_INTERRUPT (0x08) 120 #define FDC_CMD_WRITE_DEL_DATA(mt,mfm) (0x09|mt|mfm) 121 #define FDC_CMD_READ_ID(mfm) (0x0a|mfm) 122 #define FDC_CMD_READ_DEL_DATA(mt,mfm,sk) (0x0c|mt|mfm|sk) 123 #define FDC_CMD_FORMAT_TRACK(mfm) (0x0d|mfm) 124 #define FDC_CMD_DUMPREG (0x0e) 125 #define FDC_CMD_SEEK (0x0f) 126 #define FDC_CMD_VERSION (0x10) 127 #define FDC_CMD_SCAN_EQUAL(mt,mfm,sk) (0x11|mt|mfm|sk) 128 #define FDC_CMD_PERPENDICULAR (0x12) 129 #define FDC_CMD_CONFIGURE (0x13) 130 #define FDC_CMD_LOCK(lock) (0x14|lock) 131 #define FDC_CMD_VERIFY(mt,mfm,sk) (0x16|mt|mfm|sk) 132 #define FDC_CMD_NSC (0x18) 133 #define FDC_CMD_SCAN_LO_EQUAL(mt,mfm,sk) (0x19|mt|mfm|sk) 134 #define FDC_CMD_SCAN_HI_EQUAL(mt,mfm,sk) (0x1d|mt|mfm|sk) 135 #define FDC_CMD_SET_TRACK(wnr) (0x21|wnr) 136 #define FDC_CMD_REL_SEEK(dir) (0x8f|dir) 137 138 #define FDC_CMD_CONFIGURE_FLAGS_POLL 0x10 139 #define FDC_CMD_CONFIGURE_FLAGS_FIFO 0x20 140 #define FDC_CMD_CONFIGURE_FLAGS_EIS 0x40 141 #define FDC_CMD_FLAGS_LOCK 0x80 142 #define FDC_CMD_FLAGS_MT 0x80 143 #define FDC_CMD_FLAGS_MFM 0x40 144 #define FDC_CMD_FLAGS_SK 0x20 145 #define FDC_CMD_FLAGS_DIR 0x40 146 #define FDC_CMD_FLAGS_WNR 0x40 147 /* 148 * Command Status 149 */ 150 /* Status register ST0 */ 151 #define FDC_ST0BITS "\020\010invld\007abnrml\006seek_cmplt\005drv_chck\004drive_rdy\003top_head\002ds1\001ds0" 152 # define FDC_ST0_DS0 0x01 /* Drive Select 0 */ 153 # define FDC_ST0_DS1 0x02 /* Drive Select 1 */ 154 # define FDC_ST0_HDS 0x04 /* Head select */ 155 # define FDC_ST0_ZERO 0x08 /* Undef; should be 0 */ 156 # define FDC_ST0_EC 0x10 /* Equipment check */ 157 # define FDC_ST0_SE 0x20 /* Seek completed */ 158 # define FDC_ST0_IC0 0x40 /* Interrupt code 0 */ 159 # define FDC_ST0_IC1 0x80 /* Interrupt code 1 */ 160 # define FDC_ST0(a) (a & ~(FDC_ST0_DS0|FDC_ST0_DS1|FDC_ST0_HDS)) 161 # define FDC_ST0_NRML 0x00 /* Normal Completion */ 162 # define FDC_ST0_ABNR 0x40 /* Abnormal Termination */ 163 # define FDC_ST0_INVL 0x80 /* Invalid Command */ 164 # define FDC_ST0_CHGD 0xc0 /* Drive status changed */ 165 166 /* Status register ST1 */ 167 #define FDC_ST1BITS "\020\010end_of_cyl\006bad_crc\005data_overrun\003sec_not_fnd\002write_protect\001no_am" 168 # define FDC_ST1_MA 0x01 /* Missing address mark */ 169 # define FDC_ST1_NW 0x02 /* Write Protect */ 170 # define FDC_ST1_ND 0x04 /* No Data */ 171 # define FDC_ST1_ZERO0 0x08 /* Undef; should be 0 */ 172 # define FDC_ST1_OR 0x10 /* Overrun error */ 173 # define FDC_ST1_CE 0x20 /* CRC error */ 174 # define FDC_ST1_ZERO1 0x40 /* Undef; should be 0 */ 175 # define FDC_ST1_ET 0x80 /* End of Track */ 176 177 /* Status register ST2 */ 178 #define FDC_ST2BITS "\020\007ctrl_mrk\006bad_crc\005wrong_cyl\004scn_eq\003scn_not_fnd\002bad_cyl\001no_dam" 179 # define FDC_ST2_MD 0x01 /* Missing Address Mark */ 180 # define FDC_ST2_BT 0x02 /* Bad Track */ 181 # define FDC_ST2_SNS 0x04 /* Scan Not Satisfied */ 182 # define FDC_ST2_SEH 0x08 /* Scan Equal Hit */ 183 # define FDC_ST2_WT 0x10 /* Wrong Track */ 184 # define FDC_ST2_CD 0x20 /* CRC Error in Data */ 185 # define FDC_ST2_CM 0x40 /* Control Mark */ 186 # define FDC_ST2_ZERO 0x80 /* Undef; should be 0 */ 187 188 /* Status register ST3 */ 189 #define FDC_ST3BITS "\020\010fault\007write_protect\006drdy\005tk0\004two_side\003side_sel\002ds1\001ds0" 190 # define FDC_ST3_DS0 0x01 /* Drive Select 0 */ 191 # define FDC_ST3_DS1 0x02 /* Drive Select 1 */ 192 # define FDC_ST3_HDS 0x04 /* Head Select */ 193 # define FDC_ST3_ONE0 0x08 /* Undef; should be 0 */ 194 # define FDC_ST3_TK0 0x10 /* Track 0 */ 195 # define FDC_ST3_ONE1 0x20 /* Undef; should be 0 */ 196 # define FDC_ST3_WP 0x40 /* Write Protect */ 197 # define FDC_ST3_ZERO 0x80 /* Undef; should be 0 */ 198 199 #define FDC_NONE 6 /* (X) None (Bus TRI-STATE) */ 200 201 #define FDC_DIR 7 /* (R) Digital Input Register */ 202 # define FDC_DIR_DSKCHG 0x80 /* Disk Changed */ 203 204 #define FDC_CCR 7 /* (W) Configuration Register */ 205 # define FDC_CCR_DRATE0 0x01 /* Data Rate Select 0 */ 206 # define FDC_CCR_DRATE1 0x02 /* Data Rate Select 0 */ 207 # define FDC_CCR_ZERO0 0x04 /* Undef; should be 0 */ 208 # define FDC_CCR_ZERO1 0x08 /* Undef; should be 0 */ 209 # define FDC_CCR_ZERO2 0x10 /* Undef; should be 0 */ 210 # define FDC_CCR_ZERO3 0x20 /* Undef; should be 0 */ 211 # define FDC_CCR_ZERO4 0x40 /* Undef; should be 0 */ 212 # define FDC_CCR_ZERO5 0x80 /* Undef; should be 0 */ 213 214 #define FDC_NPORT 8 215
Indexes created Tue Sep 30 11:09:46 GMT 2025