oosiopreg.h revision 1.1
1 /* $NetBSD: oosiopreg.h,v 1.1 2003/04/06 09:48:43 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)siopreg.h 7.3 (Berkeley) 2/5/91 39 */ 40 41 /* 42 * NCR 53C700 SCSI interface hardware description. 43 * 44 * From the Mach scsi driver for the 53C700 and amiga siop driver 45 */ 46 47 #define OOSIOP_SCNTL0 0x00 /* rw: SCSI control reg 0 */ 48 #define OOSIOP_SCNTL1 0x01 /* rw: SCSI control reg 1 */ 49 #define OOSIOP_SDID 0x02 /* rw: SCSI destination ID */ 50 #define OOSIOP_SIEN 0x03 /* rw: SCSI interrupt enable */ 51 #define OOSIOP_SCID 0x04 /* rw: SCSI Chip ID reg */ 52 #define OOSIOP_SXFER 0x05 /* rw: SCSI Transfer reg */ 53 #define OOSIOP_SODL 0x06 /* rw: SCSI Output Data Latch */ 54 #define OOSIOP_SOCL 0x07 /* rw: SCSI Output Control Latch */ 55 #define OOSIOP_SFBR 0x08 /* ro: SCSI First Byte Received */ 56 #define OOSIOP_SIDL 0x09 /* ro: SCSI Input Data Latch */ 57 #define OOSIOP_SBDL 0x0a /* ro: SCSI Bus Data Lines */ 58 #define OOSIOP_SBCL 0x0b /* rw: SCSI Bus Control Lines */ 59 #define OOSIOP_DSTAT 0x0c /* ro: DMA status */ 60 #define OOSIOP_SSTAT0 0x0d /* ro: SCSI status reg 0 */ 61 #define OOSIOP_SSTAT1 0x0e /* ro: SCSI status reg 1 */ 62 #define OOSIOP_SSTAT2 0x0f /* ro: SCSI status reg 2 */ 63 #define OOSIOP_SCRA0 0x10 /* rw: Scratch A */ 64 #define OOSIOP_SCRA1 0x11 65 #define OOSIOP_SCRA2 0x12 66 #define OOSIOP_SCRA3 0x13 67 #define OOSIOP_CTEST0 0x14 /* ro: Chip test register 0 */ 68 #define OOSIOP_CTEST1 0x15 /* ro: Chip test register 1 */ 69 #define OOSIOP_CTEST2 0x16 /* ro: Chip test register 2 */ 70 #define OOSIOP_CTEST3 0x17 /* ro: Chip test register 3 */ 71 #define OOSIOP_CTEST4 0x18 /* rw: Chip test register 4 */ 72 #define OOSIOP_CTEST5 0x19 /* rw: Chip test register 5 */ 73 #define OOSIOP_CTEST6 0x1a /* rw: Chip test register 6 */ 74 #define OOSIOP_CTEST7 0x1b /* rw: Chip test register 7 */ 75 #define OOSIOP_TEMP 0x1c /* rw: Temporary Stack reg */ 76 #define OOSIOP_DFIFO 0x20 /* rw: DMA FIFO */ 77 #define OOSIOP_ISTAT 0x21 /* rw: Interrupt Status reg */ 78 #define OOSIOP_CTEST8 0x22 /* rw: Chip test register 8 */ 79 #define OOSIOP_CTEST9 0x23 /* ro: Chip test register 9 */ 80 #define OOSIOP_DBC 0x24 /* rw: DMA Byte Counter reg */ 81 #define OOSIOP_DCMD 0x27 /* rw: DMA Command Register */ 82 #define OOSIOP_DNAD 0x28 /* rw: DMA Next Address */ 83 #define OOSIOP_DSP 0x2c /* rw: DMA SCRIPTS Pointer reg */ 84 #define OOSIOP_DSPS 0x30 /* rw: DMA SCRIPTS Pointer Save reg */ 85 #define OOSIOP_DMODE 0x34 /* rw: DMA Mode reg */ 86 #define OOSIOP_RES35 0x35 87 #define OOSIOP_RES36 0x36 88 #define OOSIOP_RES37 0x37 89 #define OOSIOP_RES38 0x38 90 #define OOSIOP_DIEN 0x39 /* rw: DMA Interrupt Enable */ 91 #define OOSIOP_DWT 0x3a /* rw: DMA Watchdog Timer */ 92 #define OOSIOP_DCNTL 0x3b /* rw: DMA Control reg */ 93 #define OOSIOP_SCRB0 0x3c /* rw: Scratch B */ 94 #define OOSIOP_SCRB1 0x3d 95 #define OOSIOP_SCRB2 0x3e 96 #define OOSIOP_SCRB3 0x3f 97 98 #define OOSIOP_NREGS 0x40 99 100 101 /* 102 * Register defines 103 */ 104 105 /* Scsi control register 0 (scntl0) */ 106 107 #define OOSIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ 108 #define OOSIOP_ARB_SIMPLE 0x00 109 #define OOSIOP_ARB_FULL 0xc0 110 #define OOSIOP_SCNTL0_START 0x20 /* Start Sequence */ 111 #define OOSIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ 112 #define OOSIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ 113 #define OOSIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ 114 #define OOSIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ 115 #define OOSIOP_SCNTL0_TRG 0x01 /* Target Mode */ 116 117 /* Scsi control register 1 (scntl1) */ 118 119 #define OOSIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ 120 #define OOSIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ 121 #define OOSIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ 122 #define OOSIOP_SCNTL1_CON 0x10 /* Connected */ 123 #define OOSIOP_SCNTL1_RST 0x08 /* Assert RST */ 124 #define OOSIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */ 125 #define OOSIOP_SCNTL1_SND 0x02 /* Start Send operation */ 126 #define OOSIOP_SCNTL1_RCV 0x01 /* Start Receive operation */ 127 128 /* Scsi interrupt enable register (sien) */ 129 130 #define OOSIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ 131 #define OOSIOP_SIEN_FC 0x40 /* Function Complete */ 132 #define OOSIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ 133 #define OOSIOP_SIEN_SEL 0x10 /* (Re)Selected */ 134 #define OOSIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ 135 #define OOSIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ 136 #define OOSIOP_SIEN_RST 0x02 /* RST asserted */ 137 #define OOSIOP_SIEN_PAR 0x01 /* Parity Error */ 138 139 /* Scsi chip ID (scid) */ 140 141 #define OOSIOP_SCID_VALUE(i) (1 << i) 142 143 /* Scsi transfer register (sxfer) */ 144 145 #define OOSIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ 146 ATN asserted */ 147 #define OOSIOP_SXFER_TP 0x70 /* Synch Transfer Period */ 148 /* see specs for formulas: 149 Period = TCP * (4 + XFERP ) 150 TCP = 1 + CLK + 1..2; 151 */ 152 #define OOSIOP_SXFER_MO 0x0f /* Synch Max Offset */ 153 #define OOSIOP_MAX_OFFSET 8 154 155 /* Scsi output data latch register (sodl) */ 156 157 /* Scsi output control latch register (socl) */ 158 159 #define OOSIOP_REQ 0x80 /* SCSI signal <x> asserted */ 160 #define OOSIOP_ACK 0x40 161 #define OOSIOP_BSY 0x20 162 #define OOSIOP_SEL 0x10 163 #define OOSIOP_ATN 0x08 164 #define OOSIOP_MSG 0x04 165 #define OOSIOP_CD 0x02 166 #define OOSIOP_IO 0x01 167 168 #define OOSIOP_PHASE(socl) SCSI_PHASE(socl) 169 170 /* Scsi first byte received register (sfbr) */ 171 172 /* Scsi input data latch register (sidl) */ 173 174 /* Scsi bus data lines register (sbdl) */ 175 176 /* Scsi bus control lines register (sbcl). Same as socl */ 177 178 #define OOSIOP_SBCL_SSCF1 0x02 /* wo */ 179 #define OOSIOP_SBCL_SSCF0 0x01 /* wo */ 180 181 /* DMA status register (dstat) */ 182 183 #define OOSIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ 184 #define OOSIOP_DSTAT_ABRT 0x10 /* Aborted */ 185 #define OOSIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ 186 #define OOSIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ 187 #define OOSIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ 188 #define OOSIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */ 189 190 /* Scsi status register 0 (sstat0) */ 191 192 #define OOSIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ 193 #define OOSIOP_SSTAT0_FC 0x40 /* Function Complete */ 194 #define OOSIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ 195 #define OOSIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ 196 #define OOSIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ 197 #define OOSIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ 198 #define OOSIOP_SSTAT0_RST 0x02 /* RST asserted */ 199 #define OOSIOP_SSTAT0_PAR 0x01 /* Parity Error */ 200 201 /* Scsi status register 1 (sstat1) */ 202 203 #define OOSIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ 204 #define OOSIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ 205 #define OOSIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ 206 #define OOSIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ 207 #define OOSIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ 208 #define OOSIOP_SSTAT1_WOA 0x04 /* Won arbitration */ 209 #define OOSIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ 210 #define OOSIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ 211 212 /* Scsi status register 2 (sstat2) */ 213 214 #define OOSIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 215 #define OOSIOP_SCSI_FIFO_DEEP 8 216 #define OOSIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ 217 #define OOSIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ 218 #define OOSIOP_SSTAT2_CD 0x02 219 #define OOSIOP_SSTAT2_IO 0x01 220 221 /* Chip test register 0 (ctest0) */ 222 223 #define OOSIOP_CTEST0_RTRG 0x02 /* Real Target Mode */ 224 #define OOSIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ 225 226 /* Chip test register 1 (ctest1) */ 227 228 #define OOSIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom 229 (high->byte3) */ 230 #define OOSIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ 231 232 /* Chip test register 2 (ctest2) */ 233 234 #define OOSIOP_CTEST2_SOFF 0x20 /* Synch Offset compare 235 (1-> zero Init, max Tgt) */ 236 #define OOSIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ 237 #define OOSIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ 238 #define OOSIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ 239 #define OOSIOP_CTEST2_DREQ 0x02 /* DREQ status */ 240 #define OOSIOP_CTEST2_DACK 0x01 /* DACK status */ 241 242 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */ 243 244 /* Chip test register 4 (ctest4) */ 245 246 #define OOSIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ 247 #define OOSIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ 248 #define OOSIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */ 249 #define OOSIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ 250 #define OOSIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select 251 (from ctest6) 4->0, .. 7->3 */ 252 253 /* Chip test register 5 (ctest5) */ 254 255 #define OOSIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ 256 #define OOSIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ 257 #define OOSIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ 258 #define OOSIOP_CTEST5_MASR 0x10 /* Master set/reset pulses 259 (of bits 3-0) */ 260 #define OOSIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ 261 #define OOSIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ 262 #define OOSIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ 263 #define OOSIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ 264 265 /* Chip test register 6 (ctest6) DMA FIFO access */ 266 267 /* Chip test register 7 (ctest7) */ 268 269 #define OOSIOP_CTEST7_STD 0x10 /* Selection timeout disable */ 270 #define OOSIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ 271 #define OOSIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ 272 #define OOSIOP_CTEST7_DIFF 0x01 /* Differential mode */ 273 274 /* DMA FIFO register (dfifo) */ 275 276 #define OOSIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */ 277 #define OOSIOP_DFIFO_CLF 0x40 /* Clear DMA and SCSI FIFOs */ 278 #define OOSIOP_DFIFO_BO 0x3f /* FIFO byte offset counter */ 279 280 /* Interrupt status register (istat) */ 281 282 #define OOSIOP_ISTAT_ABRT 0x80 /* Abort operation */ 283 #define OOSIOP_ISTAT_CON 0x08 /* Connected */ 284 #define OOSIOP_ISTAT_PRE 0x04 /* Pointer register empty */ 285 #define OOSIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ 286 #define OOSIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ 287 288 /* Chip test register 8 (ctest8) */ 289 290 /* DMA Byte Counter register (dbc) */ 291 #define OOSIOP_DBC_MAX 0x00ffffff 292 293 /* DMA Mode register (dmode) */ 294 295 #define OOSIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */ 296 #define OOSIOP_DMODE_BL_1 0x00 297 #define OOSIOP_DMODE_BL_2 0x40 298 #define OOSIOP_DMODE_BL_4 0x80 299 #define OOSIOP_DMODE_BL_8 0xc0 300 #define OOSIOP_DMODE_BW16 0x20 /* Bus Width is 16 bits */ 301 #define OOSIOP_DMODE_286 0x10 /* 286 mode */ 302 #define OOSIOP_DMODE_IO_M 0x08 /* xfer data to memory or I/O space */ 303 #define OOSIOP_DMODE_FAM 0x04 /* fixed address mode */ 304 #define OOSIOP_DMODE_PIPE 0x02 /* SCRIPTS in Pipeline mode */ 305 #define OOSIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */ 306 307 /* DMA interrupt enable register (dien) */ 308 309 #define OOSIOP_DIEN_BF 0x20 /* On Bus Fault */ 310 #define OOSIOP_DIEN_ABRT 0x10 /* On Abort */ 311 #define OOSIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ 312 #define OOSIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ 313 #define OOSIOP_DIEN_WTD 0x02 /* On watchdog timeout */ 314 #define OOSIOP_DIEN_IID 0x01 /* On illegal instruction detected */ 315 316 /* DMA control register (dcntl) */ 317 318 #define OOSIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: */ 319 #define OOSIOP_DCNTL_CF_2 0x00 /* 0 --> 37.51..50.00 MHz, div=2 */ 320 #define OOSIOP_DCNTL_CF_1_5 0x40 /* 1 --> 25.01..37.50 MHz, div=1.5 */ 321 #define OOSIOP_DCNTL_CF_1 0x80 /* 2 --> 16.67..25.00 MHz, div=1 */ 322 #define OOSIOP_DCNTL_CF_3 0xc0 /* 3 --> 50.01..66.67 MHz, div=3 */ 323 #define OOSIOP_DCNTL_S16 0x20 /* SCRIPTS fetches 16bits at a time */ 324 #define OOSIOP_DCNTL_SSM 0x10 /* Single step mode */ 325 #define OOSIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */ 326 #define OOSIOP_DCNTL_STD 0x04 /* Start DMA operation */ 327 #define OOSIOP_DCNTL_RST 0x01 /* Software reset */ 328
Indexes created Mon Sep 29 21:09:56 GMT 2025