1 /* $NetBSD: rtl80x9reg.h,v 1.7 2008/04/28 20:23:51 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Registers on Realtek 8019 and 8029 NE2000-compatible network interfaces. 35 * 36 * Data sheets for these chips can be found at: 37 * 38 * http://www.realtek.com.tw 39 */ 40 41 #ifndef _DEV_IC_RTL80x9_REG_H_ 42 #define _DEV_IC_RTL80x9_REG_H_ 43 44 /* 45 * Page 0 register offsets. 46 */ 47 #define NERTL_RTL0_8019ID0 0x0a /* 8019 ID Register 0 */ 48 #define RTL0_8019ID0 'P' 49 50 #define NERTL_RTL0_8019ID1 0x0b /* 8019 ID Register 1 */ 51 #define RTL0_8019ID1 'p' 52 53 /* 54 * Page 3 register offsets. 55 */ 56 #define NERTL_RTL3_EECR 0x01 /* EEPROM Command Register */ 57 #define RTL3_EECR_EEM1 0x80 /* EEPROM Operating Mode */ 58 #define RTL3_EECR_EEM0 0x40 59 /* 0 0 Normal operation */ 60 /* 0 1 Auto-load */ 61 /* 1 0 9346 programming */ 62 /* 1 1 Config register write enab */ 63 #define RTL3_EECR_EECS 0x08 /* EEPROM Chip Select */ 64 #define RTL3_EECR_EESK 0x04 /* EEPROM Clock */ 65 #define RTL3_EECR_EEDI 0x02 /* EEPROM Data In */ 66 #define RTL3_EECR_EEDO 0x01 /* EEPROM Data Out */ 67 68 #define NERTL_RTL3_BPAGE 0x02 /* BROM Page Register (8019) */ 69 70 #define NERTL_RTL3_CONFIG0 0x03 /* Configuration 0 (ro) */ 71 #define RTL3_CONFIG0_JP 0x08 /* jumper mode (8019) */ 72 #define RTL3_CONFIG0_BNC 0x04 /* BNC is active */ 73 74 #define NERTL_RTL3_CONFIG1 0x04 /* Configuration 1 (8019) */ 75 #define RTL3_CONFIG1_IRQEN 0x80 /* IRQ Enable */ 76 #define RTL3_CONFIG1_IRQS2 0x40 /* IRQ Select */ 77 #define RTL3_CONFIG1_IRQS1 0x20 78 #define RTL3_CONFIG1_IRQS0 0x10 79 /* 0 0 0 int 0 irq 2/9 */ 80 /* 0 0 1 int 1 irq 3 */ 81 /* 0 1 0 int 2 irq 4 */ 82 /* 0 1 1 int 3 irq 5 */ 83 /* 1 0 0 int 4 irq 10 */ 84 /* 1 0 1 int 5 irq 11 */ 85 /* 1 1 0 int 6 irq 12 */ 86 /* 1 1 1 int 7 irq 15 */ 87 #define RTL_CONFIG1_IOS3 0x08 /* I/O base Select */ 88 #define RTL_CONFIG1_IOS2 0x04 89 #define RTL_CONFIG1_IOS1 0x02 90 #define RTL_CONFIG1_IOS0 0x01 91 /* 0 0 0 0 0x300 */ 92 /* 0 0 0 1 0x320 */ 93 /* 0 0 1 0 0x340 */ 94 /* 0 0 1 1 0x360 */ 95 /* 0 1 0 0 0x380 */ 96 /* 0 1 0 1 0x3a0 */ 97 /* 0 1 1 0 0x3c0 */ 98 /* 0 1 1 1 0x3e0 */ 99 /* 1 0 0 0 0x200 */ 100 /* 1 0 0 1 0x220 */ 101 /* 1 0 1 0 0x240 */ 102 /* 1 0 1 1 0x260 */ 103 /* 1 1 0 0 0x280 */ 104 /* 1 1 0 1 0x2a0 */ 105 /* 1 1 1 0 0x2c0 */ 106 /* 1 1 1 1 0x2e0 */ 107 108 #define NERTL_RTL3_CONFIG2 0x05 /* Configuration 2 */ 109 #define RTL3_CONFIG2_PL1 0x80 /* Network media type */ 110 #define RTL3_CONFIG2_PL0 0x40 111 /* 0 0 TP/CX auto-detect */ 112 /* 0 1 10baseT */ 113 /* 1 0 10base5 */ 114 /* 1 1 10base2 */ 115 #define RTL3_CONFIG2_8029FCE 0x20 /* Flow Control Enable */ 116 #define RTL3_CONFIG2_8029PF 0x10 /* Pause Flag */ 117 #define RTL3_CONFIG2_8029BS1 0x02 /* Boot Rom Size */ 118 #define RTL3_CONFIG2_8029BS0 0x01 119 /* 0 0 No Boot Rom */ 120 /* 0 1 8k */ 121 /* 1 0 16k */ 122 /* 1 1 32k */ 123 #define RTL3_CONFIG2_8019BSELB 0x20 /* BROM disable */ 124 #define RTL3_CONFIG2_8019BS4 0x10 /* BROM size/base */ 125 #define RTL3_CONFIG2_8019BS3 0x08 126 #define RTL3_CONFIG2_8019BS2 0x04 127 #define RTL3_CONFIG2_8019BS1 0x02 128 #define RTL3_CONFIG2_8019BS0 0x01 129 130 #define NERTL_RTL3_CONFIG3 0x06 /* Configuration 3 */ 131 #define RTL3_CONFIG3_8019PNP 0x80 /* PnP Mode */ 132 #define RTL3_CONFIG3_FUDUP 0x40 /* Full Duplex */ 133 #define RTL3_CONFIG3_LEDS1 0x20 /* LED1/2 pin configuration */ 134 /* 0 LED1 == LED_RX, LED2 == LED_TX */ 135 /* 1 LED1 == LED_CRS, LED2 == MCSB */ 136 #define RTL3_CONFIG3_LEDS0 0x10 /* LED0 pin configuration */ 137 /* 0 LED0 pin == LED_COL */ 138 /* 1 LED0 pin == LED_LINK */ 139 #define RTL3_CONFIG3_SLEEP 0x04 /* Sleep mode */ 140 #define RTL3_CONFIG3_PWRDN 0x02 /* Power Down */ 141 #define RTL3_CONFIG3_8019ACTIVEB 0x01 /* inverse of bit 0 in PnP Act Reg */ 142 143 #define NERTL_RTL3_CSNSAV 0x08 /* CSN Save Register (8019) */ 144 145 #define NERTL_RTL3_HLTCLK 0x09 /* Halt Clock */ 146 #define RTL3_HLTCLK_RUNNING 'R' /* clock runs in power down */ 147 #define RTL3_HLTCLK_HALTED 'H' /* clock halted in power down */ 148 149 #define NERTL_RTL3_INTR 0x0b /* ISA bus states of INT7-0 (8019) */ 150 151 #define NERTL_RTL3_8029ID0 0x0e /* ID register 0 */ 152 153 #define NERTL_RTL3_8029ID1 0x0f /* ID register 1 */ 154 155 #endif /* _DEV_IC_RTL80x9_REG_H_ */ 156
Indexes created Sun Sep 21 16:09:51 GMT 2025